src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 static bool do_sync;
  57
  58 static void swd_finish_read(struct adiv5_dap *dap)
  59 {
  60         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  61         if (dap->last_read != NULL) {
  62                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  63                 dap->last_read = NULL;
  64         }
  65 }
  66
  67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  68                 uint32_t data);
  69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  70                 uint32_t *data);
  71
  72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  73 {
  74         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  75         assert(swd);
  76
  77         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  78                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  79 }
  80
  81 static int swd_run_inner(struct adiv5_dap *dap)
  82 {
  83         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  84         int retval;
  85
  86         retval = swd->run();
  87
  88         if (retval != ERROR_OK) {
  89                 /* fault response */
  90                 dap->do_reconnect = true;
  91         }
  92
  93         return retval;
  94 }
  95
  96 static int swd_connect(struct adiv5_dap *dap)
  97 {
  98         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  99         uint32_t dpidr = 0xdeadbeef;
 100         int status;
 101
 102         /* FIXME validate transport config ... is the
 103          * configured DAP present (check IDCODE)?
 104          * Is *only* one DAP configured?
 105          *
 106          * MUST READ DPIDR
 107          */
 108
 109         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 110         if (!dap->do_reconnect) {
 111                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 112
 113                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 114                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 115                                 adapter_assert_reset();
 116                         else
 117                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 118                 }
 119         }
 120
 121
 122         int64_t timeout = timeval_ms() + 500;
 123
 124         do {
 125                 /* Note, debugport_init() does setup too */
 126                 swd->switch_seq(JTAG_TO_SWD);
 127
 128                 /* Clear link state, including the SELECT cache. */
 129                 dap->do_reconnect = false;
 130                 dap_invalidate_cache(dap);
 131
 132                 status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 133                 if (status == ERROR_OK) {
 134                         status = swd_run_inner(dap);
 135                         if (status == ERROR_OK)
 136                                 break;
 137                 }
 138
 139                 alive_sleep(1);
 140
 141         } while (timeval_ms() < timeout);
 142
 143         if (status != ERROR_OK) {
 144                 LOG_ERROR("Error connecting DP: cannot read IDR");
 145                 return status;
 146         }
 147
 148         LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 149
 150         do {
 151                 dap->do_reconnect = false;
 152
 153                 /* force clear all sticky faults */
 154                 swd_clear_sticky_errors(dap);
 155
 156                 status = swd_run_inner(dap);
 157                 if (status != ERROR_WAIT)
 158                         break;
 159
 160                 alive_sleep(10);
 161
 162         } while (timeval_ms() < timeout);
 163
 164         /* IHI 0031E B4.3.2:
 165          * "A WAIT response must not be issued to the ...
 166          * ... writes to the ABORT register"
 167          * swd_clear_sticky_errors() writes to the ABORT register only.
 168          *
 169          * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
 170          * in a corner case. Just try if ABORT resolves the problem.
 171          */
 172         if (status == ERROR_WAIT) {
 173                 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
 174
 175                 dap->do_reconnect = false;
 176
 177                 swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 178                         DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 179                 status = swd_run_inner(dap);
 180         }
 181
 182         if (status == ERROR_OK)
 183                 status = dap_dp_init(dap);
 184
 185         return status;
 186 }
 187
 188 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
 189 {
 190         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 191         assert(swd);
 192
 193         return swd->switch_seq(seq);
 194 }
 195
 196 static inline int check_sync(struct adiv5_dap *dap)
 197 {
 198         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 199 }
 200
 201 static int swd_check_reconnect(struct adiv5_dap *dap)
 202 {
 203         if (dap->do_reconnect)
 204                 return swd_connect(dap);
 205
 206         return ERROR_OK;
 207 }
 208
 209 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 210 {
 211         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 212         assert(swd);
 213
 214         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 215                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 216         return check_sync(dap);
 217 }
 218
 219 /** Select the DP register bank matching bits 7:4 of reg. */
 220 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 221 {
 222         /* Only register address 4 is banked. */
 223         if ((reg & 0xf) != 4)
 224                 return ERROR_OK;
 225
 226         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 227         uint32_t sel = select_dp_bank
 228                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 229
 230         if (sel == dap->select)
 231                 return ERROR_OK;
 232
 233         dap->select = sel;
 234
 235         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 236         if (retval != ERROR_OK)
 237                 dap->select = DP_SELECT_INVALID;
 238
 239         return retval;
 240 }
 241
 242 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 243                 uint32_t *data)
 244 {
 245         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 246         assert(swd);
 247
 248         int retval = swd_check_reconnect(dap);
 249         if (retval != ERROR_OK)
 250                 return retval;
 251
 252         retval = swd_queue_dp_bankselect(dap, reg);
 253         if (retval != ERROR_OK)
 254                 return retval;
 255
 256         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 257
 258         return check_sync(dap);
 259 }
 260
 261 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 262                 uint32_t data)
 263 {
 264         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 265         assert(swd);
 266
 267         int retval = swd_check_reconnect(dap);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270
 271         swd_finish_read(dap);
 272         if (reg == DP_SELECT) {
 273                 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
 274
 275                 swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 276
 277                 retval = check_sync(dap);
 278                 if (retval != ERROR_OK)
 279                         dap->select = DP_SELECT_INVALID;
 280
 281                 return retval;
 282         }
 283
 284         retval = swd_queue_dp_bankselect(dap, reg);
 285         if (retval != ERROR_OK)
 286                 return retval;
 287
 288         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 289
 290         return check_sync(dap);
 291 }
 292
 293 /** Select the AP register bank matching bits 7:4 of reg. */
 294 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 295 {
 296         struct adiv5_dap *dap = ap->dap;
 297         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 298                         | (reg & 0x000000F0)
 299                         | (dap->select & DP_SELECT_DPBANK);
 300
 301         if (sel == dap->select)
 302                 return ERROR_OK;
 303
 304         dap->select = sel;
 305
 306         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 307         if (retval != ERROR_OK)
 308                 dap->select = DP_SELECT_INVALID;
 309
 310         return retval;
 311 }
 312
 313 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 314                 uint32_t *data)
 315 {
 316         struct adiv5_dap *dap = ap->dap;
 317         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 318         assert(swd);
 319
 320         int retval = swd_check_reconnect(dap);
 321         if (retval != ERROR_OK)
 322                 return retval;
 323
 324         retval = swd_queue_ap_bankselect(ap, reg);
 325         if (retval != ERROR_OK)
 326                 return retval;
 327
 328         swd->read_reg(swd_cmd(true,  true, reg), dap->last_read, ap->memaccess_tck);
 329         dap->last_read = data;
 330
 331         return check_sync(dap);
 332 }
 333
 334 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 335                 uint32_t data)
 336 {
 337         struct adiv5_dap *dap = ap->dap;
 338         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 339         assert(swd);
 340
 341         int retval = swd_check_reconnect(dap);
 342         if (retval != ERROR_OK)
 343                 return retval;
 344
 345         swd_finish_read(dap);
 346         retval = swd_queue_ap_bankselect(ap, reg);
 347         if (retval != ERROR_OK)
 348                 return retval;
 349
 350         swd->write_reg(swd_cmd(false,  true, reg), data, ap->memaccess_tck);
 351
 352         return check_sync(dap);
 353 }
 354
 355 /** Executes all queued DAP operations. */
 356 static int swd_run(struct adiv5_dap *dap)
 357 {
 358         swd_finish_read(dap);
 359         return swd_run_inner(dap);
 360 }
 361
 362 /** Put the SWJ-DP back to JTAG mode */
 363 static void swd_quit(struct adiv5_dap *dap)
 364 {
 365         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 366
 367         swd->switch_seq(SWD_TO_JTAG);
 368         /* flush the queue before exit */
 369         swd->run();
 370 }
 371
 372 const struct dap_ops swd_dap_ops = {
 373         .connect = swd_connect,
 374         .send_sequence = swd_send_sequence,
 375         .queue_dp_read = swd_queue_dp_read,
 376         .queue_dp_write = swd_queue_dp_write,
 377         .queue_ap_read = swd_queue_ap_read,
 378         .queue_ap_write = swd_queue_ap_write,
 379         .queue_ap_abort = swd_queue_ap_abort,
 380         .run = swd_run,
 381         .quit = swd_quit,
 382 };
 383
 384 static const struct command_registration swd_commands[] = {
 385         {
 386                 /*
 387                  * Set up SWD and JTAG targets identically, unless/until
 388                  * infrastructure improves ...  meanwhile, ignore all
 389                  * JTAG-specific stuff like IR length for SWD.
 390                  *
 391                  * REVISIT can we verify "just one SWD DAP" here/early?
 392                  */
 393                 .name = "newdap",
 394                 .jim_handler = jim_jtag_newtap,
 395                 .mode = COMMAND_CONFIG,
 396                 .help = "declare a new SWD DAP"
 397         },
 398         COMMAND_REGISTRATION_DONE
 399 };
 400
 401 static const struct command_registration swd_handlers[] = {
 402         {
 403                 .name = "swd",
 404                 .mode = COMMAND_ANY,
 405                 .help = "SWD command group",
 406                 .chain = swd_commands,
 407                 .usage = "",
 408         },
 409         COMMAND_REGISTRATION_DONE
 410 };
 411
 412 static int swd_select(struct command_context *ctx)
 413 {
 414         /* FIXME: only place where global 'adapter_driver' is still needed */
 415         extern struct adapter_driver *adapter_driver;
 416         const struct swd_driver *swd = adapter_driver->swd_ops;
 417         int retval;
 418
 419         retval = register_commands(ctx, NULL, swd_handlers);
 420         if (retval != ERROR_OK)
 421                 return retval;
 422
 423          /* be sure driver is in SWD mode; start
 424           * with hardware default TRN (1), it can be changed later
 425           */
 426         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 427                 LOG_DEBUG("no SWD driver?");
 428                 return ERROR_FAIL;
 429         }
 430
 431         retval = swd->init();
 432         if (retval != ERROR_OK) {
 433                 LOG_DEBUG("can't init SWD driver");
 434                 return retval;
 435         }
 436
 437         return retval;
 438 }
 439
 440 static int swd_init(struct command_context *ctx)
 441 {
 442         /* nothing done here, SWD is initialized
 443          * together with the DAP */
 444         return ERROR_OK;
 445 }
 446
 447 static struct transport swd_transport = {
 448         .name = "swd",
 449         .select = swd_select,
 450         .init = swd_init,
 451 };
 452
 453 static void swd_constructor(void) __attribute__((constructor));
 454 static void swd_constructor(void)
 455 {
 456         transport_register(&swd_transport);
 457 }
 458
 459 /** Returns true if the current debug session
 460  * is using SWD as its transport.
 461  */
 462 bool transport_is_swd(void)
 463 {
 464         return get_current_transport() == &swd_transport;
 465 }