src/target/arc.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013-2015,2019-2020 Synopsys, Inc.                      *
   3  *   Frank Dols <frank.dols@synopsys.com>                                  *
   4  *   Mischa Jonker <mischa.jonker@synopsys.com>                            *
   5  *   Anton Kolesov <anton.kolesov@synopsys.com>                            *
   6  *   Evgeniy Didin <didin@synopsys.com>                                    *
   7  *                                                                         *
   8  *   SPDX-License-Identifier: GPL-2.0-or-later                             *
   9  ***************************************************************************/
  10
  11 #ifndef OPENOCD_TARGET_ARC_H
  12 #define OPENOCD_TARGET_ARC_H
  13
  14 #include <helper/time_support.h>
  15 #include <jtag/jtag.h>
  16
  17 #include "algorithm.h"
  18 #include "breakpoints.h"
  19 #include "jtag/interface.h"
  20 #include "register.h"
  21 #include "target.h"
  22 #include "target_request.h"
  23 #include "target_type.h"
  24 #include "helper/bits.h"
  25
  26 #include "arc_jtag.h"
  27 #include "arc_cmd.h"
  28 #include "arc_mem.h"
  29
  30 #define ARC_COMMON_MAGIC        0xB32EB324  /* just a unique number */
  31
  32 #define AUX_DEBUG_REG                   0x5
  33 #define AUX_PC_REG                      0x6
  34 #define AUX_STATUS32_REG                0xA
  35
  36
  37 #define SET_CORE_FORCE_HALT             BIT(1)
  38 #define SET_CORE_HALT_BIT               BIT(0)      /* STATUS32[0] = H field */
  39 #define SET_CORE_ENABLE_INTERRUPTS      BIT(31)
  40 /* STATUS32[5] or AE bit indicates if the processor is in exception state */
  41 #define SET_CORE_AE_BIT                 BIT(5)
  42 /* Single instruction step bit in Debug register */
  43 #define SET_CORE_SINGLE_INSTR_STEP      BIT(11)
  44
  45 #define AUX_STATUS32_REG_HALT_BIT       BIT(0)
  46 #define AUX_STATUS32_REG_IE_BIT         BIT(31)    /* STATUS32[31] = IE field */
  47
  48 /* ARC register numbers */
  49 enum {
  50         ARC_R0,
  51         ARC_R1,
  52         ARC_R2,
  53         ARC_R3,
  54         ARC_R4,
  55         ARC_R5,
  56         ARC_R6,
  57         ARC_R7,
  58         ARC_R8,
  59         ARC_R9,
  60         ARC_R10,
  61         ARC_R11,
  62         ARC_R12,
  63         ARC_R13,
  64         ARC_R14,
  65         ARC_R15,
  66         ARC_R16,
  67         ARC_R17,
  68         ARC_R18,
  69         ARC_R19,
  70         ARC_R20,
  71         ARC_R21,
  72         ARC_R22,
  73         ARC_R23,
  74         ARC_R24,
  75         ARC_R25,
  76         ARC_GP          = 26,
  77         ARC_FP          = 27,
  78         ARC_SP          = 28,
  79         ARC_ILINK       = 29,
  80         ARC_R30,
  81         ARC_BLINK       = 31,
  82         ARC_LP_COUNT    = 60,
  83
  84         /* Reserved registers */
  85         ARC_R61         = 61,
  86         ARC_R62         = 62,
  87
  88         ARC_PCL         = 63,
  89         ARC_PC          = 64,
  90         ARC_LP_START    = 65,
  91         ARC_LP_END      = 66,
  92         ARC_STATUS32    = 67,
  93 };
  94
  95 #define CORE_REG_MAX_NUMBER             (63)
  96
  97 /* Limit reg_type/reg_type_field  name to 20 symbols */
  98 #define REG_TYPE_MAX_NAME_LENGTH        20
  99
 100 /* ARC 32bits opcodes */
 101 #define ARC_SDBBP_32 0x256F003FU  /* BRK */
 102
 103 /* ARC 16bits opcodes */
 104 #define ARC_SDBBP_16 0x7FFF      /* BRK_S */
 105
 106 /* Cache registers */
 107 #define AUX_IC_IVIC_REG                 0X10
 108 #define IC_IVIC_INVALIDATE              0XFFFFFFFF
 109
 110 #define AUX_DC_IVDC_REG                 0X47
 111 #define DC_IVDC_INVALIDATE              BIT(0)
 112 #define AUX_DC_CTRL_REG                 0X48
 113 #define DC_CTRL_IM                      BIT(6)
 114
 115 /* L2 cache registers */
 116 #define SLC_AUX_CACHE_CTRL              0x903
 117 #define L2_CTRL_IM                      BIT(6)
 118 #define L2_CTRL_BS                      BIT(8)          /* Busy flag */
 119 #define SLC_AUX_CACHE_FLUSH             0x904
 120 #define L2_FLUSH_FL                     BIT(0)
 121 #define SLC_AUX_CACHE_INV               0x905
 122 #define L2_INV_IV                       BIT(0)
 123
 124  /* Action Point */
 125 #define AP_AC_AT_INST_ADDR              0x0
 126 #define AP_AC_AT_MEMORY_ADDR    0x2
 127 #define AP_AC_AT_AUXREG_ADDR    0x4
 128
 129 #define AP_AC_TT_DISABLE                0x00
 130 #define AP_AC_TT_WRITE                  0x10
 131 #define AP_AC_TT_READ                   0x20
 132 #define AP_AC_TT_READWRITE              0x30
 133
 134 struct arc_reg_bitfield {
 135         struct reg_data_type_bitfield bitfield;
 136         char name[REG_TYPE_MAX_NAME_LENGTH];
 137 };
 138 /* Register data type */
 139 struct arc_reg_data_type {
 140         struct list_head list;
 141         struct reg_data_type data_type;
 142         struct reg_data_type_flags data_type_flags;
 143         struct reg_data_type_struct data_type_struct;
 144         char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
 145         struct arc_reg_bitfield *bitfields;
 146         union {
 147                 struct reg_data_type_struct_field *reg_type_struct_field;
 148                 struct reg_data_type_flags_field *reg_type_flags_field;
 149         };
 150 };
 151
 152 /* Standard GDB register types */
 153 static const struct reg_data_type standard_gdb_types[] = {
 154         { .type = REG_TYPE_INT,         .id = "int" },
 155         { .type = REG_TYPE_INT8,        .id = "int8" },
 156         { .type = REG_TYPE_INT16,       .id = "int16" },
 157         { .type = REG_TYPE_INT32,       .id = "int32" },
 158         { .type = REG_TYPE_INT64,       .id = "int64" },
 159         { .type = REG_TYPE_INT128,      .id = "int128" },
 160         { .type = REG_TYPE_UINT8,       .id = "uint8" },
 161         { .type = REG_TYPE_UINT16,      .id = "uint16" },
 162         { .type = REG_TYPE_UINT32,      .id = "uint32" },
 163         { .type = REG_TYPE_UINT64,      .id = "uint64" },
 164         { .type = REG_TYPE_UINT128,     .id = "uint128" },
 165         { .type = REG_TYPE_CODE_PTR,    .id = "code_ptr" },
 166         { .type = REG_TYPE_DATA_PTR,    .id = "data_ptr" },
 167         { .type = REG_TYPE_FLOAT,       .id = "float" },
 168         { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
 169         { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
 170 };
 171
 172 enum arc_actionpointype {
 173         ARC_AP_BREAKPOINT,
 174         ARC_AP_WATCHPOINT,
 175 };
 176
 177 /* Actionpoint related fields  */
 178 struct arc_actionpoint {
 179         int used;
 180         uint32_t bp_value;
 181         uint32_t reg_address;
 182         enum arc_actionpointype type;
 183 };
 184
 185 struct arc_common {
 186         uint32_t common_magic;
 187
 188         struct arc_jtag jtag_info;
 189
 190         struct reg_cache *core_and_aux_cache;
 191         struct reg_cache *bcr_cache;
 192
 193         /* Cache control */
 194         bool has_dcache;
 195         bool has_icache;
 196         bool has_l2cache;
 197         /* If true, then D$ has been already flushed since core has been
 198          * halted. */
 199         bool dcache_flushed;
 200         /* If true, then L2 has been already flushed since core has been
 201          * halted. */
 202         bool l2cache_flushed;
 203         /* If true, then caches have been already flushed since core has been
 204          * halted. */
 205         bool icache_invalidated;
 206         bool dcache_invalidated;
 207         bool l2cache_invalidated;
 208
 209         /* Indicate if cache was built (for deinit function) */
 210         bool core_aux_cache_built;
 211         bool bcr_cache_built;
 212         /* Closely Coupled memory(CCM) regions for performance-critical
 213          * code (optional). */
 214         uint32_t iccm0_start;
 215         uint32_t iccm0_end;
 216         uint32_t iccm1_start;
 217         uint32_t iccm1_end;
 218         uint32_t dccm_start;
 219         uint32_t dccm_end;
 220
 221         int irq_state;
 222
 223         /* Register descriptions */
 224         struct list_head reg_data_types;
 225         struct list_head core_reg_descriptions;
 226         struct list_head aux_reg_descriptions;
 227         struct list_head bcr_reg_descriptions;
 228         unsigned long num_regs;
 229         unsigned long num_core_regs;
 230         unsigned long num_aux_regs;
 231         unsigned long num_bcr_regs;
 232         unsigned long last_general_reg;
 233
 234         /* PC register location in register cache. */
 235         unsigned long pc_index_in_cache;
 236         /* DEBUG register location in register cache. */
 237         unsigned long debug_index_in_cache;
 238
 239         /* Actionpoints */
 240         unsigned int actionpoints_num;
 241         unsigned int actionpoints_num_avail;
 242         struct arc_actionpoint *actionpoints_list;
 243 };
 244
 245 /* Borrowed from nds32.h */
 246 #define CHECK_RETVAL(action)                    \
 247         do {                                    \
 248                 int __retval = (action);        \
 249                 if (__retval != ERROR_OK) {     \
 250                         LOG_DEBUG("error while calling \"%s\"", \
 251                                 # action);     \
 252                         return __retval;        \
 253                 }                               \
 254         } while (0)
 255
 256 #define JIM_CHECK_RETVAL(action)                \
 257         do {                                    \
 258                 int __retval = (action);        \
 259                 if (__retval != JIM_OK) {       \
 260                         LOG_DEBUG("error while calling \"%s\"", \
 261                                 # action);     \
 262                         return __retval;        \
 263                 }                               \
 264         } while (0)
 265
 266 static inline struct arc_common *target_to_arc(struct target *target)
 267 {
 268         return target->arch_info;
 269 }
 270
 271 /* ----- Inlined functions ------------------------------------------------- */
 272
 273 /**
 274  * Convert data in host endianness to the middle endian. This is required to
 275  * write 4-byte instructions.
 276  */
 277 static inline void arc_h_u32_to_me(uint8_t *buf, int val)
 278 {
 279         buf[1] = (uint8_t) (val >> 24);
 280         buf[0] = (uint8_t) (val >> 16);
 281         buf[3] = (uint8_t) (val >> 8);
 282         buf[2] = (uint8_t) (val >> 0);
 283 }
 284
 285 /**
 286  * Convert data in middle endian to host endian. This is required to read 32-bit
 287  * instruction from little endian ARCs.
 288  */
 289 static inline uint32_t arc_me_to_h_u32(const uint8_t *buf)
 290 {
 291         return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24);
 292 }
 293
 294
 295 /* ARC Register description */
 296 struct arc_reg_desc {
 297
 298         struct target *target;
 299
 300         /* Register name */
 301         char *name;
 302
 303         /* Actual place of storing reg_value */
 304         uint8_t reg_value[4];
 305
 306         /* Actual place of storing register feature */
 307         struct reg_feature feature;
 308
 309         /* GDB XML feature */
 310         char *gdb_xml_feature;
 311
 312         /* Is this a register in g/G-packet? */
 313         bool is_general;
 314
 315         /* Architectural number: core reg num or AUX reg num */
 316         uint32_t arch_num;
 317
 318         /* Core or AUX register? */
 319         bool is_core;
 320
 321         /* Build configuration register? */
 322         bool is_bcr;
 323
 324         /* Data type */
 325         struct reg_data_type *data_type;
 326
 327         struct list_head list;
 328 };
 329
 330 /* Error codes */
 331 #define ERROR_ARC_REGISTER_NOT_FOUND       (-700)
 332 #define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
 333 #define ERROR_ARC_REGISTER_IS_NOT_STRUCT   (-702)
 334 #define ERROR_ARC_FIELD_IS_NOT_BITFIELD    (-703)
 335 #define ERROR_ARC_REGTYPE_NOT_FOUND        (-704)
 336
 337 void free_reg_desc(struct arc_reg_desc *r);
 338
 339
 340 void arc_reg_data_type_add(struct target *target,
 341                 struct arc_reg_data_type *data_type);
 342
 343 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 344                 const char * const type_name, const size_t type_name_len);
 345
 346 struct reg *arc_reg_get_by_name(struct reg_cache *first,
 347                                         const char *name, bool search_all);
 348
 349 int arc_reg_get_field(struct target *target, const char *reg_name,
 350                 const char *field_name, uint32_t *value_ptr);
 351
 352 int arc_cache_flush(struct target *target);
 353 int arc_cache_invalidate(struct target *target);
 354
 355 int arc_add_auxreg_actionpoint(struct target *target,
 356         uint32_t auxreg_addr, uint32_t transaction);
 357 int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr);
 358 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num);
 359
 360 #endif /* OPENOCD_TARGET_ARC_H */