target: disable armv6m unaligned memory access
[openocd.git] / src / target / arm.h
1 /*
2 * Copyright (C) 2005 by Dominic Rath
3 * Dominic.Rath@gmx.de
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by √ėyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 */
26
27 #ifndef ARM_H
28 #define ARM_H
29
30 #include <helper/command.h>
31 #include "target.h"
32
33
34 /**
35 * @file
36 * Holds the interface to ARM cores.
37 *
38 * At this writing, only "classic ARM" cores built on the ARMv4 register
39 * and mode model are supported. The Thumb2-only microcontroller profile
40 * support has not yet been integrated, affecting Cortex-M parts.
41 */
42
43 /**
44 * Represent state of an ARM core.
45 *
46 * Most numbers match the five low bits of the *PSR registers on
47 * "classic ARM" processors, which build on the ARMv4 processor
48 * modes and register set.
49 *
50 * ARM_MODE_ANY is a magic value, often used as a wildcard.
51 *
52 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
53 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
54 * they support.
55 */
56 enum arm_mode {
57 ARM_MODE_USR = 16,
58 ARM_MODE_FIQ = 17,
59 ARM_MODE_IRQ = 18,
60 ARM_MODE_SVC = 19,
61 ARM_MODE_ABT = 23,
62 ARM_MODE_MON = 26,
63 ARM_MODE_UND = 27,
64 ARM_MODE_SYS = 31,
65
66 ARM_MODE_THREAD,
67 ARM_MODE_USER_THREAD,
68 ARM_MODE_HANDLER,
69
70 ARM_MODE_ANY = -1
71 };
72
73 const char *arm_mode_name(unsigned psr_mode);
74 bool is_arm_mode(unsigned psr_mode);
75
76 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
77 enum arm_state {
78 ARM_STATE_ARM,
79 ARM_STATE_THUMB,
80 ARM_STATE_JAZELLE,
81 ARM_STATE_THUMB_EE,
82 };
83
84 #define ARM_COMMON_MAGIC 0x0A450A45
85
86 /**
87 * Represents a generic ARM core, with standard application registers.
88 *
89 * There are sixteen application registers (including PC, SP, LR) and a PSR.
90 * Cortex-M series cores do not support as many core states or shadowed
91 * registers as traditional ARM cores, and only support Thumb2 instructions.
92 */
93 struct arm {
94 int common_magic;
95 struct reg_cache *core_cache;
96
97 /** Handle to the PC; valid in all core modes. */
98 struct reg *pc;
99
100 /** Handle to the CPSR; valid in all core modes. */
101 struct reg *cpsr;
102
103 /** Handle to the SPSR; valid only in core modes with an SPSR. */
104 struct reg *spsr;
105
106 /** Support for arm_reg_current() */
107 const int *map;
108
109 /**
110 * Indicates what registers are in the ARM state core register set.
111 * ARM_MODE_ANY indicates the standard set of 37 registers,
112 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
113 * more registers are shadowed, for "Secure Monitor" mode.
114 * ARM_MODE_THREAD indicates a microcontroller profile core,
115 * which only shadows SP.
116 */
117 enum arm_mode core_type;
118
119 /** Record the current core mode: SVC, USR, or some other mode. */
120 enum arm_mode core_mode;
121
122 /** Record the current core state: ARM, Thumb, or otherwise. */
123 enum arm_state core_state;
124
125 /** Flag reporting unavailability of the BKPT instruction. */
126 bool is_armv4;
127
128 /** Flag reporting armv6m based core. */
129 bool is_armv6m;
130
131 /** Flag reporting whether semihosting is active. */
132 bool is_semihosting;
133
134 /** Value to be returned by semihosting SYS_ERRNO request. */
135 int semihosting_errno;
136
137 int (*setup_semihosting)(struct target *target, int enable);
138
139 /** Backpointer to the target. */
140 struct target *target;
141
142 /** Handle for the debug module, if one is present. */
143 struct arm_dpm *dpm;
144
145 /** Handle for the Embedded Trace Module, if one is present. */
146 struct etm_context *etm;
147
148 /* FIXME all these methods should take "struct arm *" not target */
149
150 /** Retrieve all core registers, for display. */
151 int (*full_context)(struct target *target);
152
153 /** Retrieve a single core register. */
154 int (*read_core_reg)(struct target *target, struct reg *reg,
155 int num, enum arm_mode mode);
156 int (*write_core_reg)(struct target *target, struct reg *reg,
157 int num, enum arm_mode mode, uint32_t value);
158
159 /** Read coprocessor register. */
160 int (*mrc)(struct target *target, int cpnum,
161 uint32_t op1, uint32_t op2,
162 uint32_t CRn, uint32_t CRm,
163 uint32_t *value);
164
165 /** Write coprocessor register. */
166 int (*mcr)(struct target *target, int cpnum,
167 uint32_t op1, uint32_t op2,
168 uint32_t CRn, uint32_t CRm,
169 uint32_t value);
170
171 void *arch_info;
172
173 /** For targets conforming to ARM Debug Interface v5,
174 * this handle references the Debug Access Port (DAP)
175 * used to make requests to the target.
176 */
177 struct adiv5_dap *dap;
178 };
179
180 /** Convert target handle to generic ARM target state handle. */
181 static inline struct arm *target_to_arm(struct target *target)
182 {
183 assert(target != NULL);
184 return target->arch_info;
185 }
186
187 static inline bool is_arm(struct arm *arm)
188 {
189 assert(arm != NULL);
190 return arm->common_magic == ARM_COMMON_MAGIC;
191 }
192
193 struct arm_algorithm {
194 int common_magic;
195
196 enum arm_mode core_mode;
197 enum arm_state core_state;
198 };
199
200 struct arm_reg {
201 int num;
202 enum arm_mode mode;
203 struct target *target;
204 struct arm *arm;
205 uint32_t value;
206 };
207
208 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
209
210 extern const struct command_registration arm_command_handlers[];
211
212 int arm_arch_state(struct target *target);
213 int arm_get_gdb_reg_list(struct target *target,
214 struct reg **reg_list[], int *reg_list_size);
215
216 int arm_init_arch_info(struct target *target, struct arm *arm);
217
218 /* REVISIT rename this once it's usable by ARMv7-M */
219 int armv4_5_run_algorithm(struct target *target,
220 int num_mem_params, struct mem_param *mem_params,
221 int num_reg_params, struct reg_param *reg_params,
222 uint32_t entry_point, uint32_t exit_point,
223 int timeout_ms, void *arch_info);
224 int armv4_5_run_algorithm_inner(struct target *target,
225 int num_mem_params, struct mem_param *mem_params,
226 int num_reg_params, struct reg_param *reg_params,
227 uint32_t entry_point, uint32_t exit_point,
228 int timeout_ms, void *arch_info,
229 int (*run_it)(struct target *target, uint32_t exit_point,
230 int timeout_ms, void *arch_info));
231
232 int arm_checksum_memory(struct target *target,
233 uint32_t address, uint32_t count, uint32_t *checksum);
234 int arm_blank_check_memory(struct target *target,
235 uint32_t address, uint32_t count, uint32_t *blank);
236
237 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
238 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
239
240 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
241
242 extern struct reg arm_gdb_dummy_fp_reg;
243 extern struct reg arm_gdb_dummy_fps_reg;
244
245 #endif /* ARM_H */

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