src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #ifndef OPENOCD_TARGET_ARM_H
  26 #define OPENOCD_TARGET_ARM_H
  27
  28 #include <helper/command.h>
  29 #include "target.h"
  30
  31
  32 /**
  33  * @file
  34  * Holds the interface to ARM cores.
  35  *
  36  * At this writing, only "classic ARM" cores built on the ARMv4 register
  37  * and mode model are supported.  The Thumb2-only microcontroller profile
  38  * support has not yet been integrated, affecting Cortex-M parts.
  39  */
  40
  41 /**
  42  * Represent state of an ARM core.
  43  *
  44  * Most numbers match the five low bits of the *PSR registers on
  45  * "classic ARM" processors, which build on the ARMv4 processor
  46  * modes and register set.
  47  *
  48  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  49  *
  50  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  51  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  52  * they support.
  53  */
  54 enum arm_mode {
  55         ARM_MODE_USR = 16,
  56         ARM_MODE_FIQ = 17,
  57         ARM_MODE_IRQ = 18,
  58         ARM_MODE_SVC = 19,
  59         ARM_MODE_MON = 22,
  60         ARM_MODE_ABT = 23,
  61         ARM_MODE_UND = 27,
  62         ARM_MODE_1176_MON = 28,
  63         ARM_MODE_SYS = 31,
  64
  65         ARM_MODE_THREAD = 0,
  66         ARM_MODE_USER_THREAD = 1,
  67         ARM_MODE_HANDLER = 2,
  68
  69         /* shift left 4 bits for armv8 64 */
  70         ARMV8_64_EL0T = 0x0F,
  71         ARMV8_64_EL1T = 0x4F,
  72         ARMV8_64_EL1H = 0x5F,
  73         ARMV8_64_EL2T = 0x8F,
  74         ARMV8_64_EL2H = 0x9F,
  75         ARMV8_64_EL3T = 0xCF,
  76         ARMV8_64_EL3H = 0xDF,
  77
  78         ARM_MODE_ANY = -1
  79 };
  80
  81 const char *arm_mode_name(unsigned psr_mode);
  82 bool is_arm_mode(unsigned psr_mode);
  83
  84 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  85 enum arm_state {
  86         ARM_STATE_ARM,
  87         ARM_STATE_THUMB,
  88         ARM_STATE_JAZELLE,
  89         ARM_STATE_THUMB_EE,
  90         ARM_STATE_AARCH64,
  91 };
  92
  93 #define ARM_COMMON_MAGIC 0x0A450A45
  94
  95 /**
  96  * Represents a generic ARM core, with standard application registers.
  97  *
  98  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  99  * Cortex-M series cores do not support as many core states or shadowed
 100  * registers as traditional ARM cores, and only support Thumb2 instructions.
 101  */
 102 struct arm {
 103         int common_magic;
 104         struct reg_cache *core_cache;
 105
 106         /** Handle to the PC; valid in all core modes. */
 107         struct reg *pc;
 108
 109         /** Handle to the CPSR/xPSR; valid in all core modes. */
 110         struct reg *cpsr;
 111
 112         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 113         struct reg *spsr;
 114
 115         /** Support for arm_reg_current() */
 116         const int *map;
 117
 118         /**
 119          * Indicates what registers are in the ARM state core register set.
 120          * ARM_MODE_ANY indicates the standard set of 37 registers,
 121          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 122          * more registers are shadowed, for "Secure Monitor" mode.
 123          * ARM_MODE_THREAD indicates a microcontroller profile core,
 124          * which only shadows SP.
 125          */
 126         enum arm_mode core_type;
 127
 128         /** Record the current core mode: SVC, USR, or some other mode. */
 129         enum arm_mode core_mode;
 130
 131         /** Record the current core state: ARM, Thumb, or otherwise. */
 132         enum arm_state core_state;
 133
 134         /** Flag reporting unavailability of the BKPT instruction. */
 135         bool is_armv4;
 136
 137         /** Flag reporting armv6m based core. */
 138         bool is_armv6m;
 139
 140         /** Flag reporting whether semihosting is active. */
 141         bool is_semihosting;
 142
 143         /** Flag reporting whether semihosting fileio is active. */
 144         bool is_semihosting_fileio;
 145
 146         /** Flag reporting whether semihosting fileio operation is active. */
 147         bool semihosting_hit_fileio;
 148
 149         /** Current semihosting operation. */
 150         int semihosting_op;
 151
 152         /** Current semihosting result. */
 153         int semihosting_result;
 154
 155         /** Value to be returned by semihosting SYS_ERRNO request. */
 156         int semihosting_errno;
 157
 158         int (*setup_semihosting)(struct target *target, int enable);
 159
 160         /** Backpointer to the target. */
 161         struct target *target;
 162
 163         /** Handle for the debug module, if one is present. */
 164         struct arm_dpm *dpm;
 165
 166         /** Handle for the Embedded Trace Module, if one is present. */
 167         struct etm_context *etm;
 168
 169         /* FIXME all these methods should take "struct arm *" not target */
 170
 171         /** Retrieve all core registers, for display. */
 172         int (*full_context)(struct target *target);
 173
 174         /** Retrieve a single core register. */
 175         int (*read_core_reg)(struct target *target, struct reg *reg,
 176                         int num, enum arm_mode mode);
 177         int (*write_core_reg)(struct target *target, struct reg *reg,
 178                         int num, enum arm_mode mode, uint8_t *value);
 179
 180         /** Read coprocessor register.  */
 181         int (*mrc)(struct target *target, int cpnum,
 182                         uint32_t op1, uint32_t op2,
 183                         uint32_t CRn, uint32_t CRm,
 184                         uint32_t *value);
 185
 186         /** Write coprocessor register.  */
 187         int (*mcr)(struct target *target, int cpnum,
 188                         uint32_t op1, uint32_t op2,
 189                         uint32_t CRn, uint32_t CRm,
 190                         uint32_t value);
 191
 192         /** Read coprocessor register.  */
 193         int (*mrs)(struct target *target, uint32_t op0,
 194                         uint32_t op1, uint32_t op2,
 195                         uint32_t CRn, uint32_t CRm,
 196                         uint32_t *value);
 197
 198         /** Write coprocessor register.  */
 199         int (*msr)(struct target *target, uint32_t cpnum,
 200                         uint32_t op1, uint32_t op2,
 201                         uint32_t CRn, uint32_t CRm,
 202                         uint32_t value);
 203
 204         void *arch_info;
 205
 206         /** For targets conforming to ARM Debug Interface v5,
 207          * this handle references the Debug Access Port (DAP)
 208          * used to make requests to the target.
 209          */
 210         struct adiv5_dap *dap;
 211 };
 212
 213 /** Convert target handle to generic ARM target state handle. */
 214 static inline struct arm *target_to_arm(struct target *target)
 215 {
 216         assert(target != NULL);
 217         return target->arch_info;
 218 }
 219
 220 static inline bool is_arm(struct arm *arm)
 221 {
 222         assert(arm != NULL);
 223         return arm->common_magic == ARM_COMMON_MAGIC;
 224 }
 225
 226 struct arm_algorithm {
 227         int common_magic;
 228
 229         enum arm_mode core_mode;
 230         enum arm_state core_state;
 231 };
 232
 233 struct arm_reg {
 234         int num;
 235         enum arm_mode mode;
 236         struct target *target;
 237         struct arm *arm;
 238         uint8_t value[8];
 239 };
 240
 241 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 242 struct reg_cache *armv8_build_reg_cache(struct target *target);
 243
 244 extern const struct command_registration arm_command_handlers[];
 245
 246 int arm_arch_state(struct target *target);
 247 int arm_get_gdb_reg_list(struct target *target,
 248                 struct reg **reg_list[], int *reg_list_size,
 249                 enum target_register_class reg_class);
 250 int armv8_get_gdb_reg_list(struct target *target,
 251                 struct reg **reg_list[], int *reg_list_size,
 252                 enum target_register_class reg_class);
 253
 254 int arm_init_arch_info(struct target *target, struct arm *arm);
 255
 256 /* REVISIT rename this once it's usable by ARMv7-M */
 257 int armv4_5_run_algorithm(struct target *target,
 258                 int num_mem_params, struct mem_param *mem_params,
 259                 int num_reg_params, struct reg_param *reg_params,
 260                 target_addr_t entry_point, target_addr_t exit_point,
 261                 int timeout_ms, void *arch_info);
 262 int armv4_5_run_algorithm_inner(struct target *target,
 263                 int num_mem_params, struct mem_param *mem_params,
 264                 int num_reg_params, struct reg_param *reg_params,
 265                 uint32_t entry_point, uint32_t exit_point,
 266                 int timeout_ms, void *arch_info,
 267                 int (*run_it)(struct target *target, uint32_t exit_point,
 268                                 int timeout_ms, void *arch_info));
 269
 270 int arm_checksum_memory(struct target *target,
 271                 target_addr_t address, uint32_t count, uint32_t *checksum);
 272 int arm_blank_check_memory(struct target *target,
 273                 target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
 274
 275 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 276 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 277 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
 278
 279 extern struct reg arm_gdb_dummy_fp_reg;
 280 extern struct reg arm_gdb_dummy_fps_reg;
 281
 282 #endif /* OPENOCD_TARGET_ARM_H */