src/target/arm.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * Copyright (C) 2005 by Dominic Rath
   5  * Dominic.Rath@gmx.de
   6  *
   7  * Copyright (C) 2008 by Spencer Oliver
   8  * spen@spen-soft.co.uk
   9  *
  10  * Copyright (C) 2009 by Øyvind Harboe
  11  * oyvind.harboe@zylin.com
  12  *
  13  * Copyright (C) 2018 by Liviu Ionescu
  14  *   <ilg@livius.net>
  15  */
  16
  17 #ifndef OPENOCD_TARGET_ARM_H
  18 #define OPENOCD_TARGET_ARM_H
  19
  20 #include <helper/command.h>
  21 #include "target.h"
  22
  23 /**
  24  * @file
  25  * Holds the interface to ARM cores.
  26  *
  27  * At this writing, only "classic ARM" cores built on the ARMv4 register
  28  * and mode model are supported.  The Thumb2-only microcontroller profile
  29  * support has not yet been integrated, affecting Cortex-M parts.
  30  */
  31
  32 /**
  33  * Indicates what registers are in the ARM state core register set.
  34  *
  35  * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
  36  *   on for example ARM7TDMI cores.
  37  * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
  38  *   three more registers are shadowed for "Secure Monitor" mode.
  39  * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
  40  *   and also security extensions. Additional shadowed registers for
  41  *   "Secure Monitor" and "Hypervisor" modes.
  42  * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
  43  *   which only shadows SP.
  44  */
  45 enum arm_core_type {
  46         ARM_CORE_TYPE_STD = -1,
  47         ARM_CORE_TYPE_SEC_EXT = 1,
  48         ARM_CORE_TYPE_VIRT_EXT,
  49         ARM_CORE_TYPE_M_PROFILE,
  50 };
  51
  52 /** ARM Architecture specifying the version and the profile */
  53 enum arm_arch {
  54         ARM_ARCH_UNKNOWN,
  55         ARM_ARCH_V4,
  56         ARM_ARCH_V6M,
  57         ARM_ARCH_V7M,
  58         ARM_ARCH_V8M,
  59 };
  60
  61 /** Known ARM implementor IDs */
  62 enum arm_implementor {
  63         ARM_IMPLEMENTOR_ARM = 0x41,
  64         ARM_IMPLEMENTOR_INFINEON = 0x49,
  65         ARM_IMPLEMENTOR_REALTEK = 0x72,
  66 };
  67
  68 /**
  69  * Represent state of an ARM core.
  70  *
  71  * Most numbers match the five low bits of the *PSR registers on
  72  * "classic ARM" processors, which build on the ARMv4 processor
  73  * modes and register set.
  74  *
  75  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  76  *
  77  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  78  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  79  * they support.
  80  */
  81 enum arm_mode {
  82         ARM_MODE_USR = 16,
  83         ARM_MODE_FIQ = 17,
  84         ARM_MODE_IRQ = 18,
  85         ARM_MODE_SVC = 19,
  86         ARM_MODE_MON = 22,
  87         ARM_MODE_ABT = 23,
  88         ARM_MODE_HYP = 26,
  89         ARM_MODE_UND = 27,
  90         ARM_MODE_1176_MON = 28,
  91         ARM_MODE_SYS = 31,
  92
  93         ARM_MODE_THREAD = 0,
  94         ARM_MODE_USER_THREAD = 1,
  95         ARM_MODE_HANDLER = 2,
  96
  97         ARMV8_64_EL0T = 0x0,
  98         ARMV8_64_EL1T = 0x4,
  99         ARMV8_64_EL1H = 0x5,
 100         ARMV8_64_EL2T = 0x8,
 101         ARMV8_64_EL2H = 0x9,
 102         ARMV8_64_EL3T = 0xC,
 103         ARMV8_64_EL3H = 0xD,
 104
 105         ARM_MODE_ANY = -1
 106 };
 107
 108 /* VFPv3 internal register numbers mapping to d0:31 */
 109 enum {
 110         ARM_VFP_V3_D0 = 51,
 111         ARM_VFP_V3_D1,
 112         ARM_VFP_V3_D2,
 113         ARM_VFP_V3_D3,
 114         ARM_VFP_V3_D4,
 115         ARM_VFP_V3_D5,
 116         ARM_VFP_V3_D6,
 117         ARM_VFP_V3_D7,
 118         ARM_VFP_V3_D8,
 119         ARM_VFP_V3_D9,
 120         ARM_VFP_V3_D10,
 121         ARM_VFP_V3_D11,
 122         ARM_VFP_V3_D12,
 123         ARM_VFP_V3_D13,
 124         ARM_VFP_V3_D14,
 125         ARM_VFP_V3_D15,
 126         ARM_VFP_V3_D16,
 127         ARM_VFP_V3_D17,
 128         ARM_VFP_V3_D18,
 129         ARM_VFP_V3_D19,
 130         ARM_VFP_V3_D20,
 131         ARM_VFP_V3_D21,
 132         ARM_VFP_V3_D22,
 133         ARM_VFP_V3_D23,
 134         ARM_VFP_V3_D24,
 135         ARM_VFP_V3_D25,
 136         ARM_VFP_V3_D26,
 137         ARM_VFP_V3_D27,
 138         ARM_VFP_V3_D28,
 139         ARM_VFP_V3_D29,
 140         ARM_VFP_V3_D30,
 141         ARM_VFP_V3_D31,
 142         ARM_VFP_V3_FPSCR,
 143 };
 144
 145 const char *arm_mode_name(unsigned psr_mode);
 146 bool is_arm_mode(unsigned psr_mode);
 147
 148 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
 149 enum arm_state {
 150         ARM_STATE_ARM,
 151         ARM_STATE_THUMB,
 152         ARM_STATE_JAZELLE,
 153         ARM_STATE_THUMB_EE,
 154         ARM_STATE_AARCH64,
 155 };
 156
 157 /** ARM vector floating point enabled, if yes which version. */
 158 enum arm_vfp_version {
 159         ARM_VFP_DISABLED,
 160         ARM_VFP_V1,
 161         ARM_VFP_V2,
 162         ARM_VFP_V3,
 163 };
 164
 165 #define ARM_COMMON_MAGIC 0x0A450A45U
 166
 167 /**
 168  * Represents a generic ARM core, with standard application registers.
 169  *
 170  * There are sixteen application registers (including PC, SP, LR) and a PSR.
 171  * Cortex-M series cores do not support as many core states or shadowed
 172  * registers as traditional ARM cores, and only support Thumb2 instructions.
 173  */
 174 struct arm {
 175         unsigned int common_magic;
 176
 177         struct reg_cache *core_cache;
 178
 179         /** Handle to the PC; valid in all core modes. */
 180         struct reg *pc;
 181
 182         /** Handle to the CPSR/xPSR; valid in all core modes. */
 183         struct reg *cpsr;
 184
 185         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 186         struct reg *spsr;
 187
 188         /** Support for arm_reg_current() */
 189         const int *map;
 190
 191         /** Indicates what registers are in the ARM state core register set. */
 192         enum arm_core_type core_type;
 193
 194         /** Record the current core mode: SVC, USR, or some other mode. */
 195         enum arm_mode core_mode;
 196
 197         /** Record the current core state: ARM, Thumb, or otherwise. */
 198         enum arm_state core_state;
 199
 200         /** ARM architecture version */
 201         enum arm_arch arch;
 202
 203         /** Floating point or VFP version, 0 if disabled. */
 204         int arm_vfp_version;
 205
 206         int (*setup_semihosting)(struct target *target, int enable);
 207
 208         /** Backpointer to the target. */
 209         struct target *target;
 210
 211         /** Handle for the debug module, if one is present. */
 212         struct arm_dpm *dpm;
 213
 214         /** Handle for the Embedded Trace Module, if one is present. */
 215         struct etm_context *etm;
 216
 217         /* FIXME all these methods should take "struct arm *" not target */
 218
 219         /** Retrieve all core registers, for display. */
 220         int (*full_context)(struct target *target);
 221
 222         /** Retrieve a single core register. */
 223         int (*read_core_reg)(struct target *target, struct reg *reg,
 224                         int num, enum arm_mode mode);
 225         int (*write_core_reg)(struct target *target, struct reg *reg,
 226                         int num, enum arm_mode mode, uint8_t *value);
 227
 228         /** Read coprocessor register.  */
 229         int (*mrc)(struct target *target, int cpnum,
 230                         uint32_t op1, uint32_t op2,
 231                         uint32_t crn, uint32_t crm,
 232                         uint32_t *value);
 233
 234         /** Read coprocessor to two registers. */
 235         int (*mrrc)(struct target *target, int cpnum,
 236                         uint32_t op, uint32_t crm,
 237                         uint64_t *value);
 238
 239         /** Write coprocessor register.  */
 240         int (*mcr)(struct target *target, int cpnum,
 241                         uint32_t op1, uint32_t op2,
 242                         uint32_t crn, uint32_t crm,
 243                         uint32_t value);
 244
 245         /** Write coprocessor from two registers. */
 246         int (*mcrr)(struct target *target, int cpnum,
 247                         uint32_t op, uint32_t crm,
 248                         uint64_t value);
 249
 250         void *arch_info;
 251
 252         /** For targets conforming to ARM Debug Interface v5,
 253          * this handle references the Debug Access Port (DAP)
 254          * used to make requests to the target.
 255          */
 256         struct adiv5_dap *dap;
 257 };
 258
 259 /** Convert target handle to generic ARM target state handle. */
 260 static inline struct arm *target_to_arm(const struct target *target)
 261 {
 262         assert(target);
 263         return target->arch_info;
 264 }
 265
 266 static inline bool is_arm(struct arm *arm)
 267 {
 268         assert(arm);
 269         return arm->common_magic == ARM_COMMON_MAGIC;
 270 }
 271
 272 struct arm_algorithm {
 273         unsigned int common_magic;
 274
 275         enum arm_mode core_mode;
 276         enum arm_state core_state;
 277 };
 278
 279 struct arm_reg {
 280         int num;
 281         enum arm_mode mode;
 282         struct target *target;
 283         struct arm *arm;
 284         uint8_t value[16];
 285 };
 286
 287 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 288 void arm_free_reg_cache(struct arm *arm);
 289
 290 struct reg_cache *armv8_build_reg_cache(struct target *target);
 291
 292 extern const struct command_registration arm_command_handlers[];
 293 extern const struct command_registration arm_all_profiles_command_handlers[];
 294
 295 int arm_arch_state(struct target *target);
 296 const char *arm_get_gdb_arch(const struct target *target);
 297 int arm_get_gdb_reg_list(struct target *target,
 298                 struct reg **reg_list[], int *reg_list_size,
 299                 enum target_register_class reg_class);
 300 const char *armv8_get_gdb_arch(const struct target *target);
 301 int armv8_get_gdb_reg_list(struct target *target,
 302                 struct reg **reg_list[], int *reg_list_size,
 303                 enum target_register_class reg_class);
 304
 305 int arm_init_arch_info(struct target *target, struct arm *arm);
 306
 307 /* REVISIT rename this once it's usable by ARMv7-M */
 308 int armv4_5_run_algorithm(struct target *target,
 309                 int num_mem_params, struct mem_param *mem_params,
 310                 int num_reg_params, struct reg_param *reg_params,
 311                 target_addr_t entry_point, target_addr_t exit_point,
 312                 unsigned int timeout_ms, void *arch_info);
 313 int armv4_5_run_algorithm_inner(struct target *target,
 314                 int num_mem_params, struct mem_param *mem_params,
 315                 int num_reg_params, struct reg_param *reg_params,
 316                 uint32_t entry_point, uint32_t exit_point,
 317                 unsigned int timeout_ms, void *arch_info,
 318                 int (*run_it)(struct target *target, uint32_t exit_point,
 319                                 unsigned int timeout_ms, void *arch_info));
 320
 321 int arm_checksum_memory(struct target *target,
 322                 target_addr_t address, uint32_t count, uint32_t *checksum);
 323 int arm_blank_check_memory(struct target *target,
 324                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 325
 326 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 327 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 328 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
 329
 330 #endif /* OPENOCD_TARGET_ARM_H */