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[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "arm11.h"
27 #include "jtag.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32
33 #if 0
34 #define _DEBUG_INSTRUCTION_EXECUTION_
35 #endif
36
37
38 #if 0
39 #define FNC_INFO LOG_DEBUG("-")
40 #else
41 #define FNC_INFO
42 #endif
43
44 #if 1
45 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
46 #else
47 #define FNC_INFO_NOTIMPLEMENTED
48 #endif
49
50 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
51
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 u32 arm11_vcr = 0;
56
57
58 #define ARM11_HANDLER(x) \
59 .x = arm11_##x
60
61 target_type_t arm11_target =
62 {
63 .name = "arm11",
64
65 ARM11_HANDLER(poll),
66 ARM11_HANDLER(arch_state),
67
68 ARM11_HANDLER(target_request_data),
69
70 ARM11_HANDLER(halt),
71 ARM11_HANDLER(resume),
72 ARM11_HANDLER(step),
73
74 ARM11_HANDLER(assert_reset),
75 ARM11_HANDLER(deassert_reset),
76 ARM11_HANDLER(soft_reset_halt),
77
78 ARM11_HANDLER(get_gdb_reg_list),
79
80 ARM11_HANDLER(read_memory),
81 ARM11_HANDLER(write_memory),
82
83 ARM11_HANDLER(bulk_write_memory),
84
85 ARM11_HANDLER(checksum_memory),
86
87 ARM11_HANDLER(add_breakpoint),
88 ARM11_HANDLER(remove_breakpoint),
89 ARM11_HANDLER(add_watchpoint),
90 ARM11_HANDLER(remove_watchpoint),
91
92 ARM11_HANDLER(run_algorithm),
93
94 ARM11_HANDLER(register_commands),
95 ARM11_HANDLER(target_command),
96 ARM11_HANDLER(init_target),
97 ARM11_HANDLER(examine),
98 ARM11_HANDLER(quit),
99 };
100
101 int arm11_regs_arch_type = -1;
102
103
104 enum arm11_regtype
105 {
106 ARM11_REGISTER_CORE,
107 ARM11_REGISTER_CPSR,
108
109 ARM11_REGISTER_FX,
110 ARM11_REGISTER_FPS,
111
112 ARM11_REGISTER_FIQ,
113 ARM11_REGISTER_SVC,
114 ARM11_REGISTER_ABT,
115 ARM11_REGISTER_IRQ,
116 ARM11_REGISTER_UND,
117 ARM11_REGISTER_MON,
118
119 ARM11_REGISTER_SPSR_FIQ,
120 ARM11_REGISTER_SPSR_SVC,
121 ARM11_REGISTER_SPSR_ABT,
122 ARM11_REGISTER_SPSR_IRQ,
123 ARM11_REGISTER_SPSR_UND,
124 ARM11_REGISTER_SPSR_MON,
125
126 /* debug regs */
127 ARM11_REGISTER_DSCR,
128 ARM11_REGISTER_WDTR,
129 ARM11_REGISTER_RDTR,
130 };
131
132
133 typedef struct arm11_reg_defs_s
134 {
135 char * name;
136 u32 num;
137 int gdb_num;
138 enum arm11_regtype type;
139 } arm11_reg_defs_t;
140
141 /* update arm11_regcache_ids when changing this */
142 static const arm11_reg_defs_t arm11_reg_defs[] =
143 {
144 {"r0", 0, 0, ARM11_REGISTER_CORE},
145 {"r1", 1, 1, ARM11_REGISTER_CORE},
146 {"r2", 2, 2, ARM11_REGISTER_CORE},
147 {"r3", 3, 3, ARM11_REGISTER_CORE},
148 {"r4", 4, 4, ARM11_REGISTER_CORE},
149 {"r5", 5, 5, ARM11_REGISTER_CORE},
150 {"r6", 6, 6, ARM11_REGISTER_CORE},
151 {"r7", 7, 7, ARM11_REGISTER_CORE},
152 {"r8", 8, 8, ARM11_REGISTER_CORE},
153 {"r9", 9, 9, ARM11_REGISTER_CORE},
154 {"r10", 10, 10, ARM11_REGISTER_CORE},
155 {"r11", 11, 11, ARM11_REGISTER_CORE},
156 {"r12", 12, 12, ARM11_REGISTER_CORE},
157 {"sp", 13, 13, ARM11_REGISTER_CORE},
158 {"lr", 14, 14, ARM11_REGISTER_CORE},
159 {"pc", 15, 15, ARM11_REGISTER_CORE},
160
161 #if ARM11_REGCACHE_FREGS
162 {"f0", 0, 16, ARM11_REGISTER_FX},
163 {"f1", 1, 17, ARM11_REGISTER_FX},
164 {"f2", 2, 18, ARM11_REGISTER_FX},
165 {"f3", 3, 19, ARM11_REGISTER_FX},
166 {"f4", 4, 20, ARM11_REGISTER_FX},
167 {"f5", 5, 21, ARM11_REGISTER_FX},
168 {"f6", 6, 22, ARM11_REGISTER_FX},
169 {"f7", 7, 23, ARM11_REGISTER_FX},
170 {"fps", 0, 24, ARM11_REGISTER_FPS},
171 #endif
172
173 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
174
175 #if ARM11_REGCACHE_MODEREGS
176 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
177 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
178 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
179 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
180 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
181 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
182 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
183 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
184
185 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
186 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
187 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
188
189 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
190 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
191 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
192
193 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
194 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
195 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
196
197 {"r13_und", 13, -1, ARM11_REGISTER_UND},
198 {"r14_und", 14, -1, ARM11_REGISTER_UND},
199 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
200
201 /* ARM1176 only */
202 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
203 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
204 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
205 #endif
206
207 /* Debug Registers */
208 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
209 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
210 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
211 };
212
213 enum arm11_regcache_ids
214 {
215 ARM11_RC_R0,
216 ARM11_RC_RX = ARM11_RC_R0,
217
218 ARM11_RC_R1,
219 ARM11_RC_R2,
220 ARM11_RC_R3,
221 ARM11_RC_R4,
222 ARM11_RC_R5,
223 ARM11_RC_R6,
224 ARM11_RC_R7,
225 ARM11_RC_R8,
226 ARM11_RC_R9,
227 ARM11_RC_R10,
228 ARM11_RC_R11,
229 ARM11_RC_R12,
230 ARM11_RC_R13,
231 ARM11_RC_SP = ARM11_RC_R13,
232 ARM11_RC_R14,
233 ARM11_RC_LR = ARM11_RC_R14,
234 ARM11_RC_R15,
235 ARM11_RC_PC = ARM11_RC_R15,
236
237 #if ARM11_REGCACHE_FREGS
238 ARM11_RC_F0,
239 ARM11_RC_FX = ARM11_RC_F0,
240 ARM11_RC_F1,
241 ARM11_RC_F2,
242 ARM11_RC_F3,
243 ARM11_RC_F4,
244 ARM11_RC_F5,
245 ARM11_RC_F6,
246 ARM11_RC_F7,
247 ARM11_RC_FPS,
248 #endif
249
250 ARM11_RC_CPSR,
251
252 #if ARM11_REGCACHE_MODEREGS
253 ARM11_RC_R8_FIQ,
254 ARM11_RC_R9_FIQ,
255 ARM11_RC_R10_FIQ,
256 ARM11_RC_R11_FIQ,
257 ARM11_RC_R12_FIQ,
258 ARM11_RC_R13_FIQ,
259 ARM11_RC_R14_FIQ,
260 ARM11_RC_SPSR_FIQ,
261
262 ARM11_RC_R13_SVC,
263 ARM11_RC_R14_SVC,
264 ARM11_RC_SPSR_SVC,
265
266 ARM11_RC_R13_ABT,
267 ARM11_RC_R14_ABT,
268 ARM11_RC_SPSR_ABT,
269
270 ARM11_RC_R13_IRQ,
271 ARM11_RC_R14_IRQ,
272 ARM11_RC_SPSR_IRQ,
273
274 ARM11_RC_R13_UND,
275 ARM11_RC_R14_UND,
276 ARM11_RC_SPSR_UND,
277
278 ARM11_RC_R13_MON,
279 ARM11_RC_R14_MON,
280 ARM11_RC_SPSR_MON,
281 #endif
282
283 ARM11_RC_DSCR,
284 ARM11_RC_WDTR,
285 ARM11_RC_RDTR,
286
287 ARM11_RC_MAX,
288 };
289
290 #define ARM11_GDB_REGISTER_COUNT 26
291
292 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
293
294 reg_t arm11_gdb_dummy_fp_reg =
295 {
296 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
297 };
298
299 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
300
301 reg_t arm11_gdb_dummy_fps_reg =
302 {
303 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
304 };
305
306
307
308 /** Check and if necessary take control of the system
309 *
310 * \param arm11 Target state variable.
311 * \param dscr If the current DSCR content is
312 * available a pointer to a word holding the
313 * DSCR can be passed. Otherwise use NULL.
314 */
315 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
316 {
317 FNC_INFO;
318
319 u32 dscr_local_tmp_copy;
320
321 if (!dscr)
322 {
323 dscr = &dscr_local_tmp_copy;
324 *dscr = arm11_read_DSCR(arm11);
325 }
326
327 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
328 {
329 LOG_DEBUG("Bringing target into debug mode");
330
331 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
332 arm11_write_DSCR(arm11, *dscr);
333
334 /* add further reset initialization here */
335
336 arm11->simulate_reset_on_next_halt = true;
337
338 if (*dscr & ARM11_DSCR_CORE_HALTED)
339 {
340 /** \todo TODO: this needs further scrutiny because
341 * arm11_on_enter_debug_state() never gets properly called
342 */
343
344 arm11->target->state = TARGET_HALTED;
345 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
346 }
347 else
348 {
349 arm11->target->state = TARGET_RUNNING;
350 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
351 }
352
353 arm11_sc7_clear_vbw(arm11);
354 }
355 }
356
357
358
359 #define R(x) \
360 (arm11->reg_values[ARM11_RC_##x])
361
362 /** Save processor state.
363 *
364 * This is called when the HALT instruction has succeeded
365 * or on other occasions that stop the processor.
366 *
367 */
368 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
369 {
370 FNC_INFO;
371
372 {size_t i;
373 for(i = 0; i < asizeof(arm11->reg_values); i++)
374 {
375 arm11->reg_list[i].valid = 1;
376 arm11->reg_list[i].dirty = 0;
377 }}
378
379 /* Save DSCR */
380
381 R(DSCR) = arm11_read_DSCR(arm11);
382
383 /* Save wDTR */
384
385 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
386 {
387 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
388
389 arm11_add_IR(arm11, ARM11_INTEST, -1);
390
391 scan_field_t chain5_fields[3];
392
393 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
394 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
395 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
396
397 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
398 }
399 else
400 {
401 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
402 }
403
404
405 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
406 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
407 ARM1136 seems to require this to issue ITR's as well */
408
409 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
410
411 /* this executes JTAG queue: */
412
413 arm11_write_DSCR(arm11, new_dscr);
414
415
416 /* From the spec:
417 Before executing any instruction in debug state you have to drain the write buffer.
418 This ensures that no imprecise Data Aborts can return at a later point:*/
419
420 /** \todo TODO: Test drain write buffer. */
421
422 #if 0
423 while (1)
424 {
425 /* MRC p14,0,R0,c5,c10,0 */
426 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
427
428 /* mcr 15, 0, r0, cr7, cr10, {4} */
429 arm11_run_instr_no_data1(arm11, 0xee070f9a);
430
431 u32 dscr = arm11_read_DSCR(arm11);
432
433 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
434
435 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
436 {
437 arm11_run_instr_no_data1(arm11, 0xe320f000);
438
439 dscr = arm11_read_DSCR(arm11);
440
441 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
442
443 break;
444 }
445 }
446 #endif
447
448
449 arm11_run_instr_data_prepare(arm11);
450
451 /* save r0 - r14 */
452
453
454 /** \todo TODO: handle other mode registers */
455
456 {size_t i;
457 for (i = 0; i < 15; i++)
458 {
459 /* MCR p14,0,R?,c0,c5,0 */
460 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
461 }}
462
463
464 /* save rDTR */
465
466 /* check rDTRfull in DSCR */
467
468 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
469 {
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
472 }
473 else
474 {
475 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
476 }
477
478 /* save CPSR */
479
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
482
483 /* save PC */
484
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
487
488 /* adjust PC depending on ARM state */
489
490 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
491 {
492 arm11->reg_values[ARM11_RC_PC] -= 0;
493 }
494 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
495 {
496 arm11->reg_values[ARM11_RC_PC] -= 4;
497 }
498 else /* ARM state */
499 {
500 arm11->reg_values[ARM11_RC_PC] -= 8;
501 }
502
503 if (arm11->simulate_reset_on_next_halt)
504 {
505 arm11->simulate_reset_on_next_halt = false;
506
507 LOG_DEBUG("Reset c1 Control Register");
508
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
510
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
513
514 }
515
516 arm11_run_instr_data_finish(arm11);
517
518 arm11_dump_reg_changes(arm11);
519 }
520
521 void arm11_dump_reg_changes(arm11_common_t * arm11)
522 {
523 {size_t i;
524 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
525 {
526 if (!arm11->reg_list[i].valid)
527 {
528 if (arm11->reg_history[i].valid)
529 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
530 }
531 else
532 {
533 if (arm11->reg_history[i].valid)
534 {
535 if (arm11->reg_history[i].value != arm11->reg_values[i])
536 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
537 }
538 else
539 {
540 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
541 }
542 }
543 }}
544 }
545
546
547 /** Restore processor state
548 *
549 * This is called in preparation for the RESTART function.
550 *
551 */
552 void arm11_leave_debug_state(arm11_common_t * arm11)
553 {
554 FNC_INFO;
555
556 arm11_run_instr_data_prepare(arm11);
557
558 /** \todo TODO: handle other mode registers */
559
560 /* restore R1 - R14 */
561 {size_t i;
562 for (i = 1; i < 15; i++)
563 {
564 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
565 continue;
566
567 /* MRC p14,0,r?,c0,c5,0 */
568 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
569
570 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
571 }}
572
573 arm11_run_instr_data_finish(arm11);
574
575
576 /* spec says clear wDTR and rDTR; we assume they are clear as
577 otherwise our programming would be sloppy */
578
579 {
580 u32 DSCR = arm11_read_DSCR(arm11);
581
582 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
583 {
584 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
585 }
586 }
587
588 arm11_run_instr_data_prepare(arm11);
589
590 /* restore original wDTR */
591
592 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
593 {
594 /* MCR p14,0,R0,c0,c5,0 */
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
596 }
597
598 /* restore CPSR */
599
600 /* MSR CPSR,R0*/
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
602
603
604 /* restore PC */
605
606 /* MOV PC,R0 */
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
608
609
610 /* restore R0 */
611
612 /* MRC p14,0,r0,c0,c5,0 */
613 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
614
615 arm11_run_instr_data_finish(arm11);
616
617
618 /* restore DSCR */
619
620 arm11_write_DSCR(arm11, R(DSCR));
621
622
623 /* restore rDTR */
624
625 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
626 {
627 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
628
629 arm11_add_IR(arm11, ARM11_EXTEST, -1);
630
631 scan_field_t chain5_fields[3];
632
633 u8 Ready = 0; /* ignored */
634 u8 Valid = 0; /* ignored */
635
636 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
637 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
638 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
639
640 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
641 }
642
643 arm11_record_register_history(arm11);
644 }
645
646 void arm11_record_register_history(arm11_common_t * arm11)
647 {
648 {size_t i;
649 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
650 {
651 arm11->reg_history[i].value = arm11->reg_values[i];
652 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
653
654 arm11->reg_list[i].valid = 0;
655 arm11->reg_list[i].dirty = 0;
656 }}
657 }
658
659
660 /* poll current target status */
661 int arm11_poll(struct target_s *target)
662 {
663 FNC_INFO;
664
665 arm11_common_t * arm11 = target->arch_info;
666
667 if (arm11->trst_active)
668 return ERROR_OK;
669
670 u32 dscr = arm11_read_DSCR(arm11);
671
672 LOG_DEBUG("DSCR %08x", dscr);
673
674 arm11_check_init(arm11, &dscr);
675
676 if (dscr & ARM11_DSCR_CORE_HALTED)
677 {
678 if (target->state != TARGET_HALTED)
679 {
680 enum target_state old_state = target->state;
681
682 LOG_DEBUG("enter TARGET_HALTED");
683 target->state = TARGET_HALTED;
684 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
685 arm11_on_enter_debug_state(arm11);
686
687 target_call_event_callbacks(target,
688 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
689 }
690 }
691 else
692 {
693 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
694 {
695 LOG_DEBUG("enter TARGET_RUNNING");
696 target->state = TARGET_RUNNING;
697 target->debug_reason = DBG_REASON_NOTHALTED;
698 }
699 }
700
701 return ERROR_OK;
702 }
703 /* architecture specific status reply */
704 int arm11_arch_state(struct target_s *target)
705 {
706 FNC_INFO_NOTIMPLEMENTED;
707
708 return ERROR_OK;
709 }
710
711
712 /* target request support */
713 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
714 {
715 FNC_INFO_NOTIMPLEMENTED;
716
717 return ERROR_OK;
718 }
719
720
721
722 /* target execution control */
723 int arm11_halt(struct target_s *target)
724 {
725 FNC_INFO;
726
727 arm11_common_t * arm11 = target->arch_info;
728
729 LOG_DEBUG("target->state: %s",
730 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
731
732 if (target->state == TARGET_UNKNOWN)
733 {
734 arm11->simulate_reset_on_next_halt = true;
735 }
736
737 if (target->state == TARGET_HALTED)
738 {
739 LOG_DEBUG("target was already halted");
740 return ERROR_OK;
741 }
742
743 if (arm11->trst_active)
744 {
745 arm11->halt_requested = true;
746 return ERROR_OK;
747 }
748
749 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
750
751 jtag_execute_queue();
752
753 u32 dscr;
754
755 while (1)
756 {
757 dscr = arm11_read_DSCR(arm11);
758
759 if (dscr & ARM11_DSCR_CORE_HALTED)
760 break;
761 }
762
763 arm11_on_enter_debug_state(arm11);
764
765 enum target_state old_state = target->state;
766
767 target->state = TARGET_HALTED;
768 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
769
770 target_call_event_callbacks(target,
771 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
772
773 return ERROR_OK;
774 }
775
776
777 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
778 {
779 FNC_INFO;
780
781 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
782 // current, address, handle_breakpoints, debug_execution);
783
784 arm11_common_t * arm11 = target->arch_info;
785
786 LOG_DEBUG("target->state: %s",
787 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
788
789
790 if (target->state != TARGET_HALTED)
791 {
792 LOG_ERROR("Target not halted");
793 return ERROR_TARGET_NOT_HALTED;
794 }
795
796 if (!current)
797 R(PC) = address;
798
799 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
800
801 /* clear breakpoints/watchpoints and VCR*/
802 arm11_sc7_clear_vbw(arm11);
803
804 /* Set up breakpoints */
805 if (!debug_execution)
806 {
807 /* check if one matches PC and step over it if necessary */
808
809 breakpoint_t * bp;
810
811 for (bp = target->breakpoints; bp; bp = bp->next)
812 {
813 if (bp->address == R(PC))
814 {
815 LOG_DEBUG("must step over %08x", bp->address);
816 arm11_step(target, 1, 0, 0);
817 break;
818 }
819 }
820
821 /* set all breakpoints */
822
823 size_t brp_num = 0;
824
825 for (bp = target->breakpoints; bp; bp = bp->next)
826 {
827 arm11_sc7_action_t brp[2];
828
829 brp[0].write = 1;
830 brp[0].address = ARM11_SC7_BVR0 + brp_num;
831 brp[0].value = bp->address;
832 brp[1].write = 1;
833 brp[1].address = ARM11_SC7_BCR0 + brp_num;
834 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
835
836 arm11_sc7_run(arm11, brp, asizeof(brp));
837
838 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
839
840 brp_num++;
841 }
842
843 arm11_sc7_set_vcr(arm11, arm11_vcr);
844 }
845
846
847 arm11_leave_debug_state(arm11);
848
849 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
850
851 jtag_execute_queue();
852
853 while (1)
854 {
855 u32 dscr = arm11_read_DSCR(arm11);
856
857 LOG_DEBUG("DSCR %08x", dscr);
858
859 if (dscr & ARM11_DSCR_CORE_RESTARTED)
860 break;
861 }
862
863 if (!debug_execution)
864 {
865 target->state = TARGET_RUNNING;
866 target->debug_reason = DBG_REASON_NOTHALTED;
867 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
868 }
869 else
870 {
871 target->state = TARGET_DEBUG_RUNNING;
872 target->debug_reason = DBG_REASON_NOTHALTED;
873 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
874 }
875
876 return ERROR_OK;
877 }
878
879 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
880 {
881 FNC_INFO;
882
883 LOG_DEBUG("target->state: %s",
884 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
885
886 if (target->state != TARGET_HALTED)
887 {
888 LOG_WARNING("target was not halted");
889 return ERROR_TARGET_NOT_HALTED;
890 }
891
892 arm11_common_t * arm11 = target->arch_info;
893
894 if (!current)
895 R(PC) = address;
896
897 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
898
899 /** \todo TODO: Thumb not supported here */
900
901 u32 next_instruction;
902
903 arm11_read_memory_word(arm11, R(PC), &next_instruction);
904
905 /* skip over BKPT */
906 if ((next_instruction & 0xFFF00070) == 0xe1200070)
907 {
908 R(PC) += 4;
909 arm11->reg_list[ARM11_RC_PC].valid = 1;
910 arm11->reg_list[ARM11_RC_PC].dirty = 0;
911 LOG_INFO("Skipping BKPT");
912 }
913 /* skip over Wait for interrupt / Standby */
914 /* mcr 15, 0, r?, cr7, cr0, {4} */
915 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
916 {
917 R(PC) += 4;
918 arm11->reg_list[ARM11_RC_PC].valid = 1;
919 arm11->reg_list[ARM11_RC_PC].dirty = 0;
920 LOG_INFO("Skipping WFI");
921 }
922 /* ignore B to self */
923 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
924 {
925 LOG_INFO("Not stepping jump to self");
926 }
927 else
928 {
929 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
930 * with this. */
931
932 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
933 * the VCR might be something worth looking into. */
934
935
936 /* Set up breakpoint for stepping */
937
938 arm11_sc7_action_t brp[2];
939
940 brp[0].write = 1;
941 brp[0].address = ARM11_SC7_BVR0;
942 brp[0].value = R(PC);
943 brp[1].write = 1;
944 brp[1].address = ARM11_SC7_BCR0;
945 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
946
947 arm11_sc7_run(arm11, brp, asizeof(brp));
948
949 /* resume */
950
951 arm11_leave_debug_state(arm11);
952
953 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
954
955 jtag_execute_queue();
956
957 /** \todo TODO: add a timeout */
958
959 /* wait for halt */
960
961 while (1)
962 {
963 u32 dscr = arm11_read_DSCR(arm11);
964
965 LOG_DEBUG("DSCR %08x", dscr);
966
967 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
968 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
969 break;
970 }
971
972 /* clear breakpoint */
973 arm11_sc7_clear_vbw(arm11);
974
975 /* save state */
976 arm11_on_enter_debug_state(arm11);
977 }
978
979 // target->state = TARGET_HALTED;
980 target->debug_reason = DBG_REASON_SINGLESTEP;
981
982 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
983
984 return ERROR_OK;
985 }
986
987
988 /* target reset control */
989 int arm11_assert_reset(struct target_s *target)
990 {
991 FNC_INFO;
992
993 #if 0
994 /* assert reset lines */
995 /* resets only the DBGTAP, not the ARM */
996
997 jtag_add_reset(1, 0);
998 jtag_add_sleep(5000);
999
1000 arm11_common_t * arm11 = target->arch_info;
1001 arm11->trst_active = true;
1002 #endif
1003
1004 if (target->reset_halt)
1005 {
1006 int retval;
1007 if ((retval = target_halt(target))!=ERROR_OK)
1008 return retval;
1009 }
1010
1011 return ERROR_OK;
1012 }
1013
1014 int arm11_deassert_reset(struct target_s *target)
1015 {
1016 FNC_INFO;
1017
1018 #if 0
1019 LOG_DEBUG("target->state: %s",
1020 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1021
1022
1023 /* deassert reset lines */
1024 jtag_add_reset(0, 0);
1025
1026 arm11_common_t * arm11 = target->arch_info;
1027 arm11->trst_active = false;
1028
1029 if (arm11->halt_requested)
1030 return arm11_halt(target);
1031 #endif
1032
1033 return ERROR_OK;
1034 }
1035
1036 int arm11_soft_reset_halt(struct target_s *target)
1037 {
1038 FNC_INFO_NOTIMPLEMENTED;
1039
1040 return ERROR_OK;
1041 }
1042
1043
1044
1045 /* target register access for gdb */
1046 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1047 {
1048 FNC_INFO;
1049
1050 arm11_common_t * arm11 = target->arch_info;
1051
1052 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1053 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1054
1055 {size_t i;
1056 for (i = 16; i < 24; i++)
1057 {
1058 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1059 }}
1060
1061 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1062
1063
1064 {size_t i;
1065 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1066 {
1067 if (arm11_reg_defs[i].gdb_num == -1)
1068 continue;
1069
1070 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1071 }}
1072
1073 return ERROR_OK;
1074 }
1075
1076
1077 /* target memory access
1078 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1079 * count: number of items of <size>
1080 */
1081 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1082 {
1083 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1084
1085 FNC_INFO;
1086
1087 if (target->state != TARGET_HALTED)
1088 {
1089 LOG_WARNING("target was not halted");
1090 return ERROR_TARGET_NOT_HALTED;
1091 }
1092
1093 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1094
1095 arm11_common_t * arm11 = target->arch_info;
1096
1097 arm11_run_instr_data_prepare(arm11);
1098
1099 /* MRC p14,0,r0,c0,c5,0 */
1100 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1101
1102 switch (size)
1103 {
1104 case 1:
1105 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1106 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1107
1108 {size_t i;
1109 for (i = 0; i < count; i++)
1110 {
1111 /* ldrb r1, [r0], #1 */
1112 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1113
1114 u32 res;
1115 /* MCR p14,0,R1,c0,c5,0 */
1116 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1117
1118 *buffer++ = res;
1119 }}
1120
1121 break;
1122
1123 case 2:
1124 {
1125 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1126
1127 u16 * buf16 = (u16*)buffer;
1128
1129 {size_t i;
1130 for (i = 0; i < count; i++)
1131 {
1132 /* ldrh r1, [r0], #2 */
1133 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1134
1135 u32 res;
1136
1137 /* MCR p14,0,R1,c0,c5,0 */
1138 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1139
1140 *buf16++ = res;
1141 }}
1142
1143 break;
1144 }
1145
1146 case 4:
1147
1148 /* LDC p14,c5,[R0],#4 */
1149 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1150 break;
1151 }
1152
1153 arm11_run_instr_data_finish(arm11);
1154
1155 return ERROR_OK;
1156 }
1157
1158 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1159 {
1160 FNC_INFO;
1161
1162 if (target->state != TARGET_HALTED)
1163 {
1164 LOG_WARNING("target was not halted");
1165 return ERROR_TARGET_NOT_HALTED;
1166 }
1167
1168 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1169
1170 arm11_common_t * arm11 = target->arch_info;
1171
1172 arm11_run_instr_data_prepare(arm11);
1173
1174 /* MRC p14,0,r0,c0,c5,0 */
1175 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1176
1177 switch (size)
1178 {
1179 case 1:
1180 {
1181 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1182
1183 {size_t i;
1184 for (i = 0; i < count; i++)
1185 {
1186 /* MRC p14,0,r1,c0,c5,0 */
1187 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1188
1189 /* strb r1, [r0], #1 */
1190 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1191 }}
1192
1193 break;
1194 }
1195
1196 case 2:
1197 {
1198 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1199
1200 u16 * buf16 = (u16*)buffer;
1201
1202 {size_t i;
1203 for (i = 0; i < count; i++)
1204 {
1205 /* MRC p14,0,r1,c0,c5,0 */
1206 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1207
1208 /* strh r1, [r0], #2 */
1209 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1210 }}
1211
1212 break;
1213 }
1214
1215 case 4:
1216 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1217
1218 if (!arm11_config_memwrite_burst)
1219 {
1220 /* STC p14,c5,[R0],#4 */
1221 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1222 }
1223 else
1224 {
1225 /* STC p14,c5,[R0],#4 */
1226 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1227 }
1228
1229 break;
1230 }
1231
1232 #if 1
1233 /* r0 verification */
1234 {
1235 u32 r0;
1236
1237 /* MCR p14,0,R0,c0,c5,0 */
1238 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1239
1240 if (address + size * count != r0)
1241 {
1242 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1243
1244 if (arm11_config_memwrite_burst)
1245 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1246
1247 if (arm11_config_memwrite_error_fatal)
1248 return ERROR_FAIL;
1249 }
1250 }
1251 #endif
1252
1253
1254 arm11_run_instr_data_finish(arm11);
1255
1256
1257
1258
1259 return ERROR_OK;
1260 }
1261
1262
1263 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1264 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1265 {
1266 FNC_INFO;
1267
1268 if (target->state != TARGET_HALTED)
1269 {
1270 LOG_WARNING("target was not halted");
1271 return ERROR_TARGET_NOT_HALTED;
1272 }
1273
1274 return arm11_write_memory(target, address, 4, count, buffer);
1275 }
1276
1277
1278 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1279 {
1280 FNC_INFO_NOTIMPLEMENTED;
1281
1282 return ERROR_OK;
1283 }
1284
1285
1286 /* target break-/watchpoint control
1287 * rw: 0 = write, 1 = read, 2 = access
1288 */
1289 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1290 {
1291 FNC_INFO;
1292
1293 arm11_common_t * arm11 = target->arch_info;
1294
1295 #if 0
1296 if (breakpoint->type == BKPT_SOFT)
1297 {
1298 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1299 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1300 }
1301 #endif
1302
1303 if (!arm11->free_brps)
1304 {
1305 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1306 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1307 }
1308
1309 if (breakpoint->length != 4)
1310 {
1311 LOG_INFO("only breakpoints of four bytes length supported");
1312 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1313 }
1314
1315 arm11->free_brps--;
1316
1317 return ERROR_OK;
1318 }
1319
1320 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1321 {
1322 FNC_INFO;
1323
1324 arm11_common_t * arm11 = target->arch_info;
1325
1326 arm11->free_brps++;
1327
1328 return ERROR_OK;
1329 }
1330
1331 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1332 {
1333 FNC_INFO_NOTIMPLEMENTED;
1334
1335 return ERROR_OK;
1336 }
1337
1338 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1339 {
1340 FNC_INFO_NOTIMPLEMENTED;
1341
1342 return ERROR_OK;
1343 }
1344
1345
1346 /* target algorithm support */
1347 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1348 {
1349 FNC_INFO_NOTIMPLEMENTED;
1350
1351 return ERROR_OK;
1352 }
1353
1354 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1355 {
1356 FNC_INFO;
1357
1358 if (argc < 4)
1359 {
1360 return ERROR_COMMAND_SYNTAX_ERROR;
1361 }
1362
1363 int chain_pos = strtoul(args[3], NULL, 0);
1364
1365 NEW(arm11_common_t, arm11, 1);
1366
1367 arm11->target = target;
1368
1369 /* prepare JTAG information for the new target */
1370 arm11->jtag_info.chain_pos = chain_pos;
1371 arm11->jtag_info.scann_size = 5;
1372
1373 arm_jtag_setup_connection(&arm11->jtag_info);
1374
1375 jtag_device_t *device = jtag_get_device(chain_pos);
1376
1377 if (device->ir_length != 5)
1378 {
1379 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381 }
1382
1383 target->arch_info = arm11;
1384
1385 return ERROR_OK;
1386 }
1387
1388 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1389 {
1390 /* Initialize anything we can set up without talking to the target */
1391 return ERROR_OK;
1392 }
1393
1394 /* talk to the target and set things up */
1395 int arm11_examine(struct target_s *target)
1396 {
1397 FNC_INFO;
1398 int retval;
1399
1400 arm11_common_t * arm11 = target->arch_info;
1401
1402 /* check IDCODE */
1403
1404 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1405
1406 scan_field_t idcode_field;
1407
1408 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1409
1410 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1411
1412 /* check DIDR */
1413
1414 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1415
1416 arm11_add_IR(arm11, ARM11_INTEST, -1);
1417
1418 scan_field_t chain0_fields[2];
1419
1420 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1421 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1422
1423 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1424
1425 if ((retval=jtag_execute_queue())!=ERROR_OK)
1426 return retval;
1427
1428
1429 switch (arm11->device_id & 0x0FFFF000)
1430 {
1431 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1432 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1433 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1434 default:
1435 {
1436 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1437 return ERROR_FAIL;
1438 }
1439 }
1440
1441 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1442
1443 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1444 arm11->debug_version != ARM11_DEBUG_V61)
1445 {
1446 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1447 return ERROR_FAIL;
1448 }
1449
1450
1451 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1452 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1453
1454 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1455 arm11->free_brps = arm11->brp;
1456 arm11->free_wrps = arm11->wrp;
1457
1458 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1459 arm11->device_id,
1460 arm11->implementor,
1461 arm11->didr);
1462
1463 arm11_build_reg_cache(target);
1464
1465
1466 /* as a side-effect this reads DSCR and thus
1467 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1468 * as suggested by the spec.
1469 */
1470
1471 arm11_check_init(arm11, NULL);
1472
1473 target->type->examined = 1;
1474
1475 return ERROR_OK;
1476 }
1477
1478 int arm11_quit(void)
1479 {
1480 FNC_INFO_NOTIMPLEMENTED;
1481
1482 return ERROR_OK;
1483 }
1484
1485 /** Load a register that is marked !valid in the register cache */
1486 int arm11_get_reg(reg_t *reg)
1487 {
1488 FNC_INFO;
1489
1490 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1491
1492 if (target->state != TARGET_HALTED)
1493 {
1494 LOG_WARNING("target was not halted");
1495 return ERROR_TARGET_NOT_HALTED;
1496 }
1497
1498 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1499
1500 #if 0
1501 arm11_common_t *arm11 = target->arch_info;
1502 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1503 #endif
1504
1505 return ERROR_OK;
1506 }
1507
1508 /** Change a value in the register cache */
1509 int arm11_set_reg(reg_t *reg, u8 *buf)
1510 {
1511 FNC_INFO;
1512
1513 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1514 arm11_common_t *arm11 = target->arch_info;
1515 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1516
1517 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1518 reg->valid = 1;
1519 reg->dirty = 1;
1520
1521 return ERROR_OK;
1522 }
1523
1524
1525 void arm11_build_reg_cache(target_t *target)
1526 {
1527 arm11_common_t *arm11 = target->arch_info;
1528
1529 NEW(reg_cache_t, cache, 1);
1530 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1531 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1532
1533 if (arm11_regs_arch_type == -1)
1534 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1535
1536 arm11->reg_list = reg_list;
1537
1538 /* Build the process context cache */
1539 cache->name = "arm11 registers";
1540 cache->next = NULL;
1541 cache->reg_list = reg_list;
1542 cache->num_regs = ARM11_REGCACHE_COUNT;
1543
1544 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1545 (*cache_p) = cache;
1546
1547 // armv7m->core_cache = cache;
1548 // armv7m->process_context = cache;
1549
1550 size_t i;
1551
1552 /* Not very elegant assertion */
1553 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1554 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1555 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1556 {
1557 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1558 exit(-1);
1559 }
1560
1561 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1562 {
1563 reg_t * r = reg_list + i;
1564 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1565 arm11_reg_state_t * rs = arm11_reg_states + i;
1566
1567 r->name = rd->name;
1568 r->size = 32;
1569 r->value = (u8 *)(arm11->reg_values + i);
1570 r->dirty = 0;
1571 r->valid = 0;
1572 r->bitfield_desc = NULL;
1573 r->num_bitfields = 0;
1574 r->arch_type = arm11_regs_arch_type;
1575 r->arch_info = rs;
1576
1577 rs->def_index = i;
1578 rs->target = target;
1579 }
1580 }
1581
1582
1583
1584 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1585 {
1586 if (argc == 0)
1587 {
1588 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1589 return ERROR_OK;
1590 }
1591
1592 if (argc != 1)
1593 return ERROR_COMMAND_SYNTAX_ERROR;
1594
1595 switch (args[0][0])
1596 {
1597 case '0': /* 0 */
1598 case 'f': /* false */
1599 case 'F':
1600 case 'd': /* disable */
1601 case 'D':
1602 *var = false;
1603 break;
1604
1605 case '1': /* 1 */
1606 case 't': /* true */
1607 case 'T':
1608 case 'e': /* enable */
1609 case 'E':
1610 *var = true;
1611 break;
1612 }
1613
1614 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1615
1616 return ERROR_OK;
1617 }
1618
1619
1620 #define BOOL_WRAPPER(name, print_name) \
1621 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1622 { \
1623 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1624 }
1625
1626 #define RC_TOP(name, descr, more) \
1627 { \
1628 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1629 command_t * top_cmd = new_cmd; \
1630 more \
1631 }
1632
1633 #define RC_FINAL(name, descr, handler) \
1634 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1635
1636 #define RC_FINAL_BOOL(name, descr, var) \
1637 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1638
1639
1640 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1641 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1642
1643
1644 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1645 {
1646 if (argc == 1)
1647 {
1648 arm11_vcr = strtoul(args[0], NULL, 0);
1649 }
1650 else if (argc != 0)
1651 {
1652 return ERROR_COMMAND_SYNTAX_ERROR;
1653 }
1654
1655 LOG_INFO("VCR 0x%08X", arm11_vcr);
1656 return ERROR_OK;
1657 }
1658
1659 const u32 arm11_coproc_instruction_limits[] =
1660 {
1661 15, /* coprocessor */
1662 7, /* opcode 1 */
1663 15, /* CRn */
1664 15, /* CRm */
1665 7, /* opcode 2 */
1666 0xFFFFFFFF, /* value */
1667 };
1668
1669 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1670 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1671
1672
1673 arm11_common_t * arm11_find_target(const char * arg)
1674 {
1675 size_t jtag_target = strtoul(arg, NULL, 0);
1676
1677 {target_t * t;
1678 for (t = all_targets; t; t = t->next)
1679 {
1680 if (t->type != &arm11_target)
1681 continue;
1682
1683 arm11_common_t * arm11 = t->arch_info;
1684
1685 if (arm11->jtag_info.chain_pos != jtag_target)
1686 continue;
1687
1688 return arm11;
1689 }}
1690
1691 return 0;
1692 }
1693
1694 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1695 {
1696 if (argc != (read ? 6 : 7))
1697 {
1698 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1699 return -1;
1700 }
1701
1702 arm11_common_t * arm11 = arm11_find_target(args[0]);
1703
1704 if (!arm11)
1705 {
1706 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1707 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1708
1709 return -1;
1710
1711 }
1712
1713 if (arm11->target->state != TARGET_HALTED)
1714 {
1715 LOG_WARNING("target was not halted");
1716 return ERROR_TARGET_NOT_HALTED;
1717 }
1718
1719
1720 u32 values[6];
1721
1722 {size_t i;
1723 for (i = 0; i < (read ? 5 : 6); i++)
1724 {
1725 values[i] = strtoul(args[i + 1], NULL, 0);
1726
1727 if (values[i] > arm11_coproc_instruction_limits[i])
1728 {
1729 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1730 (long)(i + 2), arm11_coproc_instruction_limits[i],
1731 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1732 return -1;
1733 }
1734 }}
1735
1736 u32 instr = 0xEE000010 |
1737 (values[0] << 8) |
1738 (values[1] << 21) |
1739 (values[2] << 16) |
1740 (values[3] << 0) |
1741 (values[4] << 5);
1742
1743 if (read)
1744 instr |= 0x00100000;
1745
1746
1747 arm11_run_instr_data_prepare(arm11);
1748
1749 if (read)
1750 {
1751 u32 result;
1752 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1753
1754 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1755 values[0], values[1], values[2], values[3], values[4], result, result);
1756 }
1757 else
1758 {
1759 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1760
1761 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1762 values[0], values[1],
1763 values[5],
1764 values[2], values[3], values[4]);
1765 }
1766
1767 arm11_run_instr_data_finish(arm11);
1768
1769
1770 return ERROR_OK;
1771 }
1772
1773 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1774 {
1775 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1776 }
1777
1778 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1779 {
1780 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1781 }
1782
1783 int arm11_register_commands(struct command_context_s *cmd_ctx)
1784 {
1785 FNC_INFO;
1786
1787 command_t * top_cmd = NULL;
1788
1789 RC_TOP( "arm11", "arm11 specific commands",
1790
1791 RC_TOP( "memwrite", "Control memory write transfer mode",
1792
1793 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1794 memwrite_burst)
1795
1796 RC_FINAL_BOOL( "error_fatal",
1797 "Terminate program if transfer error was found (default: enabled)",
1798 memwrite_error_fatal)
1799 )
1800
1801 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1802 arm11_handle_vcr)
1803
1804 RC_FINAL( "mrc", "Read Coprocessor register",
1805 arm11_handle_mrc)
1806
1807 RC_FINAL( "mcr", "Write Coprocessor register",
1808 arm11_handle_mcr)
1809 )
1810
1811 return ERROR_OK;
1812 }
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