1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35 #include "algorithm.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 #define FNC_INFO LOG_DEBUG("-")
50 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
52 #define FNC_INFO_NOTIMPLEMENTED
55 static bool arm11_config_memwrite_burst
= true;
56 static bool arm11_config_memwrite_error_fatal
= true;
57 static uint32_t arm11_vcr
= 0;
58 static bool arm11_config_step_irq_enable
= false;
59 static bool arm11_config_hardware_step
= false;
76 ARM11_REGISTER_SPSR_FIQ
,
77 ARM11_REGISTER_SPSR_SVC
,
78 ARM11_REGISTER_SPSR_ABT
,
79 ARM11_REGISTER_SPSR_IRQ
,
80 ARM11_REGISTER_SPSR_UND
,
81 ARM11_REGISTER_SPSR_MON
,
95 enum arm11_regtype type
;
98 /* update arm11_regcache_ids when changing this */
99 static const struct arm11_reg_defs arm11_reg_defs
[] =
101 {"r0", 0, 0, ARM11_REGISTER_CORE
},
102 {"r1", 1, 1, ARM11_REGISTER_CORE
},
103 {"r2", 2, 2, ARM11_REGISTER_CORE
},
104 {"r3", 3, 3, ARM11_REGISTER_CORE
},
105 {"r4", 4, 4, ARM11_REGISTER_CORE
},
106 {"r5", 5, 5, ARM11_REGISTER_CORE
},
107 {"r6", 6, 6, ARM11_REGISTER_CORE
},
108 {"r7", 7, 7, ARM11_REGISTER_CORE
},
109 {"r8", 8, 8, ARM11_REGISTER_CORE
},
110 {"r9", 9, 9, ARM11_REGISTER_CORE
},
111 {"r10", 10, 10, ARM11_REGISTER_CORE
},
112 {"r11", 11, 11, ARM11_REGISTER_CORE
},
113 {"r12", 12, 12, ARM11_REGISTER_CORE
},
114 {"sp", 13, 13, ARM11_REGISTER_CORE
},
115 {"lr", 14, 14, ARM11_REGISTER_CORE
},
116 {"pc", 15, 15, ARM11_REGISTER_CORE
},
118 #if ARM11_REGCACHE_FREGS
119 {"f0", 0, 16, ARM11_REGISTER_FX
},
120 {"f1", 1, 17, ARM11_REGISTER_FX
},
121 {"f2", 2, 18, ARM11_REGISTER_FX
},
122 {"f3", 3, 19, ARM11_REGISTER_FX
},
123 {"f4", 4, 20, ARM11_REGISTER_FX
},
124 {"f5", 5, 21, ARM11_REGISTER_FX
},
125 {"f6", 6, 22, ARM11_REGISTER_FX
},
126 {"f7", 7, 23, ARM11_REGISTER_FX
},
127 {"fps", 0, 24, ARM11_REGISTER_FPS
},
130 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
132 #if ARM11_REGCACHE_MODEREGS
133 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
134 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
135 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
136 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
137 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
138 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
139 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
140 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
142 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
143 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
144 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
146 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
147 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
148 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
150 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
151 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
152 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
154 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
155 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
156 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
159 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
160 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
161 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
164 /* Debug Registers */
165 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
166 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
167 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
170 enum arm11_regcache_ids
173 ARM11_RC_RX
= ARM11_RC_R0
,
188 ARM11_RC_SP
= ARM11_RC_R13
,
190 ARM11_RC_LR
= ARM11_RC_R14
,
192 ARM11_RC_PC
= ARM11_RC_R15
,
194 #if ARM11_REGCACHE_FREGS
196 ARM11_RC_FX
= ARM11_RC_F0
,
209 #if ARM11_REGCACHE_MODEREGS
247 #define ARM11_GDB_REGISTER_COUNT 26
249 /* FIXME these are *identical* to the ARMv4_5 dummies ... except
250 * for their names, and being static vs global, and having different
251 * addresses. Ditto ARMv7a and ARMv7m dummies.
254 static uint8_t arm11_gdb_dummy_fp_value
[12];
256 static struct reg arm11_gdb_dummy_fp_reg
=
258 .name
= "GDB dummy floating-point register",
259 .value
= arm11_gdb_dummy_fp_value
,
266 static uint8_t arm11_gdb_dummy_fps_value
[4];
268 static struct reg arm11_gdb_dummy_fps_reg
=
270 .name
= "GDB dummy floating-point status register",
271 .value
= arm11_gdb_dummy_fps_value
,
279 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
);
280 static int arm11_step(struct target
*target
, int current
,
281 uint32_t address
, int handle_breakpoints
);
283 static int arm11_build_reg_cache(struct target
*target
);
284 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
);
285 static int arm11_get_reg(struct reg
*reg
);
287 static void arm11_record_register_history(struct arm11_common
* arm11
);
288 static void arm11_dump_reg_changes(struct arm11_common
* arm11
);
291 /** Check and if necessary take control of the system
293 * \param arm11 Target state variable.
294 * \param dscr If the current DSCR content is
295 * available a pointer to a word holding the
296 * DSCR can be passed. Otherwise use NULL.
298 static int arm11_check_init(struct arm11_common
*arm11
, uint32_t *dscr
)
302 uint32_t dscr_local_tmp_copy
;
306 dscr
= &dscr_local_tmp_copy
;
308 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
311 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
313 LOG_DEBUG("Bringing target into debug mode");
315 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
316 arm11_write_DSCR(arm11
, *dscr
);
318 /* add further reset initialization here */
320 arm11
->simulate_reset_on_next_halt
= true;
322 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
324 /** \todo TODO: this needs further scrutiny because
325 * arm11_on_enter_debug_state() never gets properly called.
326 * As a result we don't read the actual register states from
330 arm11
->target
->state
= TARGET_HALTED
;
331 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
335 arm11
->target
->state
= TARGET_RUNNING
;
336 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
339 arm11_sc7_clear_vbw(arm11
);
348 (arm11->reg_values[ARM11_RC_##x])
350 /** Save processor state.
352 * This is called when the HALT instruction has succeeded
353 * or on other occasions that stop the processor.
356 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
)
361 for (size_t i
= 0; i
< ARRAY_SIZE(arm11
->reg_values
); i
++)
363 arm11
->reg_list
[i
].valid
= 1;
364 arm11
->reg_list
[i
].dirty
= 0;
368 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
372 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
374 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
376 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
378 struct scan_field chain5_fields
[3];
380 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
381 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
382 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
384 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
388 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
392 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
393 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
394 ARM1136 seems to require this to issue ITR's as well */
396 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
398 /* this executes JTAG queue: */
400 arm11_write_DSCR(arm11
, new_dscr
);
404 Before executing any instruction in debug state you have to drain the write buffer.
405 This ensures that no imprecise Data Aborts can return at a later point:*/
407 /** \todo TODO: Test drain write buffer. */
412 /* MRC p14,0,R0,c5,c10,0 */
413 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
415 /* mcr 15, 0, r0, cr7, cr10, {4} */
416 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
418 uint32_t dscr
= arm11_read_DSCR(arm11
);
420 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
422 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
424 arm11_run_instr_no_data1(arm11
, 0xe320f000);
426 dscr
= arm11_read_DSCR(arm11
);
428 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
435 retval
= arm11_run_instr_data_prepare(arm11
);
436 if (retval
!= ERROR_OK
)
441 /** \todo TODO: handle other mode registers */
443 for (size_t i
= 0; i
< 15; i
++)
445 /* MCR p14,0,R?,c0,c5,0 */
446 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
447 if (retval
!= ERROR_OK
)
453 /* check rDTRfull in DSCR */
455 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
457 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
458 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
459 if (retval
!= ERROR_OK
)
464 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
469 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
470 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
471 if (retval
!= ERROR_OK
)
476 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
477 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
478 if (retval
!= ERROR_OK
)
481 /* adjust PC depending on ARM state */
483 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
485 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
487 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
489 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
493 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
496 if (arm11
->simulate_reset_on_next_halt
)
498 arm11
->simulate_reset_on_next_halt
= false;
500 LOG_DEBUG("Reset c1 Control Register");
502 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
504 /* MCR p15,0,R0,c1,c0,0 */
505 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
506 if (retval
!= ERROR_OK
)
511 retval
= arm11_run_instr_data_finish(arm11
);
512 if (retval
!= ERROR_OK
)
515 arm11_dump_reg_changes(arm11
);
520 void arm11_dump_reg_changes(struct arm11_common
* arm11
)
523 if (!(debug_level
>= LOG_LVL_DEBUG
))
528 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
530 if (!arm11
->reg_list
[i
].valid
)
532 if (arm11
->reg_history
[i
].valid
)
533 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
537 if (arm11
->reg_history
[i
].valid
)
539 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
540 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
544 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
550 /** Restore processor state
552 * This is called in preparation for the RESTART function.
555 static int arm11_leave_debug_state(struct arm11_common
*arm11
)
560 retval
= arm11_run_instr_data_prepare(arm11
);
561 if (retval
!= ERROR_OK
)
564 /** \todo TODO: handle other mode registers */
566 /* restore R1 - R14 */
568 for (size_t i
= 1; i
< 15; i
++)
570 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
573 /* MRC p14,0,r?,c0,c5,0 */
574 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
576 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
579 retval
= arm11_run_instr_data_finish(arm11
);
580 if (retval
!= ERROR_OK
)
583 /* spec says clear wDTR and rDTR; we assume they are clear as
584 otherwise our programming would be sloppy */
588 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
590 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
593 The wDTR/rDTR two registers that are used to send/receive data to/from
594 the core in tandem with corresponding instruction codes that are
595 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
596 registers hold data that was written by one side (CPU or JTAG) and not
597 read out by the other side.
599 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
604 retval
= arm11_run_instr_data_prepare(arm11
);
605 if (retval
!= ERROR_OK
)
608 /* restore original wDTR */
610 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
612 /* MCR p14,0,R0,c0,c5,0 */
613 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
614 if (retval
!= ERROR_OK
)
621 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
622 if (retval
!= ERROR_OK
)
629 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
630 if (retval
!= ERROR_OK
)
636 /* MRC p14,0,r0,c0,c5,0 */
637 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
639 retval
= arm11_run_instr_data_finish(arm11
);
640 if (retval
!= ERROR_OK
)
645 arm11_write_DSCR(arm11
, R(DSCR
));
649 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
651 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
653 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
655 struct scan_field chain5_fields
[3];
657 uint8_t Ready
= 0; /* ignored */
658 uint8_t Valid
= 0; /* ignored */
660 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
661 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
662 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
664 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
667 arm11_record_register_history(arm11
);
672 static void arm11_record_register_history(struct arm11_common
*arm11
)
674 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
676 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
677 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
679 arm11
->reg_list
[i
].valid
= 0;
680 arm11
->reg_list
[i
].dirty
= 0;
685 /* poll current target status */
686 static int arm11_poll(struct target
*target
)
690 struct arm11_common
*arm11
= target_to_arm11(target
);
693 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
695 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
697 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
699 if (dscr
& ARM11_DSCR_CORE_HALTED
)
701 if (target
->state
!= TARGET_HALTED
)
703 enum target_state old_state
= target
->state
;
705 LOG_DEBUG("enter TARGET_HALTED");
706 target
->state
= TARGET_HALTED
;
707 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
708 retval
= arm11_on_enter_debug_state(arm11
);
709 if (retval
!= ERROR_OK
)
712 target_call_event_callbacks(target
,
713 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
718 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
720 LOG_DEBUG("enter TARGET_RUNNING");
721 target
->state
= TARGET_RUNNING
;
722 target
->debug_reason
= DBG_REASON_NOTHALTED
;
728 /* architecture specific status reply */
729 static int arm11_arch_state(struct target
*target
)
731 struct arm11_common
*arm11
= target_to_arm11(target
);
733 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
734 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
741 /* target request support */
742 static int arm11_target_request_data(struct target
*target
,
743 uint32_t size
, uint8_t *buffer
)
745 FNC_INFO_NOTIMPLEMENTED
;
750 /* target execution control */
751 static int arm11_halt(struct target
*target
)
754 struct arm11_common
*arm11
= target_to_arm11(target
);
756 LOG_DEBUG("target->state: %s",
757 target_state_name(target
));
759 if (target
->state
== TARGET_UNKNOWN
)
761 arm11
->simulate_reset_on_next_halt
= true;
764 if (target
->state
== TARGET_HALTED
)
766 LOG_DEBUG("target was already halted");
770 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
772 CHECK_RETVAL(jtag_execute_queue());
779 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
781 if (dscr
& ARM11_DSCR_CORE_HALTED
)
792 if ((timeval_ms()-then
) > 1000)
794 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
801 arm11_on_enter_debug_state(arm11
);
803 enum target_state old_state
= target
->state
;
805 target
->state
= TARGET_HALTED
;
806 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
809 target_call_event_callbacks(target
,
810 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
815 static int arm11_resume(struct target
*target
, int current
,
816 uint32_t address
, int handle_breakpoints
, int debug_execution
)
820 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
821 // current, address, handle_breakpoints, debug_execution);
823 struct arm11_common
*arm11
= target_to_arm11(target
);
825 LOG_DEBUG("target->state: %s",
826 target_state_name(target
));
829 if (target
->state
!= TARGET_HALTED
)
831 LOG_ERROR("Target not halted");
832 return ERROR_TARGET_NOT_HALTED
;
838 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
840 /* clear breakpoints/watchpoints and VCR*/
841 arm11_sc7_clear_vbw(arm11
);
843 /* Set up breakpoints */
844 if (!debug_execution
)
846 /* check if one matches PC and step over it if necessary */
848 struct breakpoint
* bp
;
850 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
852 if (bp
->address
== R(PC
))
854 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
855 arm11_step(target
, 1, 0, 0);
860 /* set all breakpoints */
864 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
866 struct arm11_sc7_action brp
[2];
869 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
870 brp
[0].value
= bp
->address
;
872 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
873 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
875 arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
));
877 LOG_DEBUG("Add BP " ZU
" at %08" PRIx32
"", brp_num
, bp
->address
);
882 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
885 arm11_leave_debug_state(arm11
);
887 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
889 CHECK_RETVAL(jtag_execute_queue());
896 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
898 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
900 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
911 if ((timeval_ms()-then
) > 1000)
913 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
920 if (!debug_execution
)
922 target
->state
= TARGET_RUNNING
;
923 target
->debug_reason
= DBG_REASON_NOTHALTED
;
925 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
929 target
->state
= TARGET_DEBUG_RUNNING
;
930 target
->debug_reason
= DBG_REASON_NOTHALTED
;
932 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
939 static int armv4_5_to_arm11(int reg
)
946 return ARM11_RC_CPSR
;
948 /* FIX!!! handle thumb better! */
949 return ARM11_RC_CPSR
;
951 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
957 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
959 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
961 reg
=armv4_5_to_arm11(reg
);
963 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
966 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
,
967 int reg
, uint32_t value
)
969 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
971 reg
=armv4_5_to_arm11(reg
);
973 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
976 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
,
979 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
981 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
984 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
986 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
988 /* FIX!!!! we should implement thumb for arm11 */
989 return ARMV4_5_STATE_ARM
;
992 static void arm11_sim_set_state(struct arm_sim_interface
*sim
,
993 enum armv4_5_state mode
)
995 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
997 /* FIX!!!! we should implement thumb for arm11 */
998 LOG_ERROR("Not implemetned!");
1002 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
1004 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1006 /* FIX!!!! we should implement something that returns the current mode here!!! */
1007 return ARMV4_5_MODE_USR
;
1010 static int arm11_simulate_step(struct target
*target
, uint32_t *dry_run_pc
)
1012 struct arm_sim_interface sim
;
1014 sim
.user_data
=target
->arch_info
;
1015 sim
.get_reg
=&arm11_sim_get_reg
;
1016 sim
.set_reg
=&arm11_sim_set_reg
;
1017 sim
.get_reg_mode
=&arm11_sim_get_reg
;
1018 sim
.set_reg_mode
=&arm11_sim_set_reg
;
1019 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
1020 sim
.get_mode
=&arm11_sim_get_mode
;
1021 sim
.get_state
=&arm11_sim_get_state
;
1022 sim
.set_state
=&arm11_sim_set_state
;
1024 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
1028 static int arm11_step(struct target
*target
, int current
,
1029 uint32_t address
, int handle_breakpoints
)
1033 LOG_DEBUG("target->state: %s",
1034 target_state_name(target
));
1036 if (target
->state
!= TARGET_HALTED
)
1038 LOG_WARNING("target was not halted");
1039 return ERROR_TARGET_NOT_HALTED
;
1042 struct arm11_common
*arm11
= target_to_arm11(target
);
1047 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
1050 /** \todo TODO: Thumb not supported here */
1052 uint32_t next_instruction
;
1054 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
1056 /* skip over BKPT */
1057 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
1060 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1061 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1062 LOG_DEBUG("Skipping BKPT");
1064 /* skip over Wait for interrupt / Standby */
1065 /* mcr 15, 0, r?, cr7, cr0, {4} */
1066 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
1069 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1070 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1071 LOG_DEBUG("Skipping WFI");
1073 /* ignore B to self */
1074 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
1076 LOG_DEBUG("Not stepping jump to self");
1080 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1083 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1084 * the VCR might be something worth looking into. */
1087 /* Set up breakpoint for stepping */
1089 struct arm11_sc7_action brp
[2];
1092 brp
[0].address
= ARM11_SC7_BVR0
;
1094 brp
[1].address
= ARM11_SC7_BCR0
;
1096 if (arm11_config_hardware_step
)
1098 /* hardware single stepping be used if possible or is it better to
1099 * always use the same code path? Hardware single stepping is not supported
1102 brp
[0].value
= R(PC
);
1103 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1106 /* sets a breakpoint on the next PC(calculated by simulation),
1110 retval
= arm11_simulate_step(target
, &next_pc
);
1111 if (retval
!= ERROR_OK
)
1114 brp
[0].value
= next_pc
;
1115 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1118 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
)));
1123 if (arm11_config_step_irq_enable
)
1124 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1126 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1129 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
1131 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1133 CHECK_RETVAL(jtag_execute_queue());
1141 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1143 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1145 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1146 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1152 then
= timeval_ms();
1156 if ((timeval_ms()-then
) > 1000)
1158 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1165 /* clear breakpoint */
1166 arm11_sc7_clear_vbw(arm11
);
1169 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1171 /* restore default state */
1172 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1176 // target->state = TARGET_HALTED;
1177 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1179 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1184 static int arm11_assert_reset(struct target
*target
)
1188 struct arm11_common
*arm11
= target_to_arm11(target
);
1190 retval
= arm11_check_init(arm11
, NULL
);
1191 if (retval
!= ERROR_OK
)
1194 target
->state
= TARGET_UNKNOWN
;
1196 /* we would very much like to reset into the halted, state,
1197 * but resetting and halting is second best... */
1198 if (target
->reset_halt
)
1200 CHECK_RETVAL(target_halt(target
));
1204 /* srst is funny. We can not do *anything* else while it's asserted
1205 * and it has unkonwn side effects. Make sure no other code runs
1208 * Code below assumes srst:
1210 * - Causes power-on-reset (but of what parts of the system?). Bug
1213 * - Messes us TAP state without asserting trst.
1215 * - There is another bug in the arm11 core. When you generate an access to
1216 * external logic (for example ddr controller via AHB bus) and that block
1217 * is not configured (perhaps it is still held in reset), that transaction
1218 * will never complete. This will hang arm11 core but it will also hang
1219 * JTAG controller. Nothing, short of srst assertion will bring it out of
1224 * - What should the PC be after an srst reset when starting in the halted
1228 jtag_add_reset(0, 1);
1229 jtag_add_reset(0, 0);
1231 /* How long do we have to wait? */
1232 jtag_add_sleep(5000);
1234 /* un-mess up TAP state */
1237 retval
= jtag_execute_queue();
1238 if (retval
!= ERROR_OK
)
1246 static int arm11_deassert_reset(struct target
*target
)
1251 static int arm11_soft_reset_halt(struct target
*target
)
1253 FNC_INFO_NOTIMPLEMENTED
;
1258 /* target register access for gdb */
1259 static int arm11_get_gdb_reg_list(struct target
*target
,
1260 struct reg
**reg_list
[], int *reg_list_size
)
1263 struct arm11_common
*arm11
= target_to_arm11(target
);
1265 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1266 *reg_list
= malloc(sizeof(struct reg
*) * ARM11_GDB_REGISTER_COUNT
);
1268 for (size_t i
= 16; i
< 24; i
++)
1270 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1273 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1275 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1277 if (arm11_reg_defs
[i
].gdb_num
== -1)
1280 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1286 /* target memory access
1287 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1288 * count: number of items of <size>
1290 * arm11_config_memrw_no_increment - in the future we may want to be able
1291 * to read/write a range of data to a "port". a "port" is an action on
1292 * read memory address for some peripheral.
1294 static int arm11_read_memory_inner(struct target
*target
,
1295 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1296 bool arm11_config_memrw_no_increment
)
1298 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1303 if (target
->state
!= TARGET_HALTED
)
1305 LOG_WARNING("target was not halted");
1306 return ERROR_TARGET_NOT_HALTED
;
1309 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1311 struct arm11_common
*arm11
= target_to_arm11(target
);
1313 retval
= arm11_run_instr_data_prepare(arm11
);
1314 if (retval
!= ERROR_OK
)
1317 /* MRC p14,0,r0,c0,c5,0 */
1318 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1319 if (retval
!= ERROR_OK
)
1325 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1326 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1328 for (size_t i
= 0; i
< count
; i
++)
1330 /* ldrb r1, [r0], #1 */
1332 arm11_run_instr_no_data1(arm11
,
1333 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1336 /* MCR p14,0,R1,c0,c5,0 */
1337 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1346 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1348 for (size_t i
= 0; i
< count
; i
++)
1350 /* ldrh r1, [r0], #2 */
1351 arm11_run_instr_no_data1(arm11
,
1352 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1356 /* MCR p14,0,R1,c0,c5,0 */
1357 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1359 uint16_t svalue
= res
;
1360 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1368 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1369 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1370 uint32_t *words
= (uint32_t *)buffer
;
1372 /* LDC p14,c5,[R0],#4 */
1373 /* LDC p14,c5,[R0] */
1374 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1379 return arm11_run_instr_data_finish(arm11
);
1382 static int arm11_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1384 return arm11_read_memory_inner(target
, address
, size
, count
, buffer
, false);
1388 * arm11_config_memrw_no_increment - in the future we may want to be able
1389 * to read/write a range of data to a "port". a "port" is an action on
1390 * read memory address for some peripheral.
1392 static int arm11_write_memory_inner(struct target
*target
,
1393 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1394 bool arm11_config_memrw_no_increment
)
1399 if (target
->state
!= TARGET_HALTED
)
1401 LOG_WARNING("target was not halted");
1402 return ERROR_TARGET_NOT_HALTED
;
1405 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1407 struct arm11_common
*arm11
= target_to_arm11(target
);
1409 retval
= arm11_run_instr_data_prepare(arm11
);
1410 if (retval
!= ERROR_OK
)
1413 /* MRC p14,0,r0,c0,c5,0 */
1414 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1415 if (retval
!= ERROR_OK
)
1418 /* burst writes are not used for single words as those may well be
1419 * reset init script writes.
1421 * The other advantage is that as burst writes are default, we'll
1422 * now exercise both burst and non-burst code paths with the
1423 * default settings, increasing code coverage.
1425 bool burst
= arm11_config_memwrite_burst
&& (count
> 1);
1431 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1433 for (size_t i
= 0; i
< count
; i
++)
1435 /* MRC p14,0,r1,c0,c5,0 */
1436 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1437 if (retval
!= ERROR_OK
)
1440 /* strb r1, [r0], #1 */
1442 retval
= arm11_run_instr_no_data1(arm11
,
1443 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1444 if (retval
!= ERROR_OK
)
1453 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1455 for (size_t i
= 0; i
< count
; i
++)
1458 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1460 /* MRC p14,0,r1,c0,c5,0 */
1461 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1462 if (retval
!= ERROR_OK
)
1465 /* strh r1, [r0], #2 */
1467 retval
= arm11_run_instr_no_data1(arm11
,
1468 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1469 if (retval
!= ERROR_OK
)
1477 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1479 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1480 uint32_t *words
= (uint32_t*)buffer
;
1484 /* STC p14,c5,[R0],#4 */
1485 /* STC p14,c5,[R0]*/
1486 retval
= arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1487 if (retval
!= ERROR_OK
)
1492 /* STC p14,c5,[R0],#4 */
1493 /* STC p14,c5,[R0]*/
1494 retval
= arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1495 if (retval
!= ERROR_OK
)
1503 /* r0 verification */
1504 if (!arm11_config_memrw_no_increment
)
1508 /* MCR p14,0,R0,c0,c5,0 */
1509 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1510 if (retval
!= ERROR_OK
)
1513 if (address
+ size
* count
!= r0
)
1515 LOG_ERROR("Data transfer failed. Expected end "
1516 "address 0x%08x, got 0x%08x",
1517 (unsigned) (address
+ size
* count
),
1521 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1523 if (arm11_config_memwrite_error_fatal
)
1528 return arm11_run_instr_data_finish(arm11
);
1531 static int arm11_write_memory(struct target
*target
,
1532 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1534 return arm11_write_memory_inner(target
, address
, size
, count
, buffer
, false);
1537 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1538 static int arm11_bulk_write_memory(struct target
*target
,
1539 uint32_t address
, uint32_t count
, uint8_t *buffer
)
1543 if (target
->state
!= TARGET_HALTED
)
1545 LOG_WARNING("target was not halted");
1546 return ERROR_TARGET_NOT_HALTED
;
1549 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1552 /* target break-/watchpoint control
1553 * rw: 0 = write, 1 = read, 2 = access
1555 static int arm11_add_breakpoint(struct target
*target
,
1556 struct breakpoint
*breakpoint
)
1559 struct arm11_common
*arm11
= target_to_arm11(target
);
1562 if (breakpoint
->type
== BKPT_SOFT
)
1564 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1565 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1569 if (!arm11
->free_brps
)
1571 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1572 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1575 if (breakpoint
->length
!= 4)
1577 LOG_DEBUG("only breakpoints of four bytes length supported");
1578 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1586 static int arm11_remove_breakpoint(struct target
*target
,
1587 struct breakpoint
*breakpoint
)
1590 struct arm11_common
*arm11
= target_to_arm11(target
);
1597 static int arm11_add_watchpoint(struct target
*target
,
1598 struct watchpoint
*watchpoint
)
1600 FNC_INFO_NOTIMPLEMENTED
;
1605 static int arm11_remove_watchpoint(struct target
*target
,
1606 struct watchpoint
*watchpoint
)
1608 FNC_INFO_NOTIMPLEMENTED
;
1613 // HACKHACKHACK - FIXME mode/state
1614 /* target algorithm support */
1615 static int arm11_run_algorithm(struct target
*target
,
1616 int num_mem_params
, struct mem_param
*mem_params
,
1617 int num_reg_params
, struct reg_param
*reg_params
,
1618 uint32_t entry_point
, uint32_t exit_point
,
1619 int timeout_ms
, void *arch_info
)
1621 struct arm11_common
*arm11
= target_to_arm11(target
);
1622 // enum armv4_5_state core_state = arm11->core_state;
1623 // enum armv4_5_mode core_mode = arm11->core_mode;
1624 uint32_t context
[16];
1626 int exit_breakpoint_size
= 0;
1627 int retval
= ERROR_OK
;
1628 LOG_DEBUG("Running algorithm");
1631 if (target
->state
!= TARGET_HALTED
)
1633 LOG_WARNING("target not halted");
1634 return ERROR_TARGET_NOT_HALTED
;
1638 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1639 // return ERROR_FAIL;
1642 for (unsigned i
= 0; i
< 16; i
++)
1644 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1645 LOG_DEBUG("Save %u: 0x%" PRIx32
"", i
, context
[i
]);
1648 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1649 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1651 for (int i
= 0; i
< num_mem_params
; i
++)
1653 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1656 // Set register parameters
1657 for (int i
= 0; i
< num_reg_params
; i
++)
1659 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1662 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1663 return ERROR_INVALID_ARGUMENTS
;
1666 if (reg
->size
!= reg_params
[i
].size
)
1668 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1669 return ERROR_INVALID_ARGUMENTS
;
1671 arm11_set_reg(reg
,reg_params
[i
].value
);
1672 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1675 exit_breakpoint_size
= 4;
1677 /* arm11->core_state = arm11_algorithm_info->core_state;
1678 if (arm11->core_state == ARMV4_5_STATE_ARM)
1679 exit_breakpoint_size = 4;
1680 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1681 exit_breakpoint_size = 2;
1684 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1690 /* arm11 at this point only supports ARM not THUMB mode
1691 however if this test needs to be reactivated the current state can be read back
1694 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1696 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1697 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1698 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1699 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1703 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1705 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1706 retval
= ERROR_TARGET_FAILURE
;
1710 // no debug, otherwise breakpoint is not set
1711 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1713 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1715 if (target
->state
!= TARGET_HALTED
)
1717 CHECK_RETVAL(target_halt(target
));
1719 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1721 retval
= ERROR_TARGET_TIMEOUT
;
1723 goto del_breakpoint
;
1726 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1728 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1729 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1730 retval
= ERROR_TARGET_TIMEOUT
;
1731 goto del_breakpoint
;
1734 for (int i
= 0; i
< num_mem_params
; i
++)
1736 if (mem_params
[i
].direction
!= PARAM_OUT
)
1737 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1740 for (int i
= 0; i
< num_reg_params
; i
++)
1742 if (reg_params
[i
].direction
!= PARAM_OUT
)
1744 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1747 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1748 retval
= ERROR_INVALID_ARGUMENTS
;
1749 goto del_breakpoint
;
1752 if (reg
->size
!= reg_params
[i
].size
)
1754 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1755 retval
= ERROR_INVALID_ARGUMENTS
;
1756 goto del_breakpoint
;
1759 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1764 breakpoint_remove(target
, exit_point
);
1768 for (size_t i
= 0; i
< 16; i
++)
1770 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1771 arm11
->reg_list
[i
].name
, context
[i
]);
1772 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1774 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1775 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1777 // arm11->core_state = core_state;
1778 // arm11->core_mode = core_mode;
1783 static int arm11_target_create(struct target
*target
, Jim_Interp
*interp
)
1787 NEW(struct arm11_common
, arm11
, 1);
1789 arm11
->target
= target
;
1791 if (target
->tap
== NULL
)
1794 if (target
->tap
->ir_length
!= 5)
1796 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1797 return ERROR_COMMAND_SYNTAX_ERROR
;
1800 armv4_5_init_arch_info(target
, &arm11
->arm
);
1802 arm11
->jtag_info
.tap
= target
->tap
;
1803 arm11
->jtag_info
.scann_size
= 5;
1804 arm11
->jtag_info
.scann_instr
= ARM11_SCAN_N
;
1805 /* cur_scan_chain == 0 */
1806 arm11
->jtag_info
.intest_instr
= ARM11_INTEST
;
1811 static int arm11_init_target(struct command_context
*cmd_ctx
,
1812 struct target
*target
)
1814 /* Initialize anything we can set up without talking to the target */
1815 return arm11_build_reg_cache(target
);
1818 /* talk to the target and set things up */
1819 static int arm11_examine(struct target
*target
)
1824 struct arm11_common
*arm11
= target_to_arm11(target
);
1828 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1830 struct scan_field idcode_field
;
1832 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1834 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1838 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1840 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1842 struct scan_field chain0_fields
[2];
1844 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1845 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1847 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields
), chain0_fields
, TAP_IDLE
);
1849 CHECK_RETVAL(jtag_execute_queue());
1851 switch (arm11
->device_id
& 0x0FFFF000)
1853 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1854 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1855 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1857 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1861 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1863 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1864 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1866 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1870 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1871 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1873 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1874 arm11
->free_brps
= arm11
->brp
;
1875 arm11
->free_wrps
= arm11
->wrp
;
1877 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1879 (int)(arm11
->implementor
),
1882 /* as a side-effect this reads DSCR and thus
1883 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1884 * as suggested by the spec.
1887 retval
= arm11_check_init(arm11
, NULL
);
1888 if (retval
!= ERROR_OK
)
1891 /* ETM on ARM11 still uses original scanchain 6 access mode */
1892 if (arm11
->arm
.etm
&& !target_was_examined(target
)) {
1893 *register_get_last_cache_p(&target
->reg_cache
) =
1894 etm_build_reg_cache(target
, &arm11
->jtag_info
,
1896 retval
= etm_setup(target
);
1899 target_set_examined(target
);
1905 /** Load a register that is marked !valid in the register cache */
1906 static int arm11_get_reg(struct reg
*reg
)
1910 struct target
* target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1912 if (target
->state
!= TARGET_HALTED
)
1914 LOG_WARNING("target was not halted");
1915 return ERROR_TARGET_NOT_HALTED
;
1918 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1921 struct arm11_common
*arm11
= target_to_arm11(target
);
1922 const struct arm11_reg_defs
*arm11_reg_info
= arm11_reg_defs
+ ((struct arm11_reg_state
*)reg
->arch_info
)->def_index
;
1928 /** Change a value in the register cache */
1929 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
)
1933 struct target
*target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1934 struct arm11_common
*arm11
= target_to_arm11(target
);
1935 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1937 arm11
->reg_values
[((struct arm11_reg_state
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1944 static const struct reg_arch_type arm11_reg_type
= {
1945 .get
= arm11_get_reg
,
1946 .set
= arm11_set_reg
,
1949 static int arm11_build_reg_cache(struct target
*target
)
1951 struct arm11_common
*arm11
= target_to_arm11(target
);
1953 NEW(struct reg_cache
, cache
, 1);
1954 NEW(struct reg
, reg_list
, ARM11_REGCACHE_COUNT
);
1955 NEW(struct arm11_reg_state
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1957 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1958 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1960 arm11
->reg_list
= reg_list
;
1962 /* Build the process context cache */
1963 cache
->name
= "arm11 registers";
1965 cache
->reg_list
= reg_list
;
1966 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1968 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1971 arm11
->core_cache
= cache
;
1972 // armv7m->process_context = cache;
1976 /* Not very elegant assertion */
1977 if (ARM11_REGCACHE_COUNT
!= ARRAY_SIZE(arm11
->reg_values
) ||
1978 ARM11_REGCACHE_COUNT
!= ARRAY_SIZE(arm11_reg_defs
) ||
1979 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1981 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, ARRAY_SIZE(arm11
->reg_values
), ARRAY_SIZE(arm11_reg_defs
), ARM11_RC_MAX
);
1985 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1987 struct reg
* r
= reg_list
+ i
;
1988 const struct arm11_reg_defs
* rd
= arm11_reg_defs
+ i
;
1989 struct arm11_reg_state
* rs
= arm11_reg_states
+ i
;
1993 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1996 r
->type
= &arm11_reg_type
;
2000 rs
->target
= target
;
2006 static COMMAND_HELPER(arm11_handle_bool
, bool *var
, char *name
)
2010 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
2015 return ERROR_COMMAND_SYNTAX_ERROR
;
2017 switch (CMD_ARGV
[0][0])
2020 case 'f': /* false */
2022 case 'd': /* disable */
2028 case 't': /* true */
2030 case 'e': /* enable */
2036 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
2041 #define BOOL_WRAPPER(name, print_name) \
2042 COMMAND_HANDLER(arm11_handle_bool_##name) \
2044 return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2045 &arm11_config_##name, print_name); \
2048 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
2049 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
2050 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
2051 BOOL_WRAPPER(hardware_step
, "hardware single step")
2053 COMMAND_HANDLER(arm11_handle_vcr
)
2059 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], arm11_vcr
);
2062 return ERROR_COMMAND_SYNTAX_ERROR
;
2065 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
2069 static const uint32_t arm11_coproc_instruction_limits
[] =
2071 15, /* coprocessor */
2076 0xFFFFFFFF, /* value */
2079 static int arm11_mrc_inner(struct target
*target
, int cpnum
,
2080 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
2081 uint32_t *value
, bool read
)
2084 struct arm11_common
*arm11
= target_to_arm11(target
);
2086 if (target
->state
!= TARGET_HALTED
)
2088 LOG_ERROR("Target not halted");
2092 uint32_t instr
= 0xEE000010 |
2100 instr
|= 0x00100000;
2102 retval
= arm11_run_instr_data_prepare(arm11
);
2103 if (retval
!= ERROR_OK
)
2108 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, instr
, value
);
2109 if (retval
!= ERROR_OK
)
2114 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, instr
, *value
);
2115 if (retval
!= ERROR_OK
)
2119 return arm11_run_instr_data_finish(arm11
);
2122 static int arm11_mrc(struct target
*target
, int cpnum
,
2123 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
2125 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, value
, true);
2128 static int arm11_mcr(struct target
*target
, int cpnum
,
2129 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
2131 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, &value
, false);
2134 static int arm11_register_commands(struct command_context
*cmd_ctx
)
2138 struct command
*top_cmd
, *mw_cmd
;
2140 armv4_5_register_commands(cmd_ctx
);
2142 top_cmd
= register_command(cmd_ctx
, NULL
, "arm11",
2143 NULL
, COMMAND_ANY
, NULL
);
2145 /* "hardware_step" is only here to check if the default
2146 * simulate + breakpoint implementation is broken.
2147 * TEMPORARY! NOT DOCUMENTED!
2149 register_command(cmd_ctx
, top_cmd
, "hardware_step",
2150 arm11_handle_bool_hardware_step
, COMMAND_ANY
,
2151 "DEBUG ONLY - Hardware single stepping"
2152 " (default: disabled)");
2154 mw_cmd
= register_command(cmd_ctx
, top_cmd
, "memwrite",
2155 NULL
, COMMAND_ANY
, NULL
);
2156 register_command(cmd_ctx
, mw_cmd
, "burst",
2157 arm11_handle_bool_memwrite_burst
, COMMAND_ANY
,
2158 "Enable/Disable non-standard but fast burst mode"
2159 " (default: enabled)");
2160 register_command(cmd_ctx
, mw_cmd
, "error_fatal",
2161 arm11_handle_bool_memwrite_error_fatal
, COMMAND_ANY
,
2162 "Terminate program if transfer error was found"
2163 " (default: enabled)");
2165 register_command(cmd_ctx
, top_cmd
, "step_irq_enable",
2166 arm11_handle_bool_step_irq_enable
, COMMAND_ANY
,
2167 "Enable interrupts while stepping"
2168 " (default: disabled)");
2169 register_command(cmd_ctx
, top_cmd
, "vcr",
2170 arm11_handle_vcr
, COMMAND_ANY
,
2171 "Control (Interrupt) Vector Catch Register");
2173 return etm_register_commands(cmd_ctx
);
2176 /** Holds methods for ARM11xx targets. */
2177 struct target_type arm11_target
= {
2181 .arch_state
= arm11_arch_state
,
2183 .target_request_data
= arm11_target_request_data
,
2186 .resume
= arm11_resume
,
2189 .assert_reset
= arm11_assert_reset
,
2190 .deassert_reset
= arm11_deassert_reset
,
2191 .soft_reset_halt
= arm11_soft_reset_halt
,
2193 .get_gdb_reg_list
= arm11_get_gdb_reg_list
,
2195 .read_memory
= arm11_read_memory
,
2196 .write_memory
= arm11_write_memory
,
2198 .bulk_write_memory
= arm11_bulk_write_memory
,
2200 .checksum_memory
= arm_checksum_memory
,
2201 .blank_check_memory
= arm_blank_check_memory
,
2203 .add_breakpoint
= arm11_add_breakpoint
,
2204 .remove_breakpoint
= arm11_remove_breakpoint
,
2205 .add_watchpoint
= arm11_add_watchpoint
,
2206 .remove_watchpoint
= arm11_remove_watchpoint
,
2208 .run_algorithm
= arm11_run_algorithm
,
2210 .register_commands
= arm11_register_commands
,
2211 .target_create
= arm11_target_create
,
2212 .init_target
= arm11_init_target
,
2213 .examine
= arm11_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)