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905a5d77eda112297191ebf6e508db499e76235f
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm11.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35
36 #if 0
37 #define FNC_INFO DEBUG("-")
38 #else
39 #define FNC_INFO
40 #endif
41
42 #if 1
43 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
44 #else
45 #define FNC_INFO_NOTIMPLEMENTED
46 #endif
47
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
49
50
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 u32 arm11_vcr = 0;
54
55
56 #define ARM11_HANDLER(x) \
57 .x = arm11_##x
58
59 target_type_t arm11_target =
60 {
61 .name = "arm11",
62
63 ARM11_HANDLER(poll),
64 ARM11_HANDLER(arch_state),
65
66 ARM11_HANDLER(target_request_data),
67
68 ARM11_HANDLER(halt),
69 ARM11_HANDLER(resume),
70 ARM11_HANDLER(step),
71
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75 ARM11_HANDLER(prepare_reset_halt),
76
77 ARM11_HANDLER(get_gdb_reg_list),
78
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
81
82 ARM11_HANDLER(bulk_write_memory),
83
84 ARM11_HANDLER(checksum_memory),
85
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
90
91 ARM11_HANDLER(run_algorithm),
92
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_command),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(quit),
97 };
98
99 int arm11_regs_arch_type = -1;
100
101
102 enum arm11_regtype
103 {
104 ARM11_REGISTER_CORE,
105 ARM11_REGISTER_CPSR,
106
107 ARM11_REGISTER_FX,
108 ARM11_REGISTER_FPS,
109
110 ARM11_REGISTER_FIQ,
111 ARM11_REGISTER_SVC,
112 ARM11_REGISTER_ABT,
113 ARM11_REGISTER_IRQ,
114 ARM11_REGISTER_UND,
115 ARM11_REGISTER_MON,
116
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
123
124 /* debug regs */
125 ARM11_REGISTER_DSCR,
126 ARM11_REGISTER_WDTR,
127 ARM11_REGISTER_RDTR,
128 };
129
130
131 typedef struct arm11_reg_defs_s
132 {
133 char * name;
134 u32 num;
135 int gdb_num;
136 enum arm11_regtype type;
137 } arm11_reg_defs_t;
138
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
141 {
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
158
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
169 #endif
170
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
172
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
182
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
186
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
190
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
194
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
198
199 /* ARM1176 only */
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
203 #endif
204
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
209 };
210
211 enum arm11_regcache_ids
212 {
213 ARM11_RC_R0,
214 ARM11_RC_RX = ARM11_RC_R0,
215
216 ARM11_RC_R1,
217 ARM11_RC_R2,
218 ARM11_RC_R3,
219 ARM11_RC_R4,
220 ARM11_RC_R5,
221 ARM11_RC_R6,
222 ARM11_RC_R7,
223 ARM11_RC_R8,
224 ARM11_RC_R9,
225 ARM11_RC_R10,
226 ARM11_RC_R11,
227 ARM11_RC_R12,
228 ARM11_RC_R13,
229 ARM11_RC_SP = ARM11_RC_R13,
230 ARM11_RC_R14,
231 ARM11_RC_LR = ARM11_RC_R14,
232 ARM11_RC_R15,
233 ARM11_RC_PC = ARM11_RC_R15,
234
235 #if ARM11_REGCACHE_FREGS
236 ARM11_RC_F0,
237 ARM11_RC_FX = ARM11_RC_F0,
238 ARM11_RC_F1,
239 ARM11_RC_F2,
240 ARM11_RC_F3,
241 ARM11_RC_F4,
242 ARM11_RC_F5,
243 ARM11_RC_F6,
244 ARM11_RC_F7,
245 ARM11_RC_FPS,
246 #endif
247
248 ARM11_RC_CPSR,
249
250 #if ARM11_REGCACHE_MODEREGS
251 ARM11_RC_R8_FIQ,
252 ARM11_RC_R9_FIQ,
253 ARM11_RC_R10_FIQ,
254 ARM11_RC_R11_FIQ,
255 ARM11_RC_R12_FIQ,
256 ARM11_RC_R13_FIQ,
257 ARM11_RC_R14_FIQ,
258 ARM11_RC_SPSR_FIQ,
259
260 ARM11_RC_R13_SVC,
261 ARM11_RC_R14_SVC,
262 ARM11_RC_SPSR_SVC,
263
264 ARM11_RC_R13_ABT,
265 ARM11_RC_R14_ABT,
266 ARM11_RC_SPSR_ABT,
267
268 ARM11_RC_R13_IRQ,
269 ARM11_RC_R14_IRQ,
270 ARM11_RC_SPSR_IRQ,
271
272 ARM11_RC_R13_UND,
273 ARM11_RC_R14_UND,
274 ARM11_RC_SPSR_UND,
275
276 ARM11_RC_R13_MON,
277 ARM11_RC_R14_MON,
278 ARM11_RC_SPSR_MON,
279 #endif
280
281 ARM11_RC_DSCR,
282 ARM11_RC_WDTR,
283 ARM11_RC_RDTR,
284
285
286 ARM11_RC_MAX,
287 };
288
289 #define ARM11_GDB_REGISTER_COUNT 26
290
291 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292
293 reg_t arm11_gdb_dummy_fp_reg =
294 {
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
296 };
297
298 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299
300 reg_t arm11_gdb_dummy_fps_reg =
301 {
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
303 };
304
305
306
307 /** Check and if necessary take control of the system
308 *
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
313 */
314 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
315 {
316 FNC_INFO;
317
318 u32 dscr_local_tmp_copy;
319
320 if (!dscr)
321 {
322 dscr = &dscr_local_tmp_copy;
323 *dscr = arm11_read_DSCR(arm11);
324 }
325
326 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
327 {
328 DEBUG("Bringing target into debug mode");
329
330 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
331 arm11_write_DSCR(arm11, *dscr);
332
333 /* add further reset initialization here */
334
335 if (*dscr & ARM11_DSCR_CORE_HALTED)
336 {
337 arm11->target->state = TARGET_HALTED;
338 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
339 }
340 else
341 {
342 arm11->target->state = TARGET_RUNNING;
343 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
344 }
345
346 arm11_sc7_clear_vbw(arm11);
347 }
348 }
349
350
351
352 #define R(x) \
353 (arm11->reg_values[ARM11_RC_##x])
354
355 /** Save processor state.
356 *
357 * This is called when the HALT instruction has succeeded
358 * or on other occasions that stop the processor.
359 *
360 */
361 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
362 {
363 FNC_INFO;
364
365 {size_t i;
366 for(i = 0; i < asizeof(arm11->reg_values); i++)
367 {
368 arm11->reg_list[i].valid = 1;
369 arm11->reg_list[i].dirty = 0;
370 }}
371
372 /* Save DSCR */
373
374 R(DSCR) = arm11_read_DSCR(arm11);
375
376 /* Save wDTR */
377
378 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
379 {
380 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
381
382 arm11_add_IR(arm11, ARM11_INTEST, -1);
383
384 scan_field_t chain5_fields[3];
385
386 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
387 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
388 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
389
390 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
391 }
392 else
393 {
394 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
395 }
396
397
398 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
399 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
400 ARM1136 seems to require this to issue ITR's as well */
401
402 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
403
404 /* this executes JTAG queue: */
405
406 arm11_write_DSCR(arm11, new_dscr);
407
408 // jtag_execute_queue();
409
410
411
412 // DEBUG("SAVE DSCR %08x", R(DSCR));
413
414 // if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
415 // DEBUG("SAVE wDTR %08x", R(WDTR));
416
417
418 /* From the spec:
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
421
422 /** \todo TODO: Test drain write buffer. */
423
424 #if 0
425 while (1)
426 {
427 /* MRC p14,0,R0,c5,c10,0 */
428 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
429
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
432
433 u32 dscr = arm11_read_DSCR(arm11);
434
435 DEBUG("DRAIN, DSCR %08x", dscr);
436
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
438 {
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
440
441 dscr = arm11_read_DSCR(arm11);
442
443 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
444
445 break;
446 }
447 }
448 #endif
449
450
451 arm11_run_instr_data_prepare(arm11);
452
453 /* save r0 - r14 */
454
455
456 /** \todo TODO: handle other mode registers */
457
458 {size_t i;
459 for (i = 0; i < 15; i++)
460 {
461 /* MCR p14,0,R?,c0,c5,0 */
462 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
463 }}
464
465
466 /* save rDTR */
467
468 /* check rDTRfull in DSCR */
469
470 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
471 {
472 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
473 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
474 }
475 else
476 {
477 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
478 }
479
480 /* save CPSR */
481
482 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
484
485 /* save PC */
486
487 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
488 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
489
490 /* adjust PC depending on ARM state */
491
492 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 0;
495 }
496 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 4;
499 }
500 else /* ARM state */
501 {
502 arm11->reg_values[ARM11_RC_PC] -= 8;
503 }
504
505 // DEBUG("SAVE PC %08x", R(PC));
506
507 arm11_run_instr_data_finish(arm11);
508
509 arm11_dump_reg_changes(arm11);
510 }
511
512 void arm11_dump_reg_changes(arm11_common_t * arm11)
513 {
514 {size_t i;
515 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
516 {
517 if (!arm11->reg_list[i].valid)
518 {
519 if (arm11->reg_history[i].valid)
520 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
521 }
522 else
523 {
524 if (arm11->reg_history[i].valid)
525 {
526 if (arm11->reg_history[i].value != arm11->reg_values[i])
527 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
528 }
529 else
530 {
531 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
532 }
533 }
534 }}
535 }
536
537
538 /** Restore processor state
539 *
540 * This is called in preparation for the RESTART function.
541 *
542 */
543 void arm11_leave_debug_state(arm11_common_t * arm11)
544 {
545 FNC_INFO;
546
547 arm11_run_instr_data_prepare(arm11);
548
549 /** \todo TODO: handle other mode registers */
550
551 /* restore R1 - R14 */
552 {size_t i;
553 for (i = 1; i < 15; i++)
554 {
555 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
556 continue;
557
558 /* MRC p14,0,r?,c0,c5,0 */
559 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
560
561 // DEBUG("RESTORE R%d %08x", i, R(RX + i));
562 }}
563
564 arm11_run_instr_data_finish(arm11);
565
566
567 /* spec says clear wDTR and rDTR; we assume they are clear as
568 otherwise our programming would be sloppy */
569
570 {
571 u32 DSCR = arm11_read_DSCR(arm11);
572
573 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
574 {
575 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
576 }
577 }
578
579 arm11_run_instr_data_prepare(arm11);
580
581 /* restore original wDTR */
582
583 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
584 {
585 /* MCR p14,0,R0,c0,c5,0 */
586 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
587 }
588
589 /* restore CPSR */
590
591 /* MSR CPSR,R0*/
592 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
593
594
595 /* restore PC */
596
597 /* MOV PC,R0 */
598 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
599
600
601 /* restore R0 */
602
603 /* MRC p14,0,r0,c0,c5,0 */
604 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
605
606 arm11_run_instr_data_finish(arm11);
607
608
609 /* restore DSCR */
610
611 arm11_write_DSCR(arm11, R(DSCR));
612
613
614 /* restore rDTR */
615
616 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
617 {
618 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
619
620 arm11_add_IR(arm11, ARM11_EXTEST, -1);
621
622 scan_field_t chain5_fields[3];
623
624 u8 Ready = 0; /* ignored */
625 u8 Valid = 0; /* ignored */
626
627 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
628 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
629 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
630
631 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
632 }
633
634 arm11_record_register_history(arm11);
635 }
636
637 void arm11_record_register_history(arm11_common_t * arm11)
638 {
639 {size_t i;
640 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
641 {
642 arm11->reg_history[i].value = arm11->reg_values[i];
643 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
644
645 arm11->reg_list[i].valid = 0;
646 arm11->reg_list[i].dirty = 0;
647 }}
648 }
649
650
651 /* poll current target status */
652 int arm11_poll(struct target_s *target)
653 {
654 FNC_INFO;
655
656 arm11_common_t * arm11 = target->arch_info;
657
658 if (arm11->trst_active)
659 return ERROR_OK;
660
661 u32 dscr = arm11_read_DSCR(arm11);
662
663 DEBUG("DSCR %08x", dscr);
664
665 arm11_check_init(arm11, &dscr);
666
667 if (dscr & ARM11_DSCR_CORE_HALTED)
668 {
669 if (target->state != TARGET_HALTED)
670 {
671 enum target_state old_state = target->state;
672
673 DEBUG("enter TARGET_HALTED");
674 target->state = TARGET_HALTED;
675 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
676 arm11_on_enter_debug_state(arm11);
677
678 target_call_event_callbacks(target,
679 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
680 }
681 }
682 else
683 {
684 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
685 {
686 DEBUG("enter TARGET_RUNNING");
687 target->state = TARGET_RUNNING;
688 target->debug_reason = DBG_REASON_NOTHALTED;
689 }
690 }
691
692 return ERROR_OK;
693 }
694 /* architecture specific status reply */
695 int arm11_arch_state(struct target_s *target)
696 {
697 FNC_INFO_NOTIMPLEMENTED;
698
699 return ERROR_OK;
700 }
701
702
703 /* target request support */
704 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
705 {
706 FNC_INFO_NOTIMPLEMENTED;
707
708 return ERROR_OK;
709 }
710
711
712
713 /* target execution control */
714 int arm11_halt(struct target_s *target)
715 {
716 FNC_INFO;
717
718 arm11_common_t * arm11 = target->arch_info;
719
720 DEBUG("target->state: %s", target_state_strings[target->state]);
721
722 if (target->state == TARGET_HALTED)
723 {
724 WARNING("target was already halted");
725 return ERROR_TARGET_ALREADY_HALTED;
726 }
727
728 if (arm11->trst_active)
729 {
730 arm11->halt_requested = true;
731 return ERROR_OK;
732 }
733
734 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
735
736 jtag_execute_queue();
737
738 u32 dscr;
739
740 while (1)
741 {
742 dscr = arm11_read_DSCR(arm11);
743
744 if (dscr & ARM11_DSCR_CORE_HALTED)
745 break;
746 }
747
748 arm11_on_enter_debug_state(arm11);
749
750 enum target_state old_state = target->state;
751
752 target->state = TARGET_HALTED;
753 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
754
755 target_call_event_callbacks(target,
756 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
757
758 return ERROR_OK;
759 }
760
761
762 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
763 {
764 FNC_INFO;
765
766 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
767 // current, address, handle_breakpoints, debug_execution);
768
769 arm11_common_t * arm11 = target->arch_info;
770
771 DEBUG("target->state: %s", target_state_strings[target->state]);
772
773 if (target->state != TARGET_HALTED)
774 {
775 WARNING("target was not halted");
776 return ERROR_TARGET_NOT_HALTED;
777 }
778
779 if (!current)
780 R(PC) = address;
781
782 INFO("RESUME PC %08x", R(PC));
783
784 /* clear breakpoints/watchpoints and VCR*/
785 arm11_sc7_clear_vbw(arm11);
786
787 /* Set up breakpoints */
788 if (!debug_execution)
789 {
790 /* check if one matches PC and step over it if necessary */
791
792 breakpoint_t * bp;
793
794 for (bp = target->breakpoints; bp; bp = bp->next)
795 {
796 if (bp->address == R(PC))
797 {
798 DEBUG("must step over %08x", bp->address);
799 arm11_step(target, 1, 0, 0);
800 break;
801 }
802 }
803
804 /* set all breakpoints */
805
806 size_t brp_num = 0;
807
808 for (bp = target->breakpoints; bp; bp = bp->next)
809 {
810 arm11_sc7_action_t brp[2];
811
812 brp[0].write = 1;
813 brp[0].address = ARM11_SC7_BVR0 + brp_num;
814 brp[0].value = bp->address;
815 brp[1].write = 1;
816 brp[1].address = ARM11_SC7_BCR0 + brp_num;
817 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
818
819 arm11_sc7_run(arm11, brp, asizeof(brp));
820
821 DEBUG("Add BP %d at %08x", brp_num, bp->address);
822
823 brp_num++;
824 }
825
826 arm11_sc7_set_vcr(arm11, arm11_vcr);
827 }
828
829
830 arm11_leave_debug_state(arm11);
831
832 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
833
834 jtag_execute_queue();
835
836 while (1)
837 {
838 u32 dscr = arm11_read_DSCR(arm11);
839
840 DEBUG("DSCR %08x", dscr);
841
842 if (dscr & ARM11_DSCR_CORE_RESTARTED)
843 break;
844 }
845
846 if (!debug_execution)
847 {
848 target->state = TARGET_RUNNING;
849 target->debug_reason = DBG_REASON_NOTHALTED;
850 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
851 }
852 else
853 {
854 target->state = TARGET_DEBUG_RUNNING;
855 target->debug_reason = DBG_REASON_NOTHALTED;
856 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
857 }
858
859 return ERROR_OK;
860 }
861
862 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
863 {
864 FNC_INFO;
865
866 DEBUG("target->state: %s", target_state_strings[target->state]);
867
868 if (target->state != TARGET_HALTED)
869 {
870 WARNING("target was not halted");
871 return ERROR_TARGET_NOT_HALTED;
872 }
873
874 arm11_common_t * arm11 = target->arch_info;
875
876 if (!current)
877 R(PC) = address;
878
879 INFO("STEP PC %08x", R(PC));
880
881 /** \todo TODO: Thumb not supported here */
882
883 u32 next_instruction;
884
885 arm11_read_memory_word(arm11, R(PC), &next_instruction);
886
887 /** skip over BKPT */
888 if ((next_instruction & 0xFFF00070) == 0xe1200070)
889 {
890 R(PC) += 4;
891 arm11->reg_list[ARM11_RC_PC].valid = 1;
892 arm11->reg_list[ARM11_RC_PC].dirty = 0;
893 INFO("Skipping BKPT");
894 }
895 /* ignore B to self */
896 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
897 {
898 INFO("Not stepping jump to self");
899 }
900 else
901 {
902 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
903 * with this. */
904
905 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
906 * the VCR might be something worth looking into. */
907
908
909 /* Set up breakpoint for stepping */
910
911 arm11_sc7_action_t brp[2];
912
913 brp[0].write = 1;
914 brp[0].address = ARM11_SC7_BVR0;
915 brp[0].value = R(PC);
916 brp[1].write = 1;
917 brp[1].address = ARM11_SC7_BCR0;
918 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
919
920 arm11_sc7_run(arm11, brp, asizeof(brp));
921
922 /* resume */
923
924 arm11_leave_debug_state(arm11);
925
926 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
927
928 jtag_execute_queue();
929
930 /** \todo TODO: add a timeout */
931
932 /* wait for halt */
933
934 while (1)
935 {
936 u32 dscr = arm11_read_DSCR(arm11);
937
938 DEBUG("DSCR %08x", dscr);
939
940 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
941 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
942 break;
943 }
944
945 /* clear breakpoint */
946 arm11_sc7_clear_vbw(arm11);
947
948 /* save state */
949 arm11_on_enter_debug_state(arm11);
950 }
951
952 // target->state = TARGET_HALTED;
953 target->debug_reason = DBG_REASON_SINGLESTEP;
954
955 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
956
957 return ERROR_OK;
958 }
959
960
961 /* target reset control */
962 int arm11_assert_reset(struct target_s *target)
963 {
964 FNC_INFO;
965
966 #if 0
967 /* assert reset lines */
968 /* resets only the DBGTAP, not the ARM */
969
970 jtag_add_reset(1, 0);
971 jtag_add_sleep(5000);
972
973 arm11_common_t * arm11 = target->arch_info;
974 arm11->trst_active = true;
975 #endif
976
977 return ERROR_OK;
978 }
979
980 int arm11_deassert_reset(struct target_s *target)
981 {
982 FNC_INFO;
983
984 #if 0
985 DEBUG("target->state: %s", target_state_strings[target->state]);
986
987 /* deassert reset lines */
988 jtag_add_reset(0, 0);
989
990 arm11_common_t * arm11 = target->arch_info;
991 arm11->trst_active = false;
992
993 if (arm11->halt_requested)
994 return arm11_halt(target);
995 #endif
996
997 return ERROR_OK;
998 }
999
1000 int arm11_soft_reset_halt(struct target_s *target)
1001 {
1002 FNC_INFO_NOTIMPLEMENTED;
1003
1004 return ERROR_OK;
1005 }
1006
1007 int arm11_prepare_reset_halt(struct target_s *target)
1008 {
1009 FNC_INFO_NOTIMPLEMENTED;
1010
1011 return ERROR_OK;
1012 }
1013
1014
1015 /* target register access for gdb */
1016 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1017 {
1018 FNC_INFO;
1019
1020 arm11_common_t * arm11 = target->arch_info;
1021
1022 if (target->state != TARGET_HALTED)
1023 {
1024 return ERROR_TARGET_NOT_HALTED;
1025 }
1026
1027 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1028 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1029
1030 {size_t i;
1031 for (i = 16; i < 24; i++)
1032 {
1033 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1034 }}
1035
1036 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1037
1038
1039 {size_t i;
1040 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1041 {
1042 if (arm11_reg_defs[i].gdb_num == -1)
1043 continue;
1044
1045 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1046 }}
1047
1048 return ERROR_OK;
1049 }
1050
1051
1052 /* target memory access
1053 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1054 * count: number of items of <size>
1055 */
1056 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1057 {
1058 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1059
1060 FNC_INFO;
1061
1062 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1063
1064 arm11_common_t * arm11 = target->arch_info;
1065
1066 arm11_run_instr_data_prepare(arm11);
1067
1068 /* MRC p14,0,r0,c0,c5,0 */
1069 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1070
1071 switch (size)
1072 {
1073 case 1:
1074 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1075 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1076
1077 while (count--)
1078 {
1079 /* ldrb r1, [r0], #1 */
1080 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1081
1082 u32 res;
1083 /* MCR p14,0,R1,c0,c5,0 */
1084 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1085
1086 *buffer++ = res;
1087 }
1088 break;
1089
1090 case 2:
1091 {
1092 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1093
1094 u16 * buf16 = (u16*)buffer;
1095
1096 while (count--)
1097 {
1098 /* ldrh r1, [r0], #2 */
1099 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1100
1101 u32 res;
1102
1103 /* MCR p14,0,R1,c0,c5,0 */
1104 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1105
1106 *buf16++ = res;
1107 }
1108 break;
1109 }
1110
1111 case 4:
1112
1113 /* LDC p14,c5,[R0],#4 */
1114 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1115 break;
1116 }
1117
1118 arm11_run_instr_data_finish(arm11);
1119
1120 return ERROR_OK;
1121 }
1122
1123 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1124 {
1125 FNC_INFO;
1126
1127 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1128
1129 arm11_common_t * arm11 = target->arch_info;
1130
1131 arm11_run_instr_data_prepare(arm11);
1132
1133 /* MRC p14,0,r0,c0,c5,0 */
1134 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1135
1136 switch (size)
1137 {
1138 case 1:
1139 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1140
1141 while (count--)
1142 {
1143 /* MRC p14,0,r1,c0,c5,0 */
1144 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1145
1146 /* strb r1, [r0], #1 */
1147 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1148 }
1149 break;
1150
1151 case 2:
1152 {
1153 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1154
1155 u16 * buf16 = (u16*)buffer;
1156
1157 while (count--)
1158 {
1159 /* MRC p14,0,r1,c0,c5,0 */
1160 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1161
1162 /* strh r1, [r0], #2 */
1163 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1164 }
1165 break;
1166 }
1167
1168 case 4:
1169 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1170
1171 if (!arm11_config_memwrite_burst)
1172 {
1173 /* STC p14,c5,[R0],#4 */
1174 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1175 }
1176 else
1177 {
1178 /* STC p14,c5,[R0],#4 */
1179 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1180 }
1181
1182 break;
1183 }
1184
1185 #if 1
1186 /* r0 verification */
1187 {
1188 u32 r0;
1189
1190 /* MCR p14,0,R0,c0,c5,0 */
1191 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1192
1193 if (address + size * count != r0)
1194 {
1195 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1196
1197 if (arm11_config_memwrite_burst)
1198 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1199
1200 if (arm11_config_memwrite_error_fatal)
1201 exit(-1);
1202 }
1203 }
1204 #endif
1205
1206
1207 arm11_run_instr_data_finish(arm11);
1208
1209
1210
1211
1212 return ERROR_OK;
1213 }
1214
1215
1216 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1217 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1218 {
1219 FNC_INFO;
1220
1221 return arm11_write_memory(target, address, 4, count, buffer);
1222 }
1223
1224
1225 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1226 {
1227 FNC_INFO_NOTIMPLEMENTED;
1228
1229 return ERROR_OK;
1230 }
1231
1232
1233 /* target break-/watchpoint control
1234 * rw: 0 = write, 1 = read, 2 = access
1235 */
1236 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1237 {
1238 FNC_INFO;
1239
1240 arm11_common_t * arm11 = target->arch_info;
1241
1242 #if 0
1243 if (breakpoint->type == BKPT_SOFT)
1244 {
1245 INFO("sw breakpoint requested, but software breakpoints not enabled");
1246 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1247 }
1248 #endif
1249
1250 if (!arm11->free_brps)
1251 {
1252 INFO("no breakpoint unit available for hardware breakpoint");
1253 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1254 }
1255
1256 if (breakpoint->length != 4)
1257 {
1258 INFO("only breakpoints of four bytes length supported");
1259 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1260 }
1261
1262 arm11->free_brps--;
1263
1264 return ERROR_OK;
1265 }
1266
1267 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1268 {
1269 FNC_INFO;
1270
1271 arm11_common_t * arm11 = target->arch_info;
1272
1273 arm11->free_brps++;
1274
1275 return ERROR_OK;
1276 }
1277
1278 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1279 {
1280 FNC_INFO_NOTIMPLEMENTED;
1281
1282 return ERROR_OK;
1283 }
1284
1285 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1286 {
1287 FNC_INFO_NOTIMPLEMENTED;
1288
1289 return ERROR_OK;
1290 }
1291
1292
1293 /* target algorithm support */
1294 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1295 {
1296 FNC_INFO_NOTIMPLEMENTED;
1297
1298 return ERROR_OK;
1299 }
1300
1301 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1302 {
1303 FNC_INFO;
1304
1305 if (argc < 4)
1306 {
1307 ERROR("'target arm11' 4th argument <jtag chain pos>");
1308 exit(-1);
1309 }
1310
1311 int chain_pos = strtoul(args[3], NULL, 0);
1312
1313 NEW(arm11_common_t, arm11, 1);
1314
1315 arm11->target = target;
1316
1317 /* prepare JTAG information for the new target */
1318 arm11->jtag_info.chain_pos = chain_pos;
1319 arm11->jtag_info.scann_size = 5;
1320
1321 arm_jtag_setup_connection(&arm11->jtag_info);
1322
1323 jtag_device_t *device = jtag_get_device(chain_pos);
1324
1325 if (device->ir_length != 5)
1326 {
1327 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1328 exit(-1);
1329 }
1330
1331 target->arch_info = arm11;
1332
1333 return ERROR_OK;
1334 }
1335
1336 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1337 {
1338 FNC_INFO;
1339
1340 arm11_common_t * arm11 = target->arch_info;
1341
1342 /* check IDCODE */
1343
1344 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1345
1346 scan_field_t idcode_field;
1347
1348 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1349
1350 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1351
1352 /* check DIDR */
1353
1354 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1355
1356 arm11_add_IR(arm11, ARM11_INTEST, -1);
1357
1358 scan_field_t chain0_fields[2];
1359
1360 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1361 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1362
1363 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1364
1365 jtag_execute_queue();
1366
1367
1368 switch (arm11->device_id & 0x0FFFF000)
1369 {
1370 case 0x07B36000: INFO("found ARM1136"); break;
1371 case 0x07B56000: INFO("found ARM1156"); break;
1372 case 0x07B76000: INFO("found ARM1176"); break;
1373 default:
1374 {
1375 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1376 exit(-1);
1377 }
1378 }
1379
1380 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1381
1382 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1383 arm11->debug_version != ARM11_DEBUG_V61)
1384 {
1385 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1386 exit(-1);
1387 }
1388
1389
1390 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1391 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1392
1393 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1394 arm11->free_brps = arm11->brp;
1395 arm11->free_wrps = arm11->wrp;
1396
1397 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1398 arm11->device_id,
1399 arm11->implementor,
1400 arm11->didr);
1401
1402 arm11_build_reg_cache(target);
1403
1404
1405 /* as a side-effect this reads DSCR and thus
1406 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1407 * as suggested by the spec.
1408 */
1409
1410 arm11_check_init(arm11, NULL);
1411
1412 return ERROR_OK;
1413 }
1414
1415 int arm11_quit(void)
1416 {
1417 FNC_INFO_NOTIMPLEMENTED;
1418
1419 return ERROR_OK;
1420 }
1421
1422 /** Load a register that is marked !valid in the register cache */
1423 int arm11_get_reg(reg_t *reg)
1424 {
1425 FNC_INFO;
1426
1427 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1428
1429 if (target->state != TARGET_HALTED)
1430 {
1431 return ERROR_TARGET_NOT_HALTED;
1432 }
1433
1434 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1435
1436 #if 0
1437 arm11_common_t *arm11 = target->arch_info;
1438 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1439 #endif
1440
1441 return ERROR_OK;
1442 }
1443
1444 /** Change a value in the register cache */
1445 int arm11_set_reg(reg_t *reg, u8 *buf)
1446 {
1447 FNC_INFO;
1448
1449 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1450 arm11_common_t *arm11 = target->arch_info;
1451 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1452
1453 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1454 reg->valid = 1;
1455 reg->dirty = 1;
1456
1457 return ERROR_OK;
1458 }
1459
1460
1461 void arm11_build_reg_cache(target_t *target)
1462 {
1463 arm11_common_t *arm11 = target->arch_info;
1464
1465 NEW(reg_cache_t, cache, 1);
1466 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1467 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1468
1469 if (arm11_regs_arch_type == -1)
1470 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1471
1472 arm11->reg_list = reg_list;
1473
1474 /* Build the process context cache */
1475 cache->name = "arm11 registers";
1476 cache->next = NULL;
1477 cache->reg_list = reg_list;
1478 cache->num_regs = ARM11_REGCACHE_COUNT;
1479
1480 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1481 (*cache_p) = cache;
1482
1483 // armv7m->core_cache = cache;
1484 // armv7m->process_context = cache;
1485
1486 size_t i;
1487
1488 /* Not very elegant assertion */
1489 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1490 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1491 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1492 {
1493 ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1494 exit(-1);
1495 }
1496
1497 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1498 {
1499 reg_t * r = reg_list + i;
1500 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1501 arm11_reg_state_t * rs = arm11_reg_states + i;
1502
1503 r->name = rd->name;
1504 r->size = 32;
1505 r->value = (u8 *)(arm11->reg_values + i);
1506 r->dirty = 0;
1507 r->valid = 0;
1508 r->bitfield_desc = NULL;
1509 r->num_bitfields = 0;
1510 r->arch_type = arm11_regs_arch_type;
1511 r->arch_info = rs;
1512
1513 rs->def_index = i;
1514 rs->target = target;
1515 }
1516 }
1517
1518
1519
1520 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1521 {
1522 if (argc == 0)
1523 {
1524 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1525 return ERROR_OK;
1526 }
1527
1528 if (argc != 1)
1529 return ERROR_COMMAND_SYNTAX_ERROR;
1530
1531 switch (args[0][0])
1532 {
1533 case '0': /* 0 */
1534 case 'f': /* false */
1535 case 'F':
1536 case 'd': /* disable */
1537 case 'D':
1538 *var = false;
1539 break;
1540
1541 case '1': /* 1 */
1542 case 't': /* true */
1543 case 'T':
1544 case 'e': /* enable */
1545 case 'E':
1546 *var = true;
1547 break;
1548 }
1549
1550 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1551
1552 return ERROR_OK;
1553 }
1554
1555
1556 #define BOOL_WRAPPER(name, print_name) \
1557 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1558 { \
1559 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1560 }
1561
1562 #define RC_TOP(name, descr, more) \
1563 { \
1564 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1565 command_t * top_cmd = new_cmd; \
1566 more \
1567 }
1568
1569 #define RC_FINAL(name, descr, handler) \
1570 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1571
1572 #define RC_FINAL_BOOL(name, descr, var) \
1573 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1574
1575
1576 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1577 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1578
1579
1580 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1581 {
1582 if (argc == 1)
1583 {
1584 arm11_vcr = strtoul(args[0], NULL, 0);
1585 }
1586 else if (argc != 0)
1587 {
1588 return ERROR_COMMAND_SYNTAX_ERROR;
1589 }
1590
1591 INFO("VCR 0x%08X", arm11_vcr);
1592 return ERROR_OK;
1593 }
1594
1595
1596 int arm11_register_commands(struct command_context_s *cmd_ctx)
1597 {
1598 FNC_INFO;
1599
1600 command_t * top_cmd = NULL;
1601
1602 RC_TOP( "arm11", "arm11 specific commands",
1603
1604 RC_TOP( "memwrite", "Control memory write transfer mode",
1605
1606 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1607 memwrite_burst)
1608
1609 RC_FINAL_BOOL( "error_fatal",
1610 "Terminate program if transfer error was found (default: enabled)",
1611 memwrite_error_fatal)
1612 )
1613
1614 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1615 arm11_handle_vcr)
1616 )
1617
1618 return ERROR_OK;
1619 }
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