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- Work on fixing erase check. Many implementations are plain broken.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm11.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35
36 #if 0
37 #define FNC_INFO LOG_DEBUG("-")
38 #else
39 #define FNC_INFO
40 #endif
41
42 #if 1
43 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
44 #else
45 #define FNC_INFO_NOTIMPLEMENTED
46 #endif
47
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
49
50
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 u32 arm11_vcr = 0;
54
55
56 #define ARM11_HANDLER(x) \
57 .x = arm11_##x
58
59 target_type_t arm11_target =
60 {
61 .name = "arm11",
62
63 ARM11_HANDLER(poll),
64 ARM11_HANDLER(arch_state),
65
66 ARM11_HANDLER(target_request_data),
67
68 ARM11_HANDLER(halt),
69 ARM11_HANDLER(resume),
70 ARM11_HANDLER(step),
71
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75
76 ARM11_HANDLER(get_gdb_reg_list),
77
78 ARM11_HANDLER(read_memory),
79 ARM11_HANDLER(write_memory),
80
81 ARM11_HANDLER(bulk_write_memory),
82
83 ARM11_HANDLER(checksum_memory),
84
85 ARM11_HANDLER(add_breakpoint),
86 ARM11_HANDLER(remove_breakpoint),
87 ARM11_HANDLER(add_watchpoint),
88 ARM11_HANDLER(remove_watchpoint),
89
90 ARM11_HANDLER(run_algorithm),
91
92 ARM11_HANDLER(register_commands),
93 ARM11_HANDLER(target_command),
94 ARM11_HANDLER(init_target),
95 ARM11_HANDLER(quit),
96 };
97
98 int arm11_regs_arch_type = -1;
99
100
101 enum arm11_regtype
102 {
103 ARM11_REGISTER_CORE,
104 ARM11_REGISTER_CPSR,
105
106 ARM11_REGISTER_FX,
107 ARM11_REGISTER_FPS,
108
109 ARM11_REGISTER_FIQ,
110 ARM11_REGISTER_SVC,
111 ARM11_REGISTER_ABT,
112 ARM11_REGISTER_IRQ,
113 ARM11_REGISTER_UND,
114 ARM11_REGISTER_MON,
115
116 ARM11_REGISTER_SPSR_FIQ,
117 ARM11_REGISTER_SPSR_SVC,
118 ARM11_REGISTER_SPSR_ABT,
119 ARM11_REGISTER_SPSR_IRQ,
120 ARM11_REGISTER_SPSR_UND,
121 ARM11_REGISTER_SPSR_MON,
122
123 /* debug regs */
124 ARM11_REGISTER_DSCR,
125 ARM11_REGISTER_WDTR,
126 ARM11_REGISTER_RDTR,
127 };
128
129
130 typedef struct arm11_reg_defs_s
131 {
132 char * name;
133 u32 num;
134 int gdb_num;
135 enum arm11_regtype type;
136 } arm11_reg_defs_t;
137
138 /* update arm11_regcache_ids when changing this */
139 static const arm11_reg_defs_t arm11_reg_defs[] =
140 {
141 {"r0", 0, 0, ARM11_REGISTER_CORE},
142 {"r1", 1, 1, ARM11_REGISTER_CORE},
143 {"r2", 2, 2, ARM11_REGISTER_CORE},
144 {"r3", 3, 3, ARM11_REGISTER_CORE},
145 {"r4", 4, 4, ARM11_REGISTER_CORE},
146 {"r5", 5, 5, ARM11_REGISTER_CORE},
147 {"r6", 6, 6, ARM11_REGISTER_CORE},
148 {"r7", 7, 7, ARM11_REGISTER_CORE},
149 {"r8", 8, 8, ARM11_REGISTER_CORE},
150 {"r9", 9, 9, ARM11_REGISTER_CORE},
151 {"r10", 10, 10, ARM11_REGISTER_CORE},
152 {"r11", 11, 11, ARM11_REGISTER_CORE},
153 {"r12", 12, 12, ARM11_REGISTER_CORE},
154 {"sp", 13, 13, ARM11_REGISTER_CORE},
155 {"lr", 14, 14, ARM11_REGISTER_CORE},
156 {"pc", 15, 15, ARM11_REGISTER_CORE},
157
158 #if ARM11_REGCACHE_FREGS
159 {"f0", 0, 16, ARM11_REGISTER_FX},
160 {"f1", 1, 17, ARM11_REGISTER_FX},
161 {"f2", 2, 18, ARM11_REGISTER_FX},
162 {"f3", 3, 19, ARM11_REGISTER_FX},
163 {"f4", 4, 20, ARM11_REGISTER_FX},
164 {"f5", 5, 21, ARM11_REGISTER_FX},
165 {"f6", 6, 22, ARM11_REGISTER_FX},
166 {"f7", 7, 23, ARM11_REGISTER_FX},
167 {"fps", 0, 24, ARM11_REGISTER_FPS},
168 #endif
169
170 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
171
172 #if ARM11_REGCACHE_MODEREGS
173 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
174 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
175 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
176 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
177 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
178 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
179 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
180 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
181
182 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
183 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
184 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
185
186 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
187 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
188 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
189
190 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
191 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
192 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
193
194 {"r13_und", 13, -1, ARM11_REGISTER_UND},
195 {"r14_und", 14, -1, ARM11_REGISTER_UND},
196 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
197
198 /* ARM1176 only */
199 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
200 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
201 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
202 #endif
203
204 /* Debug Registers */
205 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
206 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
207 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
208 };
209
210 enum arm11_regcache_ids
211 {
212 ARM11_RC_R0,
213 ARM11_RC_RX = ARM11_RC_R0,
214
215 ARM11_RC_R1,
216 ARM11_RC_R2,
217 ARM11_RC_R3,
218 ARM11_RC_R4,
219 ARM11_RC_R5,
220 ARM11_RC_R6,
221 ARM11_RC_R7,
222 ARM11_RC_R8,
223 ARM11_RC_R9,
224 ARM11_RC_R10,
225 ARM11_RC_R11,
226 ARM11_RC_R12,
227 ARM11_RC_R13,
228 ARM11_RC_SP = ARM11_RC_R13,
229 ARM11_RC_R14,
230 ARM11_RC_LR = ARM11_RC_R14,
231 ARM11_RC_R15,
232 ARM11_RC_PC = ARM11_RC_R15,
233
234 #if ARM11_REGCACHE_FREGS
235 ARM11_RC_F0,
236 ARM11_RC_FX = ARM11_RC_F0,
237 ARM11_RC_F1,
238 ARM11_RC_F2,
239 ARM11_RC_F3,
240 ARM11_RC_F4,
241 ARM11_RC_F5,
242 ARM11_RC_F6,
243 ARM11_RC_F7,
244 ARM11_RC_FPS,
245 #endif
246
247 ARM11_RC_CPSR,
248
249 #if ARM11_REGCACHE_MODEREGS
250 ARM11_RC_R8_FIQ,
251 ARM11_RC_R9_FIQ,
252 ARM11_RC_R10_FIQ,
253 ARM11_RC_R11_FIQ,
254 ARM11_RC_R12_FIQ,
255 ARM11_RC_R13_FIQ,
256 ARM11_RC_R14_FIQ,
257 ARM11_RC_SPSR_FIQ,
258
259 ARM11_RC_R13_SVC,
260 ARM11_RC_R14_SVC,
261 ARM11_RC_SPSR_SVC,
262
263 ARM11_RC_R13_ABT,
264 ARM11_RC_R14_ABT,
265 ARM11_RC_SPSR_ABT,
266
267 ARM11_RC_R13_IRQ,
268 ARM11_RC_R14_IRQ,
269 ARM11_RC_SPSR_IRQ,
270
271 ARM11_RC_R13_UND,
272 ARM11_RC_R14_UND,
273 ARM11_RC_SPSR_UND,
274
275 ARM11_RC_R13_MON,
276 ARM11_RC_R14_MON,
277 ARM11_RC_SPSR_MON,
278 #endif
279
280 ARM11_RC_DSCR,
281 ARM11_RC_WDTR,
282 ARM11_RC_RDTR,
283
284 ARM11_RC_MAX,
285 };
286
287 #define ARM11_GDB_REGISTER_COUNT 26
288
289 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
290
291 reg_t arm11_gdb_dummy_fp_reg =
292 {
293 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
294 };
295
296 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
297
298 reg_t arm11_gdb_dummy_fps_reg =
299 {
300 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
301 };
302
303
304
305 /** Check and if necessary take control of the system
306 *
307 * \param arm11 Target state variable.
308 * \param dscr If the current DSCR content is
309 * available a pointer to a word holding the
310 * DSCR can be passed. Otherwise use NULL.
311 */
312 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
313 {
314 FNC_INFO;
315
316 u32 dscr_local_tmp_copy;
317
318 if (!dscr)
319 {
320 dscr = &dscr_local_tmp_copy;
321 *dscr = arm11_read_DSCR(arm11);
322 }
323
324 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
325 {
326 LOG_DEBUG("Bringing target into debug mode");
327
328 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
329 arm11_write_DSCR(arm11, *dscr);
330
331 /* add further reset initialization here */
332
333 arm11->simulate_reset_on_next_halt = true;
334
335 if (*dscr & ARM11_DSCR_CORE_HALTED)
336 {
337 /** \todo TODO: this needs further scrutiny because
338 * arm11_on_enter_debug_state() never gets properly called
339 */
340
341 arm11->target->state = TARGET_HALTED;
342 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
343 }
344 else
345 {
346 arm11->target->state = TARGET_RUNNING;
347 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
348 }
349
350 arm11_sc7_clear_vbw(arm11);
351 }
352 }
353
354
355
356 #define R(x) \
357 (arm11->reg_values[ARM11_RC_##x])
358
359 /** Save processor state.
360 *
361 * This is called when the HALT instruction has succeeded
362 * or on other occasions that stop the processor.
363 *
364 */
365 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
366 {
367 FNC_INFO;
368
369 {size_t i;
370 for(i = 0; i < asizeof(arm11->reg_values); i++)
371 {
372 arm11->reg_list[i].valid = 1;
373 arm11->reg_list[i].dirty = 0;
374 }}
375
376 /* Save DSCR */
377
378 R(DSCR) = arm11_read_DSCR(arm11);
379
380 /* Save wDTR */
381
382 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
383 {
384 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
385
386 arm11_add_IR(arm11, ARM11_INTEST, -1);
387
388 scan_field_t chain5_fields[3];
389
390 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
391 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
393
394 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
395 }
396 else
397 {
398 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
399 }
400
401
402 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
403 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
404 ARM1136 seems to require this to issue ITR's as well */
405
406 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
407
408 /* this executes JTAG queue: */
409
410 arm11_write_DSCR(arm11, new_dscr);
411
412
413 /* From the spec:
414 Before executing any instruction in debug state you have to drain the write buffer.
415 This ensures that no imprecise Data Aborts can return at a later point:*/
416
417 /** \todo TODO: Test drain write buffer. */
418
419 #if 0
420 while (1)
421 {
422 /* MRC p14,0,R0,c5,c10,0 */
423 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
424
425 /* mcr 15, 0, r0, cr7, cr10, {4} */
426 arm11_run_instr_no_data1(arm11, 0xee070f9a);
427
428 u32 dscr = arm11_read_DSCR(arm11);
429
430 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
431
432 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
433 {
434 arm11_run_instr_no_data1(arm11, 0xe320f000);
435
436 dscr = arm11_read_DSCR(arm11);
437
438 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
439
440 break;
441 }
442 }
443 #endif
444
445
446 arm11_run_instr_data_prepare(arm11);
447
448 /* save r0 - r14 */
449
450
451 /** \todo TODO: handle other mode registers */
452
453 {size_t i;
454 for (i = 0; i < 15; i++)
455 {
456 /* MCR p14,0,R?,c0,c5,0 */
457 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
458 }}
459
460
461 /* save rDTR */
462
463 /* check rDTRfull in DSCR */
464
465 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
466 {
467 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
468 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
469 }
470 else
471 {
472 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
473 }
474
475 /* save CPSR */
476
477 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
478 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
479
480 /* save PC */
481
482 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
484
485 /* adjust PC depending on ARM state */
486
487 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
488 {
489 arm11->reg_values[ARM11_RC_PC] -= 0;
490 }
491 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
492 {
493 arm11->reg_values[ARM11_RC_PC] -= 4;
494 }
495 else /* ARM state */
496 {
497 arm11->reg_values[ARM11_RC_PC] -= 8;
498 }
499
500 if (arm11->simulate_reset_on_next_halt)
501 {
502 arm11->simulate_reset_on_next_halt = false;
503
504 LOG_DEBUG("Reset c1 Control Register");
505
506 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
507
508 /* MCR p15,0,R0,c1,c0,0 */
509 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
510
511 }
512
513 arm11_run_instr_data_finish(arm11);
514
515 arm11_dump_reg_changes(arm11);
516 }
517
518 void arm11_dump_reg_changes(arm11_common_t * arm11)
519 {
520 {size_t i;
521 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
522 {
523 if (!arm11->reg_list[i].valid)
524 {
525 if (arm11->reg_history[i].valid)
526 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
527 }
528 else
529 {
530 if (arm11->reg_history[i].valid)
531 {
532 if (arm11->reg_history[i].value != arm11->reg_values[i])
533 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
534 }
535 else
536 {
537 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
538 }
539 }
540 }}
541 }
542
543
544 /** Restore processor state
545 *
546 * This is called in preparation for the RESTART function.
547 *
548 */
549 void arm11_leave_debug_state(arm11_common_t * arm11)
550 {
551 FNC_INFO;
552
553 arm11_run_instr_data_prepare(arm11);
554
555 /** \todo TODO: handle other mode registers */
556
557 /* restore R1 - R14 */
558 {size_t i;
559 for (i = 1; i < 15; i++)
560 {
561 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
562 continue;
563
564 /* MRC p14,0,r?,c0,c5,0 */
565 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
566
567 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
568 }}
569
570 arm11_run_instr_data_finish(arm11);
571
572
573 /* spec says clear wDTR and rDTR; we assume they are clear as
574 otherwise our programming would be sloppy */
575
576 {
577 u32 DSCR = arm11_read_DSCR(arm11);
578
579 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
580 {
581 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
582 }
583 }
584
585 arm11_run_instr_data_prepare(arm11);
586
587 /* restore original wDTR */
588
589 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
590 {
591 /* MCR p14,0,R0,c0,c5,0 */
592 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
593 }
594
595 /* restore CPSR */
596
597 /* MSR CPSR,R0*/
598 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
599
600
601 /* restore PC */
602
603 /* MOV PC,R0 */
604 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
605
606
607 /* restore R0 */
608
609 /* MRC p14,0,r0,c0,c5,0 */
610 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
611
612 arm11_run_instr_data_finish(arm11);
613
614
615 /* restore DSCR */
616
617 arm11_write_DSCR(arm11, R(DSCR));
618
619
620 /* restore rDTR */
621
622 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
623 {
624 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
625
626 arm11_add_IR(arm11, ARM11_EXTEST, -1);
627
628 scan_field_t chain5_fields[3];
629
630 u8 Ready = 0; /* ignored */
631 u8 Valid = 0; /* ignored */
632
633 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
634 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
635 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
636
637 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
638 }
639
640 arm11_record_register_history(arm11);
641 }
642
643 void arm11_record_register_history(arm11_common_t * arm11)
644 {
645 {size_t i;
646 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
647 {
648 arm11->reg_history[i].value = arm11->reg_values[i];
649 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
650
651 arm11->reg_list[i].valid = 0;
652 arm11->reg_list[i].dirty = 0;
653 }}
654 }
655
656
657 /* poll current target status */
658 int arm11_poll(struct target_s *target)
659 {
660 FNC_INFO;
661
662 arm11_common_t * arm11 = target->arch_info;
663
664 if (arm11->trst_active)
665 return ERROR_OK;
666
667 u32 dscr = arm11_read_DSCR(arm11);
668
669 LOG_DEBUG("DSCR %08x", dscr);
670
671 arm11_check_init(arm11, &dscr);
672
673 if (dscr & ARM11_DSCR_CORE_HALTED)
674 {
675 if (target->state != TARGET_HALTED)
676 {
677 enum target_state old_state = target->state;
678
679 LOG_DEBUG("enter TARGET_HALTED");
680 target->state = TARGET_HALTED;
681 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
682 arm11_on_enter_debug_state(arm11);
683
684 target_call_event_callbacks(target,
685 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
686 }
687 }
688 else
689 {
690 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
691 {
692 LOG_DEBUG("enter TARGET_RUNNING");
693 target->state = TARGET_RUNNING;
694 target->debug_reason = DBG_REASON_NOTHALTED;
695 }
696 }
697
698 return ERROR_OK;
699 }
700 /* architecture specific status reply */
701 int arm11_arch_state(struct target_s *target)
702 {
703 FNC_INFO_NOTIMPLEMENTED;
704
705 return ERROR_OK;
706 }
707
708
709 /* target request support */
710 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
711 {
712 FNC_INFO_NOTIMPLEMENTED;
713
714 return ERROR_OK;
715 }
716
717
718
719 /* target execution control */
720 int arm11_halt(struct target_s *target)
721 {
722 FNC_INFO;
723
724 arm11_common_t * arm11 = target->arch_info;
725
726 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
727
728 if (target->state == TARGET_UNKNOWN)
729 {
730 arm11->simulate_reset_on_next_halt = true;
731 }
732
733 if (target->state == TARGET_HALTED)
734 {
735 LOG_WARNING("target was already halted");
736 return ERROR_OK;
737 }
738
739 if (arm11->trst_active)
740 {
741 arm11->halt_requested = true;
742 return ERROR_OK;
743 }
744
745 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
746
747 jtag_execute_queue();
748
749 u32 dscr;
750
751 while (1)
752 {
753 dscr = arm11_read_DSCR(arm11);
754
755 if (dscr & ARM11_DSCR_CORE_HALTED)
756 break;
757 }
758
759 arm11_on_enter_debug_state(arm11);
760
761 enum target_state old_state = target->state;
762
763 target->state = TARGET_HALTED;
764 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
765
766 target_call_event_callbacks(target,
767 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
768
769 return ERROR_OK;
770 }
771
772
773 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
774 {
775 FNC_INFO;
776
777 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
778 // current, address, handle_breakpoints, debug_execution);
779
780 arm11_common_t * arm11 = target->arch_info;
781
782 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
783
784 if (target->state != TARGET_HALTED)
785 {
786 LOG_WARNING("target was not halted");
787 return ERROR_TARGET_NOT_HALTED;
788 }
789
790 if (!current)
791 R(PC) = address;
792
793 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
794
795 /* clear breakpoints/watchpoints and VCR*/
796 arm11_sc7_clear_vbw(arm11);
797
798 /* Set up breakpoints */
799 if (!debug_execution)
800 {
801 /* check if one matches PC and step over it if necessary */
802
803 breakpoint_t * bp;
804
805 for (bp = target->breakpoints; bp; bp = bp->next)
806 {
807 if (bp->address == R(PC))
808 {
809 LOG_DEBUG("must step over %08x", bp->address);
810 arm11_step(target, 1, 0, 0);
811 break;
812 }
813 }
814
815 /* set all breakpoints */
816
817 size_t brp_num = 0;
818
819 for (bp = target->breakpoints; bp; bp = bp->next)
820 {
821 arm11_sc7_action_t brp[2];
822
823 brp[0].write = 1;
824 brp[0].address = ARM11_SC7_BVR0 + brp_num;
825 brp[0].value = bp->address;
826 brp[1].write = 1;
827 brp[1].address = ARM11_SC7_BCR0 + brp_num;
828 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
829
830 arm11_sc7_run(arm11, brp, asizeof(brp));
831
832 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
833
834 brp_num++;
835 }
836
837 arm11_sc7_set_vcr(arm11, arm11_vcr);
838 }
839
840
841 arm11_leave_debug_state(arm11);
842
843 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
844
845 jtag_execute_queue();
846
847 while (1)
848 {
849 u32 dscr = arm11_read_DSCR(arm11);
850
851 LOG_DEBUG("DSCR %08x", dscr);
852
853 if (dscr & ARM11_DSCR_CORE_RESTARTED)
854 break;
855 }
856
857 if (!debug_execution)
858 {
859 target->state = TARGET_RUNNING;
860 target->debug_reason = DBG_REASON_NOTHALTED;
861 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
862 }
863 else
864 {
865 target->state = TARGET_DEBUG_RUNNING;
866 target->debug_reason = DBG_REASON_NOTHALTED;
867 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
868 }
869
870 return ERROR_OK;
871 }
872
873 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
874 {
875 FNC_INFO;
876
877 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
878
879 if (target->state != TARGET_HALTED)
880 {
881 LOG_WARNING("target was not halted");
882 return ERROR_TARGET_NOT_HALTED;
883 }
884
885 arm11_common_t * arm11 = target->arch_info;
886
887 if (!current)
888 R(PC) = address;
889
890 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
891
892 /** \todo TODO: Thumb not supported here */
893
894 u32 next_instruction;
895
896 arm11_read_memory_word(arm11, R(PC), &next_instruction);
897
898 /* skip over BKPT */
899 if ((next_instruction & 0xFFF00070) == 0xe1200070)
900 {
901 R(PC) += 4;
902 arm11->reg_list[ARM11_RC_PC].valid = 1;
903 arm11->reg_list[ARM11_RC_PC].dirty = 0;
904 LOG_INFO("Skipping BKPT");
905 }
906 /* skip over Wait for interrupt / Standby */
907 /* mcr 15, 0, r?, cr7, cr0, {4} */
908 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
909 {
910 R(PC) += 4;
911 arm11->reg_list[ARM11_RC_PC].valid = 1;
912 arm11->reg_list[ARM11_RC_PC].dirty = 0;
913 LOG_INFO("Skipping WFI");
914 }
915 /* ignore B to self */
916 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
917 {
918 LOG_INFO("Not stepping jump to self");
919 }
920 else
921 {
922 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
923 * with this. */
924
925 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
926 * the VCR might be something worth looking into. */
927
928
929 /* Set up breakpoint for stepping */
930
931 arm11_sc7_action_t brp[2];
932
933 brp[0].write = 1;
934 brp[0].address = ARM11_SC7_BVR0;
935 brp[0].value = R(PC);
936 brp[1].write = 1;
937 brp[1].address = ARM11_SC7_BCR0;
938 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
939
940 arm11_sc7_run(arm11, brp, asizeof(brp));
941
942 /* resume */
943
944 arm11_leave_debug_state(arm11);
945
946 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
947
948 jtag_execute_queue();
949
950 /** \todo TODO: add a timeout */
951
952 /* wait for halt */
953
954 while (1)
955 {
956 u32 dscr = arm11_read_DSCR(arm11);
957
958 LOG_DEBUG("DSCR %08x", dscr);
959
960 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
961 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
962 break;
963 }
964
965 /* clear breakpoint */
966 arm11_sc7_clear_vbw(arm11);
967
968 /* save state */
969 arm11_on_enter_debug_state(arm11);
970 }
971
972 // target->state = TARGET_HALTED;
973 target->debug_reason = DBG_REASON_SINGLESTEP;
974
975 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
976
977 return ERROR_OK;
978 }
979
980
981 /* target reset control */
982 int arm11_assert_reset(struct target_s *target)
983 {
984 FNC_INFO;
985
986 #if 0
987 /* assert reset lines */
988 /* resets only the DBGTAP, not the ARM */
989
990 jtag_add_reset(1, 0);
991 jtag_add_sleep(5000);
992
993 arm11_common_t * arm11 = target->arch_info;
994 arm11->trst_active = true;
995 #endif
996
997 return ERROR_OK;
998 }
999
1000 int arm11_deassert_reset(struct target_s *target)
1001 {
1002 FNC_INFO;
1003
1004 #if 0
1005 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1006
1007 /* deassert reset lines */
1008 jtag_add_reset(0, 0);
1009
1010 arm11_common_t * arm11 = target->arch_info;
1011 arm11->trst_active = false;
1012
1013 if (arm11->halt_requested)
1014 return arm11_halt(target);
1015 #endif
1016
1017 return ERROR_OK;
1018 }
1019
1020 int arm11_soft_reset_halt(struct target_s *target)
1021 {
1022 FNC_INFO_NOTIMPLEMENTED;
1023
1024 return ERROR_OK;
1025 }
1026
1027
1028
1029 /* target register access for gdb */
1030 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1031 {
1032 FNC_INFO;
1033
1034 arm11_common_t * arm11 = target->arch_info;
1035
1036 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1037 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1038
1039 {size_t i;
1040 for (i = 16; i < 24; i++)
1041 {
1042 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1043 }}
1044
1045 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1046
1047
1048 {size_t i;
1049 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1050 {
1051 if (arm11_reg_defs[i].gdb_num == -1)
1052 continue;
1053
1054 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1055 }}
1056
1057 return ERROR_OK;
1058 }
1059
1060
1061 /* target memory access
1062 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1063 * count: number of items of <size>
1064 */
1065 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1066 {
1067 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1068
1069 FNC_INFO;
1070
1071 if (target->state != TARGET_HALTED)
1072 {
1073 LOG_WARNING("target was not halted");
1074 return ERROR_TARGET_NOT_HALTED;
1075 }
1076
1077 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1078
1079 arm11_common_t * arm11 = target->arch_info;
1080
1081 arm11_run_instr_data_prepare(arm11);
1082
1083 /* MRC p14,0,r0,c0,c5,0 */
1084 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1085
1086 switch (size)
1087 {
1088 case 1:
1089 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1090 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1091
1092 {size_t i;
1093 for (i = 0; i < count; i++)
1094 {
1095 /* ldrb r1, [r0], #1 */
1096 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1097
1098 u32 res;
1099 /* MCR p14,0,R1,c0,c5,0 */
1100 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1101
1102 *buffer++ = res;
1103 }}
1104
1105 break;
1106
1107 case 2:
1108 {
1109 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1110
1111 u16 * buf16 = (u16*)buffer;
1112
1113 {size_t i;
1114 for (i = 0; i < count; i++)
1115 {
1116 /* ldrh r1, [r0], #2 */
1117 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1118
1119 u32 res;
1120
1121 /* MCR p14,0,R1,c0,c5,0 */
1122 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1123
1124 *buf16++ = res;
1125 }}
1126
1127 break;
1128 }
1129
1130 case 4:
1131
1132 /* LDC p14,c5,[R0],#4 */
1133 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1134 break;
1135 }
1136
1137 arm11_run_instr_data_finish(arm11);
1138
1139 return ERROR_OK;
1140 }
1141
1142 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1143 {
1144 FNC_INFO;
1145
1146 if (target->state != TARGET_HALTED)
1147 {
1148 LOG_WARNING("target was not halted");
1149 return ERROR_TARGET_NOT_HALTED;
1150 }
1151
1152 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1153
1154 arm11_common_t * arm11 = target->arch_info;
1155
1156 arm11_run_instr_data_prepare(arm11);
1157
1158 /* MRC p14,0,r0,c0,c5,0 */
1159 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1160
1161 switch (size)
1162 {
1163 case 1:
1164 {
1165 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1166
1167 {size_t i;
1168 for (i = 0; i < count; i++)
1169 {
1170 /* MRC p14,0,r1,c0,c5,0 */
1171 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1172
1173 /* strb r1, [r0], #1 */
1174 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1175 }}
1176
1177 break;
1178 }
1179
1180 case 2:
1181 {
1182 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1183
1184 u16 * buf16 = (u16*)buffer;
1185
1186 {size_t i;
1187 for (i = 0; i < count; i++)
1188 {
1189 /* MRC p14,0,r1,c0,c5,0 */
1190 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1191
1192 /* strh r1, [r0], #2 */
1193 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1194 }}
1195
1196 break;
1197 }
1198
1199 case 4:
1200 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1201
1202 if (!arm11_config_memwrite_burst)
1203 {
1204 /* STC p14,c5,[R0],#4 */
1205 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1206 }
1207 else
1208 {
1209 /* STC p14,c5,[R0],#4 */
1210 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1211 }
1212
1213 break;
1214 }
1215
1216 #if 1
1217 /* r0 verification */
1218 {
1219 u32 r0;
1220
1221 /* MCR p14,0,R0,c0,c5,0 */
1222 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1223
1224 if (address + size * count != r0)
1225 {
1226 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1227
1228 if (arm11_config_memwrite_burst)
1229 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1230
1231 if (arm11_config_memwrite_error_fatal)
1232 exit(-1);
1233 }
1234 }
1235 #endif
1236
1237
1238 arm11_run_instr_data_finish(arm11);
1239
1240
1241
1242
1243 return ERROR_OK;
1244 }
1245
1246
1247 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1248 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1249 {
1250 FNC_INFO;
1251
1252 if (target->state != TARGET_HALTED)
1253 {
1254 LOG_WARNING("target was not halted");
1255 return ERROR_TARGET_NOT_HALTED;
1256 }
1257
1258 return arm11_write_memory(target, address, 4, count, buffer);
1259 }
1260
1261
1262 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1263 {
1264 FNC_INFO_NOTIMPLEMENTED;
1265
1266 return ERROR_OK;
1267 }
1268
1269
1270 /* target break-/watchpoint control
1271 * rw: 0 = write, 1 = read, 2 = access
1272 */
1273 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1274 {
1275 FNC_INFO;
1276
1277 arm11_common_t * arm11 = target->arch_info;
1278
1279 #if 0
1280 if (breakpoint->type == BKPT_SOFT)
1281 {
1282 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284 }
1285 #endif
1286
1287 if (!arm11->free_brps)
1288 {
1289 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1290 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1291 }
1292
1293 if (breakpoint->length != 4)
1294 {
1295 LOG_INFO("only breakpoints of four bytes length supported");
1296 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1297 }
1298
1299 arm11->free_brps--;
1300
1301 return ERROR_OK;
1302 }
1303
1304 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1305 {
1306 FNC_INFO;
1307
1308 arm11_common_t * arm11 = target->arch_info;
1309
1310 arm11->free_brps++;
1311
1312 return ERROR_OK;
1313 }
1314
1315 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1316 {
1317 FNC_INFO_NOTIMPLEMENTED;
1318
1319 return ERROR_OK;
1320 }
1321
1322 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1323 {
1324 FNC_INFO_NOTIMPLEMENTED;
1325
1326 return ERROR_OK;
1327 }
1328
1329
1330 /* target algorithm support */
1331 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1332 {
1333 FNC_INFO_NOTIMPLEMENTED;
1334
1335 return ERROR_OK;
1336 }
1337
1338 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1339 {
1340 FNC_INFO;
1341
1342 if (argc < 4)
1343 {
1344 LOG_ERROR("'target arm11' 4th argument <jtag chain pos>");
1345 exit(-1);
1346 }
1347
1348 int chain_pos = strtoul(args[3], NULL, 0);
1349
1350 NEW(arm11_common_t, arm11, 1);
1351
1352 arm11->target = target;
1353
1354 /* prepare JTAG information for the new target */
1355 arm11->jtag_info.chain_pos = chain_pos;
1356 arm11->jtag_info.scann_size = 5;
1357
1358 arm_jtag_setup_connection(&arm11->jtag_info);
1359
1360 jtag_device_t *device = jtag_get_device(chain_pos);
1361
1362 if (device->ir_length != 5)
1363 {
1364 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1365 exit(-1);
1366 }
1367
1368 target->arch_info = arm11;
1369
1370 return ERROR_OK;
1371 }
1372
1373 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1374 {
1375 FNC_INFO;
1376
1377 arm11_common_t * arm11 = target->arch_info;
1378
1379 /* check IDCODE */
1380
1381 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1382
1383 scan_field_t idcode_field;
1384
1385 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1386
1387 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1388
1389 /* check DIDR */
1390
1391 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1392
1393 arm11_add_IR(arm11, ARM11_INTEST, -1);
1394
1395 scan_field_t chain0_fields[2];
1396
1397 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1398 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1399
1400 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1401
1402 jtag_execute_queue();
1403
1404
1405 switch (arm11->device_id & 0x0FFFF000)
1406 {
1407 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1408 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1409 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1410 default:
1411 {
1412 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1413 exit(-1);
1414 }
1415 }
1416
1417 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1418
1419 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1420 arm11->debug_version != ARM11_DEBUG_V61)
1421 {
1422 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1423 exit(-1);
1424 }
1425
1426
1427 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1428 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1429
1430 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1431 arm11->free_brps = arm11->brp;
1432 arm11->free_wrps = arm11->wrp;
1433
1434 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1435 arm11->device_id,
1436 arm11->implementor,
1437 arm11->didr);
1438
1439 arm11_build_reg_cache(target);
1440
1441
1442 /* as a side-effect this reads DSCR and thus
1443 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1444 * as suggested by the spec.
1445 */
1446
1447 arm11_check_init(arm11, NULL);
1448
1449 return ERROR_OK;
1450 }
1451
1452 int arm11_quit(void)
1453 {
1454 FNC_INFO_NOTIMPLEMENTED;
1455
1456 return ERROR_OK;
1457 }
1458
1459 /** Load a register that is marked !valid in the register cache */
1460 int arm11_get_reg(reg_t *reg)
1461 {
1462 FNC_INFO;
1463
1464 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1465
1466 if (target->state != TARGET_HALTED)
1467 {
1468 LOG_WARNING("target was not halted");
1469 return ERROR_TARGET_NOT_HALTED;
1470 }
1471
1472 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1473
1474 #if 0
1475 arm11_common_t *arm11 = target->arch_info;
1476 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1477 #endif
1478
1479 return ERROR_OK;
1480 }
1481
1482 /** Change a value in the register cache */
1483 int arm11_set_reg(reg_t *reg, u8 *buf)
1484 {
1485 FNC_INFO;
1486
1487 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1488 arm11_common_t *arm11 = target->arch_info;
1489 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1490
1491 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1492 reg->valid = 1;
1493 reg->dirty = 1;
1494
1495 return ERROR_OK;
1496 }
1497
1498
1499 void arm11_build_reg_cache(target_t *target)
1500 {
1501 arm11_common_t *arm11 = target->arch_info;
1502
1503 NEW(reg_cache_t, cache, 1);
1504 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1505 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1506
1507 if (arm11_regs_arch_type == -1)
1508 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1509
1510 arm11->reg_list = reg_list;
1511
1512 /* Build the process context cache */
1513 cache->name = "arm11 registers";
1514 cache->next = NULL;
1515 cache->reg_list = reg_list;
1516 cache->num_regs = ARM11_REGCACHE_COUNT;
1517
1518 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1519 (*cache_p) = cache;
1520
1521 // armv7m->core_cache = cache;
1522 // armv7m->process_context = cache;
1523
1524 size_t i;
1525
1526 /* Not very elegant assertion */
1527 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1528 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1529 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1530 {
1531 LOG_ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1532 exit(-1);
1533 }
1534
1535 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1536 {
1537 reg_t * r = reg_list + i;
1538 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1539 arm11_reg_state_t * rs = arm11_reg_states + i;
1540
1541 r->name = rd->name;
1542 r->size = 32;
1543 r->value = (u8 *)(arm11->reg_values + i);
1544 r->dirty = 0;
1545 r->valid = 0;
1546 r->bitfield_desc = NULL;
1547 r->num_bitfields = 0;
1548 r->arch_type = arm11_regs_arch_type;
1549 r->arch_info = rs;
1550
1551 rs->def_index = i;
1552 rs->target = target;
1553 }
1554 }
1555
1556
1557
1558 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1559 {
1560 if (argc == 0)
1561 {
1562 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1563 return ERROR_OK;
1564 }
1565
1566 if (argc != 1)
1567 return ERROR_COMMAND_SYNTAX_ERROR;
1568
1569 switch (args[0][0])
1570 {
1571 case '0': /* 0 */
1572 case 'f': /* false */
1573 case 'F':
1574 case 'd': /* disable */
1575 case 'D':
1576 *var = false;
1577 break;
1578
1579 case '1': /* 1 */
1580 case 't': /* true */
1581 case 'T':
1582 case 'e': /* enable */
1583 case 'E':
1584 *var = true;
1585 break;
1586 }
1587
1588 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1589
1590 return ERROR_OK;
1591 }
1592
1593
1594 #define BOOL_WRAPPER(name, print_name) \
1595 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1596 { \
1597 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1598 }
1599
1600 #define RC_TOP(name, descr, more) \
1601 { \
1602 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1603 command_t * top_cmd = new_cmd; \
1604 more \
1605 }
1606
1607 #define RC_FINAL(name, descr, handler) \
1608 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1609
1610 #define RC_FINAL_BOOL(name, descr, var) \
1611 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1612
1613
1614 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1615 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1616
1617
1618 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1619 {
1620 if (argc == 1)
1621 {
1622 arm11_vcr = strtoul(args[0], NULL, 0);
1623 }
1624 else if (argc != 0)
1625 {
1626 return ERROR_COMMAND_SYNTAX_ERROR;
1627 }
1628
1629 LOG_INFO("VCR 0x%08X", arm11_vcr);
1630 return ERROR_OK;
1631 }
1632
1633 const u32 arm11_coproc_instruction_limits[] =
1634 {
1635 15, /* coprocessor */
1636 7, /* opcode 1 */
1637 15, /* CRn */
1638 15, /* CRm */
1639 7, /* opcode 2 */
1640 0xFFFFFFFF, /* value */
1641 };
1642
1643 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1644 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1645
1646
1647 arm11_common_t * arm11_find_target(const char * arg)
1648 {
1649 size_t jtag_target = strtoul(arg, NULL, 0);
1650
1651 {target_t * t;
1652 for (t = targets; t; t = t->next)
1653 {
1654 if (t->type != &arm11_target)
1655 continue;
1656
1657 arm11_common_t * arm11 = t->arch_info;
1658
1659 if (arm11->jtag_info.chain_pos != jtag_target)
1660 continue;
1661
1662 return arm11;
1663 }}
1664
1665 return 0;
1666 }
1667
1668 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1669 {
1670 if (argc != (read ? 6 : 7))
1671 {
1672 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1673 return -1;
1674 }
1675
1676 arm11_common_t * arm11 = arm11_find_target(args[0]);
1677
1678 if (!arm11)
1679 {
1680 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1681 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1682
1683 return -1;
1684
1685 }
1686
1687 if (arm11->target->state != TARGET_HALTED)
1688 {
1689 LOG_WARNING("target was not halted");
1690 return ERROR_TARGET_NOT_HALTED;
1691 }
1692
1693
1694 u32 values[6];
1695
1696 {size_t i;
1697 for (i = 0; i < (read ? 5 : 6); i++)
1698 {
1699 values[i] = strtoul(args[i + 1], NULL, 0);
1700
1701 if (values[i] > arm11_coproc_instruction_limits[i])
1702 {
1703 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1704 i + 2, arm11_coproc_instruction_limits[i],
1705 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1706 return -1;
1707 }
1708 }}
1709
1710 u32 instr = 0xEE000010 |
1711 (values[0] << 8) |
1712 (values[1] << 21) |
1713 (values[2] << 16) |
1714 (values[3] << 0) |
1715 (values[4] << 5);
1716
1717 if (read)
1718 instr |= 0x00100000;
1719
1720
1721 arm11_run_instr_data_prepare(arm11);
1722
1723 if (read)
1724 {
1725 u32 result;
1726 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1727
1728 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1729 values[0], values[1], values[2], values[3], values[4], result, result);
1730 }
1731 else
1732 {
1733 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1734
1735 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1736 values[0], values[1],
1737 values[5],
1738 values[2], values[3], values[4]);
1739 }
1740
1741 arm11_run_instr_data_finish(arm11);
1742
1743
1744 return ERROR_OK;
1745 }
1746
1747 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1748 {
1749 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1750 }
1751
1752 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1753 {
1754 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1755 }
1756
1757 int arm11_register_commands(struct command_context_s *cmd_ctx)
1758 {
1759 FNC_INFO;
1760
1761 command_t * top_cmd = NULL;
1762
1763 RC_TOP( "arm11", "arm11 specific commands",
1764
1765 RC_TOP( "memwrite", "Control memory write transfer mode",
1766
1767 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1768 memwrite_burst)
1769
1770 RC_FINAL_BOOL( "error_fatal",
1771 "Terminate program if transfer error was found (default: enabled)",
1772 memwrite_error_fatal)
1773 )
1774
1775 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1776 arm11_handle_vcr)
1777
1778 RC_FINAL( "mrc", "Read Coprocessor register",
1779 arm11_handle_mrc)
1780
1781 RC_FINAL( "mcr", "Write Coprocessor register",
1782 arm11_handle_mcr)
1783 )
1784
1785 return ERROR_OK;
1786 }
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