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[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "target_type.h"
31
32
33 #if 0
34 #define _DEBUG_INSTRUCTION_EXECUTION_
35 #endif
36
37 #if 0
38 #define FNC_INFO LOG_DEBUG("-")
39 #else
40 #define FNC_INFO
41 #endif
42
43 #if 1
44 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
45 #else
46 #define FNC_INFO_NOTIMPLEMENTED
47 #endif
48
49 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
50
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 uint32_t arm11_vcr = 0;
54 bool arm11_config_memrw_no_increment = false;
55 bool arm11_config_step_irq_enable = false;
56
57 #define ARM11_HANDLER(x) \
58 .x = arm11_##x
59
60 target_type_t arm11_target =
61 {
62 .name = "arm11",
63
64 ARM11_HANDLER(poll),
65 ARM11_HANDLER(arch_state),
66
67 ARM11_HANDLER(target_request_data),
68
69 ARM11_HANDLER(halt),
70 ARM11_HANDLER(resume),
71 ARM11_HANDLER(step),
72
73 ARM11_HANDLER(assert_reset),
74 ARM11_HANDLER(deassert_reset),
75 ARM11_HANDLER(soft_reset_halt),
76
77 ARM11_HANDLER(get_gdb_reg_list),
78
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
81
82 ARM11_HANDLER(bulk_write_memory),
83
84 ARM11_HANDLER(checksum_memory),
85
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
90
91 ARM11_HANDLER(run_algorithm),
92
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_create),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(examine),
97 ARM11_HANDLER(quit),
98 };
99
100 int arm11_regs_arch_type = -1;
101
102
103 enum arm11_regtype
104 {
105 ARM11_REGISTER_CORE,
106 ARM11_REGISTER_CPSR,
107
108 ARM11_REGISTER_FX,
109 ARM11_REGISTER_FPS,
110
111 ARM11_REGISTER_FIQ,
112 ARM11_REGISTER_SVC,
113 ARM11_REGISTER_ABT,
114 ARM11_REGISTER_IRQ,
115 ARM11_REGISTER_UND,
116 ARM11_REGISTER_MON,
117
118 ARM11_REGISTER_SPSR_FIQ,
119 ARM11_REGISTER_SPSR_SVC,
120 ARM11_REGISTER_SPSR_ABT,
121 ARM11_REGISTER_SPSR_IRQ,
122 ARM11_REGISTER_SPSR_UND,
123 ARM11_REGISTER_SPSR_MON,
124
125 /* debug regs */
126 ARM11_REGISTER_DSCR,
127 ARM11_REGISTER_WDTR,
128 ARM11_REGISTER_RDTR,
129 };
130
131
132 typedef struct arm11_reg_defs_s
133 {
134 char * name;
135 uint32_t num;
136 int gdb_num;
137 enum arm11_regtype type;
138 } arm11_reg_defs_t;
139
140 /* update arm11_regcache_ids when changing this */
141 static const arm11_reg_defs_t arm11_reg_defs[] =
142 {
143 {"r0", 0, 0, ARM11_REGISTER_CORE},
144 {"r1", 1, 1, ARM11_REGISTER_CORE},
145 {"r2", 2, 2, ARM11_REGISTER_CORE},
146 {"r3", 3, 3, ARM11_REGISTER_CORE},
147 {"r4", 4, 4, ARM11_REGISTER_CORE},
148 {"r5", 5, 5, ARM11_REGISTER_CORE},
149 {"r6", 6, 6, ARM11_REGISTER_CORE},
150 {"r7", 7, 7, ARM11_REGISTER_CORE},
151 {"r8", 8, 8, ARM11_REGISTER_CORE},
152 {"r9", 9, 9, ARM11_REGISTER_CORE},
153 {"r10", 10, 10, ARM11_REGISTER_CORE},
154 {"r11", 11, 11, ARM11_REGISTER_CORE},
155 {"r12", 12, 12, ARM11_REGISTER_CORE},
156 {"sp", 13, 13, ARM11_REGISTER_CORE},
157 {"lr", 14, 14, ARM11_REGISTER_CORE},
158 {"pc", 15, 15, ARM11_REGISTER_CORE},
159
160 #if ARM11_REGCACHE_FREGS
161 {"f0", 0, 16, ARM11_REGISTER_FX},
162 {"f1", 1, 17, ARM11_REGISTER_FX},
163 {"f2", 2, 18, ARM11_REGISTER_FX},
164 {"f3", 3, 19, ARM11_REGISTER_FX},
165 {"f4", 4, 20, ARM11_REGISTER_FX},
166 {"f5", 5, 21, ARM11_REGISTER_FX},
167 {"f6", 6, 22, ARM11_REGISTER_FX},
168 {"f7", 7, 23, ARM11_REGISTER_FX},
169 {"fps", 0, 24, ARM11_REGISTER_FPS},
170 #endif
171
172 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
173
174 #if ARM11_REGCACHE_MODEREGS
175 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
176 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
177 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
178 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
179 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
180 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
181 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
182 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
183
184 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
185 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
186 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
187
188 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
189 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
190 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
191
192 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
193 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
194 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
195
196 {"r13_und", 13, -1, ARM11_REGISTER_UND},
197 {"r14_und", 14, -1, ARM11_REGISTER_UND},
198 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
199
200 /* ARM1176 only */
201 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
202 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
203 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
204 #endif
205
206 /* Debug Registers */
207 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
208 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
209 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
210 };
211
212 enum arm11_regcache_ids
213 {
214 ARM11_RC_R0,
215 ARM11_RC_RX = ARM11_RC_R0,
216
217 ARM11_RC_R1,
218 ARM11_RC_R2,
219 ARM11_RC_R3,
220 ARM11_RC_R4,
221 ARM11_RC_R5,
222 ARM11_RC_R6,
223 ARM11_RC_R7,
224 ARM11_RC_R8,
225 ARM11_RC_R9,
226 ARM11_RC_R10,
227 ARM11_RC_R11,
228 ARM11_RC_R12,
229 ARM11_RC_R13,
230 ARM11_RC_SP = ARM11_RC_R13,
231 ARM11_RC_R14,
232 ARM11_RC_LR = ARM11_RC_R14,
233 ARM11_RC_R15,
234 ARM11_RC_PC = ARM11_RC_R15,
235
236 #if ARM11_REGCACHE_FREGS
237 ARM11_RC_F0,
238 ARM11_RC_FX = ARM11_RC_F0,
239 ARM11_RC_F1,
240 ARM11_RC_F2,
241 ARM11_RC_F3,
242 ARM11_RC_F4,
243 ARM11_RC_F5,
244 ARM11_RC_F6,
245 ARM11_RC_F7,
246 ARM11_RC_FPS,
247 #endif
248
249 ARM11_RC_CPSR,
250
251 #if ARM11_REGCACHE_MODEREGS
252 ARM11_RC_R8_FIQ,
253 ARM11_RC_R9_FIQ,
254 ARM11_RC_R10_FIQ,
255 ARM11_RC_R11_FIQ,
256 ARM11_RC_R12_FIQ,
257 ARM11_RC_R13_FIQ,
258 ARM11_RC_R14_FIQ,
259 ARM11_RC_SPSR_FIQ,
260
261 ARM11_RC_R13_SVC,
262 ARM11_RC_R14_SVC,
263 ARM11_RC_SPSR_SVC,
264
265 ARM11_RC_R13_ABT,
266 ARM11_RC_R14_ABT,
267 ARM11_RC_SPSR_ABT,
268
269 ARM11_RC_R13_IRQ,
270 ARM11_RC_R14_IRQ,
271 ARM11_RC_SPSR_IRQ,
272
273 ARM11_RC_R13_UND,
274 ARM11_RC_R14_UND,
275 ARM11_RC_SPSR_UND,
276
277 ARM11_RC_R13_MON,
278 ARM11_RC_R14_MON,
279 ARM11_RC_SPSR_MON,
280 #endif
281
282 ARM11_RC_DSCR,
283 ARM11_RC_WDTR,
284 ARM11_RC_RDTR,
285
286 ARM11_RC_MAX,
287 };
288
289 #define ARM11_GDB_REGISTER_COUNT 26
290
291 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292
293 reg_t arm11_gdb_dummy_fp_reg =
294 {
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
296 };
297
298 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299
300 reg_t arm11_gdb_dummy_fps_reg =
301 {
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
303 };
304
305
306
307 /** Check and if necessary take control of the system
308 *
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
313 */
314 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
315 {
316 FNC_INFO;
317
318 uint32_t dscr_local_tmp_copy;
319
320 if (!dscr)
321 {
322 dscr = &dscr_local_tmp_copy;
323
324 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
325 }
326
327 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
328 {
329 LOG_DEBUG("Bringing target into debug mode");
330
331 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
332 arm11_write_DSCR(arm11, *dscr);
333
334 /* add further reset initialization here */
335
336 arm11->simulate_reset_on_next_halt = true;
337
338 if (*dscr & ARM11_DSCR_CORE_HALTED)
339 {
340 /** \todo TODO: this needs further scrutiny because
341 * arm11_on_enter_debug_state() never gets properly called.
342 * As a result we don't read the actual register states from
343 * the target.
344 */
345
346 arm11->target->state = TARGET_HALTED;
347 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
348 }
349 else
350 {
351 arm11->target->state = TARGET_RUNNING;
352 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
353 }
354
355 arm11_sc7_clear_vbw(arm11);
356 }
357
358 return ERROR_OK;
359 }
360
361
362
363 #define R(x) \
364 (arm11->reg_values[ARM11_RC_##x])
365
366 /** Save processor state.
367 *
368 * This is called when the HALT instruction has succeeded
369 * or on other occasions that stop the processor.
370 *
371 */
372 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
373 {
374 FNC_INFO;
375
376 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
377 {
378 arm11->reg_list[i].valid = 1;
379 arm11->reg_list[i].dirty = 0;
380 }
381
382 /* Save DSCR */
383 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
384
385 /* Save wDTR */
386
387 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
388 {
389 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
390
391 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
392
393 scan_field_t chain5_fields[3];
394
395 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
396 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
397 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
398
399 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
400 }
401 else
402 {
403 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
404 }
405
406
407 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
408 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
409 ARM1136 seems to require this to issue ITR's as well */
410
411 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
412
413 /* this executes JTAG queue: */
414
415 arm11_write_DSCR(arm11, new_dscr);
416
417
418 /* From the spec:
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
421
422 /** \todo TODO: Test drain write buffer. */
423
424 #if 0
425 while (1)
426 {
427 /* MRC p14,0,R0,c5,c10,0 */
428 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
429
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
432
433 uint32_t dscr = arm11_read_DSCR(arm11);
434
435 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
436
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
438 {
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
440
441 dscr = arm11_read_DSCR(arm11);
442
443 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
444
445 break;
446 }
447 }
448 #endif
449
450 arm11_run_instr_data_prepare(arm11);
451
452 /* save r0 - r14 */
453
454 /** \todo TODO: handle other mode registers */
455
456 for (size_t i = 0; i < 15; i++)
457 {
458 /* MCR p14,0,R?,c0,c5,0 */
459 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
460 }
461
462 /* save rDTR */
463
464 /* check rDTRfull in DSCR */
465
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
467 {
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
470 }
471 else
472 {
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
474 }
475
476 /* save CPSR */
477
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
480
481 /* save PC */
482
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
485
486 /* adjust PC depending on ARM state */
487
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
489 {
490 arm11->reg_values[ARM11_RC_PC] -= 0;
491 }
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 4;
495 }
496 else /* ARM state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 8;
499 }
500
501 if (arm11->simulate_reset_on_next_halt)
502 {
503 arm11->simulate_reset_on_next_halt = false;
504
505 LOG_DEBUG("Reset c1 Control Register");
506
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
508
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
511
512 }
513
514 arm11_run_instr_data_finish(arm11);
515
516 arm11_dump_reg_changes(arm11);
517
518 return ERROR_OK;
519 }
520
521 void arm11_dump_reg_changes(arm11_common_t * arm11)
522 {
523
524 if (!(debug_level >= LOG_LVL_DEBUG))
525 {
526 return;
527 }
528
529 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
530 {
531 if (!arm11->reg_list[i].valid)
532 {
533 if (arm11->reg_history[i].valid)
534 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
535 }
536 else
537 {
538 if (arm11->reg_history[i].valid)
539 {
540 if (arm11->reg_history[i].value != arm11->reg_values[i])
541 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
542 }
543 else
544 {
545 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
546 }
547 }
548 }
549 }
550
551 /** Restore processor state
552 *
553 * This is called in preparation for the RESTART function.
554 *
555 */
556 int arm11_leave_debug_state(arm11_common_t * arm11)
557 {
558 FNC_INFO;
559
560 arm11_run_instr_data_prepare(arm11);
561
562 /** \todo TODO: handle other mode registers */
563
564 /* restore R1 - R14 */
565
566 for (size_t i = 1; i < 15; i++)
567 {
568 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
569 continue;
570
571 /* MRC p14,0,r?,c0,c5,0 */
572 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
573
574 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
575 }
576
577 arm11_run_instr_data_finish(arm11);
578
579 /* spec says clear wDTR and rDTR; we assume they are clear as
580 otherwise our programming would be sloppy */
581 {
582 uint32_t DSCR;
583
584 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
585
586 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
587 {
588 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
589 }
590 }
591
592 arm11_run_instr_data_prepare(arm11);
593
594 /* restore original wDTR */
595
596 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
597 {
598 /* MCR p14,0,R0,c0,c5,0 */
599 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
600 }
601
602 /* restore CPSR */
603
604 /* MSR CPSR,R0*/
605 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
606
607 /* restore PC */
608
609 /* MOV PC,R0 */
610 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
611
612 /* restore R0 */
613
614 /* MRC p14,0,r0,c0,c5,0 */
615 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
616
617 arm11_run_instr_data_finish(arm11);
618
619 /* restore DSCR */
620
621 arm11_write_DSCR(arm11, R(DSCR));
622
623 /* restore rDTR */
624
625 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
626 {
627 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
628
629 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
630
631 scan_field_t chain5_fields[3];
632
633 uint8_t Ready = 0; /* ignored */
634 uint8_t Valid = 0; /* ignored */
635
636 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
637 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
638 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
639
640 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
641 }
642
643 arm11_record_register_history(arm11);
644
645 return ERROR_OK;
646 }
647
648 void arm11_record_register_history(arm11_common_t * arm11)
649 {
650 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
651 {
652 arm11->reg_history[i].value = arm11->reg_values[i];
653 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
654
655 arm11->reg_list[i].valid = 0;
656 arm11->reg_list[i].dirty = 0;
657 }
658 }
659
660
661 /* poll current target status */
662 int arm11_poll(struct target_s *target)
663 {
664 FNC_INFO;
665
666 arm11_common_t * arm11 = target->arch_info;
667
668 if (arm11->trst_active)
669 return ERROR_OK;
670
671 uint32_t dscr;
672
673 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
674
675 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
676
677 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
678
679 if (dscr & ARM11_DSCR_CORE_HALTED)
680 {
681 if (target->state != TARGET_HALTED)
682 {
683 enum target_state old_state = target->state;
684
685 LOG_DEBUG("enter TARGET_HALTED");
686 target->state = TARGET_HALTED;
687 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
688 arm11_on_enter_debug_state(arm11);
689
690 target_call_event_callbacks(target,
691 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
692 }
693 }
694 else
695 {
696 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
697 {
698 LOG_DEBUG("enter TARGET_RUNNING");
699 target->state = TARGET_RUNNING;
700 target->debug_reason = DBG_REASON_NOTHALTED;
701 }
702 }
703
704 return ERROR_OK;
705 }
706 /* architecture specific status reply */
707 int arm11_arch_state(struct target_s *target)
708 {
709 arm11_common_t * arm11 = target->arch_info;
710
711 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
712 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
713 R(CPSR),
714 R(PC));
715
716 return ERROR_OK;
717 }
718
719 /* target request support */
720 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
721 {
722 FNC_INFO_NOTIMPLEMENTED;
723
724 return ERROR_OK;
725 }
726
727 /* target execution control */
728 int arm11_halt(struct target_s *target)
729 {
730 FNC_INFO;
731
732 arm11_common_t * arm11 = target->arch_info;
733
734 LOG_DEBUG("target->state: %s",
735 Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
736
737 if (target->state == TARGET_UNKNOWN)
738 {
739 arm11->simulate_reset_on_next_halt = true;
740 }
741
742 if (target->state == TARGET_HALTED)
743 {
744 LOG_DEBUG("target was already halted");
745 return ERROR_OK;
746 }
747
748 if (arm11->trst_active)
749 {
750 arm11->halt_requested = true;
751 return ERROR_OK;
752 }
753
754 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
755
756 CHECK_RETVAL(jtag_execute_queue());
757
758 uint32_t dscr;
759
760 while (1)
761 {
762 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
763
764 if (dscr & ARM11_DSCR_CORE_HALTED)
765 break;
766 }
767
768 arm11_on_enter_debug_state(arm11);
769
770 enum target_state old_state = target->state;
771
772 target->state = TARGET_HALTED;
773 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
774
775 CHECK_RETVAL(
776 target_call_event_callbacks(target,
777 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
778
779 return ERROR_OK;
780 }
781
782 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
783 {
784 FNC_INFO;
785
786 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
787 // current, address, handle_breakpoints, debug_execution);
788
789 arm11_common_t * arm11 = target->arch_info;
790
791 LOG_DEBUG("target->state: %s",
792 Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
793
794
795 if (target->state != TARGET_HALTED)
796 {
797 LOG_ERROR("Target not halted");
798 return ERROR_TARGET_NOT_HALTED;
799 }
800
801 if (!current)
802 R(PC) = address;
803
804 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
805
806 /* clear breakpoints/watchpoints and VCR*/
807 arm11_sc7_clear_vbw(arm11);
808
809 /* Set up breakpoints */
810 if (!debug_execution)
811 {
812 /* check if one matches PC and step over it if necessary */
813
814 breakpoint_t * bp;
815
816 for (bp = target->breakpoints; bp; bp = bp->next)
817 {
818 if (bp->address == R(PC))
819 {
820 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
821 arm11_step(target, 1, 0, 0);
822 break;
823 }
824 }
825
826 /* set all breakpoints */
827
828 size_t brp_num = 0;
829
830 for (bp = target->breakpoints; bp; bp = bp->next)
831 {
832 arm11_sc7_action_t brp[2];
833
834 brp[0].write = 1;
835 brp[0].address = ARM11_SC7_BVR0 + brp_num;
836 brp[0].value = bp->address;
837 brp[1].write = 1;
838 brp[1].address = ARM11_SC7_BCR0 + brp_num;
839 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
840
841 arm11_sc7_run(arm11, brp, asizeof(brp));
842
843 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
844
845 brp_num++;
846 }
847
848 arm11_sc7_set_vcr(arm11, arm11_vcr);
849 }
850
851 arm11_leave_debug_state(arm11);
852
853 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
854
855 CHECK_RETVAL(jtag_execute_queue());
856
857 while (1)
858 {
859 uint32_t dscr;
860
861 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
862
863 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
864
865 if (dscr & ARM11_DSCR_CORE_RESTARTED)
866 break;
867 }
868
869 if (!debug_execution)
870 {
871 target->state = TARGET_RUNNING;
872 target->debug_reason = DBG_REASON_NOTHALTED;
873
874 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
875 }
876 else
877 {
878 target->state = TARGET_DEBUG_RUNNING;
879 target->debug_reason = DBG_REASON_NOTHALTED;
880
881 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
882 }
883
884 return ERROR_OK;
885 }
886
887 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
888 {
889 FNC_INFO;
890
891 LOG_DEBUG("target->state: %s",
892 Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
893
894 if (target->state != TARGET_HALTED)
895 {
896 LOG_WARNING("target was not halted");
897 return ERROR_TARGET_NOT_HALTED;
898 }
899
900 arm11_common_t * arm11 = target->arch_info;
901
902 if (!current)
903 R(PC) = address;
904
905 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
906
907 /** \todo TODO: Thumb not supported here */
908
909 uint32_t next_instruction;
910
911 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
912
913 /* skip over BKPT */
914 if ((next_instruction & 0xFFF00070) == 0xe1200070)
915 {
916 R(PC) += 4;
917 arm11->reg_list[ARM11_RC_PC].valid = 1;
918 arm11->reg_list[ARM11_RC_PC].dirty = 0;
919 LOG_DEBUG("Skipping BKPT");
920 }
921 /* skip over Wait for interrupt / Standby */
922 /* mcr 15, 0, r?, cr7, cr0, {4} */
923 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
924 {
925 R(PC) += 4;
926 arm11->reg_list[ARM11_RC_PC].valid = 1;
927 arm11->reg_list[ARM11_RC_PC].dirty = 0;
928 LOG_DEBUG("Skipping WFI");
929 }
930 /* ignore B to self */
931 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
932 {
933 LOG_DEBUG("Not stepping jump to self");
934 }
935 else
936 {
937 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
938 * with this. */
939
940 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
941 * the VCR might be something worth looking into. */
942
943
944 /* Set up breakpoint for stepping */
945
946 arm11_sc7_action_t brp[2];
947
948 brp[0].write = 1;
949 brp[0].address = ARM11_SC7_BVR0;
950 brp[0].value = R(PC);
951 brp[1].write = 1;
952 brp[1].address = ARM11_SC7_BCR0;
953 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
954
955 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
956
957 /* resume */
958
959
960 if (arm11_config_step_irq_enable)
961 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
962 else
963 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
964
965
966 CHECK_RETVAL(arm11_leave_debug_state(arm11));
967
968 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
969
970 CHECK_RETVAL(jtag_execute_queue());
971
972 /** \todo TODO: add a timeout */
973
974 /* wait for halt */
975
976 while (1)
977 {
978 uint32_t dscr;
979
980 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
981
982 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
983
984 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
985 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
986 break;
987 }
988
989 /* clear breakpoint */
990 arm11_sc7_clear_vbw(arm11);
991
992 /* save state */
993 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
994
995 /* restore default state */
996 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
997
998 }
999
1000 // target->state = TARGET_HALTED;
1001 target->debug_reason = DBG_REASON_SINGLESTEP;
1002
1003 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1004
1005 return ERROR_OK;
1006 }
1007
1008 /* target reset control */
1009 int arm11_assert_reset(struct target_s *target)
1010 {
1011 FNC_INFO;
1012
1013 #if 0
1014 /* assert reset lines */
1015 /* resets only the DBGTAP, not the ARM */
1016
1017 jtag_add_reset(1, 0);
1018 jtag_add_sleep(5000);
1019
1020 arm11_common_t * arm11 = target->arch_info;
1021 arm11->trst_active = true;
1022 #endif
1023
1024 if (target->reset_halt)
1025 {
1026 CHECK_RETVAL(target_halt(target));
1027 }
1028
1029 return ERROR_OK;
1030 }
1031
1032 int arm11_deassert_reset(struct target_s *target)
1033 {
1034 FNC_INFO;
1035
1036 #if 0
1037 LOG_DEBUG("target->state: %s",
1038 Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
1039
1040
1041 /* deassert reset lines */
1042 jtag_add_reset(0, 0);
1043
1044 arm11_common_t * arm11 = target->arch_info;
1045 arm11->trst_active = false;
1046
1047 if (arm11->halt_requested)
1048 return arm11_halt(target);
1049 #endif
1050
1051 return ERROR_OK;
1052 }
1053
1054 int arm11_soft_reset_halt(struct target_s *target)
1055 {
1056 FNC_INFO_NOTIMPLEMENTED;
1057
1058 return ERROR_OK;
1059 }
1060
1061 /* target register access for gdb */
1062 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1063 {
1064 FNC_INFO;
1065
1066 arm11_common_t * arm11 = target->arch_info;
1067
1068 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1069 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1070
1071 for (size_t i = 16; i < 24; i++)
1072 {
1073 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1074 }
1075
1076 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1077
1078 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1079 {
1080 if (arm11_reg_defs[i].gdb_num == -1)
1081 continue;
1082
1083 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1084 }
1085
1086 return ERROR_OK;
1087 }
1088
1089 /* target memory access
1090 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1091 * count: number of items of <size>
1092 */
1093 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1094 {
1095 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1096
1097 FNC_INFO;
1098
1099 if (target->state != TARGET_HALTED)
1100 {
1101 LOG_WARNING("target was not halted");
1102 return ERROR_TARGET_NOT_HALTED;
1103 }
1104
1105 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1106
1107 arm11_common_t * arm11 = target->arch_info;
1108
1109 arm11_run_instr_data_prepare(arm11);
1110
1111 /* MRC p14,0,r0,c0,c5,0 */
1112 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1113
1114 switch (size)
1115 {
1116 case 1:
1117 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1118 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1119
1120 for (size_t i = 0; i < count; i++)
1121 {
1122 /* ldrb r1, [r0], #1 */
1123 /* ldrb r1, [r0] */
1124 arm11_run_instr_no_data1(arm11,
1125 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1126
1127 uint32_t res;
1128 /* MCR p14,0,R1,c0,c5,0 */
1129 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1130
1131 *buffer++ = res;
1132 }
1133
1134 break;
1135
1136 case 2:
1137 {
1138 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1139
1140 for (size_t i = 0; i < count; i++)
1141 {
1142 /* ldrh r1, [r0], #2 */
1143 arm11_run_instr_no_data1(arm11,
1144 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1145
1146 uint32_t res;
1147
1148 /* MCR p14,0,R1,c0,c5,0 */
1149 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1150
1151 uint16_t svalue = res;
1152 memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1153 }
1154
1155 break;
1156 }
1157
1158 case 4:
1159 {
1160 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1161 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1162 uint32_t *words = (uint32_t *)buffer;
1163
1164 /* LDC p14,c5,[R0],#4 */
1165 /* LDC p14,c5,[R0] */
1166 arm11_run_instr_data_from_core(arm11, instr, words, count);
1167 break;
1168 }
1169 }
1170
1171 arm11_run_instr_data_finish(arm11);
1172
1173 return ERROR_OK;
1174 }
1175
1176 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1177 {
1178 FNC_INFO;
1179
1180 if (target->state != TARGET_HALTED)
1181 {
1182 LOG_WARNING("target was not halted");
1183 return ERROR_TARGET_NOT_HALTED;
1184 }
1185
1186 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1187
1188 arm11_common_t * arm11 = target->arch_info;
1189
1190 arm11_run_instr_data_prepare(arm11);
1191
1192 /* MRC p14,0,r0,c0,c5,0 */
1193 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1194
1195 switch (size)
1196 {
1197 case 1:
1198 {
1199 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1200
1201 for (size_t i = 0; i < count; i++)
1202 {
1203 /* MRC p14,0,r1,c0,c5,0 */
1204 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1205
1206 /* strb r1, [r0], #1 */
1207 /* strb r1, [r0] */
1208 arm11_run_instr_no_data1(arm11,
1209 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1210 }
1211
1212 break;
1213 }
1214
1215 case 2:
1216 {
1217 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1218
1219 for (size_t i = 0; i < count; i++)
1220 {
1221 uint16_t value;
1222 memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t));
1223
1224 /* MRC p14,0,r1,c0,c5,0 */
1225 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1226
1227 /* strh r1, [r0], #2 */
1228 /* strh r1, [r0] */
1229 arm11_run_instr_no_data1(arm11,
1230 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1231 }
1232
1233 break;
1234 }
1235
1236 case 4: {
1237 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1238
1239 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1240 uint32_t *words = (uint32_t*)buffer;
1241
1242 if (!arm11_config_memwrite_burst)
1243 {
1244 /* STC p14,c5,[R0],#4 */
1245 /* STC p14,c5,[R0]*/
1246 arm11_run_instr_data_to_core(arm11, instr, words, count);
1247 }
1248 else
1249 {
1250 /* STC p14,c5,[R0],#4 */
1251 /* STC p14,c5,[R0]*/
1252 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1253 }
1254
1255 break;
1256 }
1257 }
1258
1259 #if 1
1260 /* r0 verification */
1261 if (!arm11_config_memrw_no_increment)
1262 {
1263 uint32_t r0;
1264
1265 /* MCR p14,0,R0,c0,c5,0 */
1266 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1267
1268 if (address + size * count != r0)
1269 {
1270 LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
1271
1272 if (arm11_config_memwrite_burst)
1273 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1274
1275 if (arm11_config_memwrite_error_fatal)
1276 return ERROR_FAIL;
1277 }
1278 }
1279 #endif
1280
1281 arm11_run_instr_data_finish(arm11);
1282
1283 return ERROR_OK;
1284 }
1285
1286
1287 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1288 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1289 {
1290 FNC_INFO;
1291
1292 if (target->state != TARGET_HALTED)
1293 {
1294 LOG_WARNING("target was not halted");
1295 return ERROR_TARGET_NOT_HALTED;
1296 }
1297
1298 return arm11_write_memory(target, address, 4, count, buffer);
1299 }
1300
1301 /* here we have nothing target specific to contribute, so we fail and then the
1302 * fallback code will read data from the target and calculate the CRC on the
1303 * host.
1304 */
1305 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1306 {
1307 return ERROR_FAIL;
1308 }
1309
1310 /* target break-/watchpoint control
1311 * rw: 0 = write, 1 = read, 2 = access
1312 */
1313 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1314 {
1315 FNC_INFO;
1316
1317 arm11_common_t * arm11 = target->arch_info;
1318
1319 #if 0
1320 if (breakpoint->type == BKPT_SOFT)
1321 {
1322 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1323 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1324 }
1325 #endif
1326
1327 if (!arm11->free_brps)
1328 {
1329 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1330 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1331 }
1332
1333 if (breakpoint->length != 4)
1334 {
1335 LOG_DEBUG("only breakpoints of four bytes length supported");
1336 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1337 }
1338
1339 arm11->free_brps--;
1340
1341 return ERROR_OK;
1342 }
1343
1344 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1345 {
1346 FNC_INFO;
1347
1348 arm11_common_t * arm11 = target->arch_info;
1349
1350 arm11->free_brps++;
1351
1352 return ERROR_OK;
1353 }
1354
1355 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1356 {
1357 FNC_INFO_NOTIMPLEMENTED;
1358
1359 return ERROR_OK;
1360 }
1361
1362 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1363 {
1364 FNC_INFO_NOTIMPLEMENTED;
1365
1366 return ERROR_OK;
1367 }
1368
1369 // HACKHACKHACK - FIXME mode/state
1370 /* target algorithm support */
1371 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1372 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1373 int timeout_ms, void *arch_info)
1374 {
1375 arm11_common_t *arm11 = target->arch_info;
1376 // enum armv4_5_state core_state = arm11->core_state;
1377 // enum armv4_5_mode core_mode = arm11->core_mode;
1378 uint32_t context[16];
1379 uint32_t cpsr;
1380 int exit_breakpoint_size = 0;
1381 int retval = ERROR_OK;
1382 LOG_DEBUG("Running algorithm");
1383
1384
1385 if (target->state != TARGET_HALTED)
1386 {
1387 LOG_WARNING("target not halted");
1388 return ERROR_TARGET_NOT_HALTED;
1389 }
1390
1391 // FIXME
1392 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1393 // return ERROR_FAIL;
1394
1395 // Save regs
1396 for (size_t i = 0; i < 16; i++)
1397 {
1398 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1399 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1400 }
1401
1402 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1403 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1404
1405 for (int i = 0; i < num_mem_params; i++)
1406 {
1407 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1408 }
1409
1410 // Set register parameters
1411 for (int i = 0; i < num_reg_params; i++)
1412 {
1413 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1414 if (!reg)
1415 {
1416 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1417 exit(-1);
1418 }
1419
1420 if (reg->size != reg_params[i].size)
1421 {
1422 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1423 exit(-1);
1424 }
1425 arm11_set_reg(reg,reg_params[i].value);
1426 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1427 }
1428
1429 exit_breakpoint_size = 4;
1430
1431 /* arm11->core_state = arm11_algorithm_info->core_state;
1432 if (arm11->core_state == ARMV4_5_STATE_ARM)
1433 exit_breakpoint_size = 4;
1434 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1435 exit_breakpoint_size = 2;
1436 else
1437 {
1438 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1439 exit(-1);
1440 }
1441 */
1442
1443
1444 /* arm11 at this point only supports ARM not THUMB mode
1445 however if this test needs to be reactivated the current state can be read back
1446 from CPSR */
1447 #if 0
1448 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1449 {
1450 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1451 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1452 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1453 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1454 }
1455 #endif
1456
1457 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1458 {
1459 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1460 retval = ERROR_TARGET_FAILURE;
1461 goto restore;
1462 }
1463
1464 // no debug, otherwise breakpoint is not set
1465 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1466
1467 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1468
1469 if (target->state != TARGET_HALTED)
1470 {
1471 CHECK_RETVAL(target_halt(target));
1472
1473 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1474
1475 retval = ERROR_TARGET_TIMEOUT;
1476
1477 goto del_breakpoint;
1478 }
1479
1480 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1481 {
1482 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1483 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1484 retval = ERROR_TARGET_TIMEOUT;
1485 goto del_breakpoint;
1486 }
1487
1488 for (int i = 0; i < num_mem_params; i++)
1489 {
1490 if (mem_params[i].direction != PARAM_OUT)
1491 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1492 }
1493
1494 for (int i = 0; i < num_reg_params; i++)
1495 {
1496 if (reg_params[i].direction != PARAM_OUT)
1497 {
1498 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1499 if (!reg)
1500 {
1501 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1502 exit(-1);
1503 }
1504
1505 if (reg->size != reg_params[i].size)
1506 {
1507 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1508 exit(-1);
1509 }
1510
1511 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1512 }
1513 }
1514
1515 del_breakpoint:
1516 breakpoint_remove(target, exit_point);
1517
1518 restore:
1519 // Restore context
1520 for (size_t i = 0; i < 16; i++)
1521 {
1522 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1523 arm11->reg_list[i].name, context[i]);
1524 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1525 }
1526 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1527 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1528
1529 // arm11->core_state = core_state;
1530 // arm11->core_mode = core_mode;
1531
1532 return retval;
1533 }
1534
1535 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1536 {
1537 FNC_INFO;
1538
1539 NEW(arm11_common_t, arm11, 1);
1540
1541 arm11->target = target;
1542
1543 if (target->tap == NULL)
1544 return ERROR_FAIL;
1545
1546 if (target->tap->ir_length != 5)
1547 {
1548 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1549 return ERROR_COMMAND_SYNTAX_ERROR;
1550 }
1551
1552 target->arch_info = arm11;
1553
1554 return ERROR_OK;
1555 }
1556
1557 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1558 {
1559 /* Initialize anything we can set up without talking to the target */
1560 return arm11_build_reg_cache(target);
1561 }
1562
1563 /* talk to the target and set things up */
1564 int arm11_examine(struct target_s *target)
1565 {
1566 FNC_INFO;
1567
1568 arm11_common_t * arm11 = target->arch_info;
1569
1570 /* check IDCODE */
1571
1572 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1573
1574 scan_field_t idcode_field;
1575
1576 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1577
1578 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1579
1580 /* check DIDR */
1581
1582 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1583
1584 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1585
1586 scan_field_t chain0_fields[2];
1587
1588 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1589 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1590
1591 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1592
1593 CHECK_RETVAL(jtag_execute_queue());
1594
1595 switch (arm11->device_id & 0x0FFFF000)
1596 {
1597 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1598 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1599 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1600 default:
1601 {
1602 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1603 return ERROR_FAIL;
1604 }
1605 }
1606
1607 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1608
1609 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1610 arm11->debug_version != ARM11_DEBUG_V61)
1611 {
1612 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1613 return ERROR_FAIL;
1614 }
1615
1616 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1617 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1618
1619 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1620 arm11->free_brps = arm11->brp;
1621 arm11->free_wrps = arm11->wrp;
1622
1623 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1624 arm11->device_id,
1625 (int)(arm11->implementor),
1626 arm11->didr);
1627
1628 /* as a side-effect this reads DSCR and thus
1629 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1630 * as suggested by the spec.
1631 */
1632
1633 arm11_check_init(arm11, NULL);
1634
1635 target_set_examined(target);
1636
1637 return ERROR_OK;
1638 }
1639
1640 int arm11_quit(void)
1641 {
1642 FNC_INFO_NOTIMPLEMENTED;
1643
1644 return ERROR_OK;
1645 }
1646
1647 /** Load a register that is marked !valid in the register cache */
1648 int arm11_get_reg(reg_t *reg)
1649 {
1650 FNC_INFO;
1651
1652 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1653
1654 if (target->state != TARGET_HALTED)
1655 {
1656 LOG_WARNING("target was not halted");
1657 return ERROR_TARGET_NOT_HALTED;
1658 }
1659
1660 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1661
1662 #if 0
1663 arm11_common_t *arm11 = target->arch_info;
1664 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1665 #endif
1666
1667 return ERROR_OK;
1668 }
1669
1670 /** Change a value in the register cache */
1671 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1672 {
1673 FNC_INFO;
1674
1675 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1676 arm11_common_t *arm11 = target->arch_info;
1677 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1678
1679 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1680 reg->valid = 1;
1681 reg->dirty = 1;
1682
1683 return ERROR_OK;
1684 }
1685
1686 int arm11_build_reg_cache(target_t *target)
1687 {
1688 arm11_common_t *arm11 = target->arch_info;
1689
1690 NEW(reg_cache_t, cache, 1);
1691 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1692 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1693
1694 if (arm11_regs_arch_type == -1)
1695 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1696
1697 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1698 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1699
1700 arm11->reg_list = reg_list;
1701
1702 /* Build the process context cache */
1703 cache->name = "arm11 registers";
1704 cache->next = NULL;
1705 cache->reg_list = reg_list;
1706 cache->num_regs = ARM11_REGCACHE_COUNT;
1707
1708 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1709 (*cache_p) = cache;
1710
1711 arm11->core_cache = cache;
1712 // armv7m->process_context = cache;
1713
1714 size_t i;
1715
1716 /* Not very elegant assertion */
1717 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1718 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1719 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1720 {
1721 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1722 exit(-1);
1723 }
1724
1725 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1726 {
1727 reg_t * r = reg_list + i;
1728 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1729 arm11_reg_state_t * rs = arm11_reg_states + i;
1730
1731 r->name = rd->name;
1732 r->size = 32;
1733 r->value = (uint8_t *)(arm11->reg_values + i);
1734 r->dirty = 0;
1735 r->valid = 0;
1736 r->bitfield_desc = NULL;
1737 r->num_bitfields = 0;
1738 r->arch_type = arm11_regs_arch_type;
1739 r->arch_info = rs;
1740
1741 rs->def_index = i;
1742 rs->target = target;
1743 }
1744
1745 return ERROR_OK;
1746 }
1747
1748 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1749 {
1750 if (argc == 0)
1751 {
1752 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1753 return ERROR_OK;
1754 }
1755
1756 if (argc != 1)
1757 return ERROR_COMMAND_SYNTAX_ERROR;
1758
1759 switch (args[0][0])
1760 {
1761 case '0': /* 0 */
1762 case 'f': /* false */
1763 case 'F':
1764 case 'd': /* disable */
1765 case 'D':
1766 *var = false;
1767 break;
1768
1769 case '1': /* 1 */
1770 case 't': /* true */
1771 case 'T':
1772 case 'e': /* enable */
1773 case 'E':
1774 *var = true;
1775 break;
1776 }
1777
1778 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1779
1780 return ERROR_OK;
1781 }
1782
1783 #define BOOL_WRAPPER(name, print_name) \
1784 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1785 { \
1786 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1787 }
1788
1789 #define RC_TOP(name, descr, more) \
1790 { \
1791 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1792 command_t * top_cmd = new_cmd; \
1793 more \
1794 }
1795
1796 #define RC_FINAL(name, descr, handler) \
1797 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1798
1799 #define RC_FINAL_BOOL(name, descr, var) \
1800 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1801
1802 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1803 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1804 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1805 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1806
1807 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1808 {
1809 if (argc == 1)
1810 {
1811 arm11_vcr = strtoul(args[0], NULL, 0);
1812 }
1813 else if (argc != 0)
1814 {
1815 return ERROR_COMMAND_SYNTAX_ERROR;
1816 }
1817
1818 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1819 return ERROR_OK;
1820 }
1821
1822 const uint32_t arm11_coproc_instruction_limits[] =
1823 {
1824 15, /* coprocessor */
1825 7, /* opcode 1 */
1826 15, /* CRn */
1827 15, /* CRm */
1828 7, /* opcode 2 */
1829 0xFFFFFFFF, /* value */
1830 };
1831
1832 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1833 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1834
1835 arm11_common_t * arm11_find_target(const char * arg)
1836 {
1837 jtag_tap_t * tap;
1838 target_t * t;
1839
1840 tap = jtag_tap_by_string(arg);
1841
1842 if (!tap)
1843 return 0;
1844
1845 for (t = all_targets; t; t = t->next)
1846 {
1847 if (t->tap != tap)
1848 continue;
1849
1850 /* if (t->type == arm11_target) */
1851 if (0 == strcmp(target_get_name(t), "arm11"))
1852 return t->arch_info;
1853 }
1854
1855 return 0;
1856 }
1857
1858 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1859 {
1860 if (argc != (read ? 6 : 7))
1861 {
1862 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1863 return -1;
1864 }
1865
1866 arm11_common_t * arm11 = arm11_find_target(args[0]);
1867
1868 if (!arm11)
1869 {
1870 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1871 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1872
1873 return -1;
1874 }
1875
1876 if (arm11->target->state != TARGET_HALTED)
1877 {
1878 LOG_WARNING("target was not halted");
1879 return ERROR_TARGET_NOT_HALTED;
1880 }
1881
1882 uint32_t values[6];
1883
1884 for (size_t i = 0; i < (read ? 5 : 6); i++)
1885 {
1886 values[i] = strtoul(args[i + 1], NULL, 0);
1887
1888 if (values[i] > arm11_coproc_instruction_limits[i])
1889 {
1890 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
1891 (long)(i + 2),
1892 arm11_coproc_instruction_limits[i],
1893 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1894 return -1;
1895 }
1896 }
1897
1898 uint32_t instr = 0xEE000010 |
1899 (values[0] << 8) |
1900 (values[1] << 21) |
1901 (values[2] << 16) |
1902 (values[3] << 0) |
1903 (values[4] << 5);
1904
1905 if (read)
1906 instr |= 0x00100000;
1907
1908 arm11_run_instr_data_prepare(arm11);
1909
1910 if (read)
1911 {
1912 uint32_t result;
1913 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1914
1915 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
1916 (int)(values[0]),
1917 (int)(values[1]),
1918 (int)(values[2]),
1919 (int)(values[3]),
1920 (int)(values[4]), result, result);
1921 }
1922 else
1923 {
1924 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1925
1926 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
1927 (int)(values[0]), (int)(values[1]),
1928 values[5],
1929 (int)(values[2]), (int)(values[3]), (int)(values[4]));
1930 }
1931
1932 arm11_run_instr_data_finish(arm11);
1933
1934
1935 return ERROR_OK;
1936 }
1937
1938 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1939 {
1940 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1941 }
1942
1943 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1944 {
1945 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1946 }
1947
1948 int arm11_register_commands(struct command_context_s *cmd_ctx)
1949 {
1950 FNC_INFO;
1951
1952 command_t * top_cmd = NULL;
1953
1954 RC_TOP("arm11", "arm11 specific commands",
1955
1956 RC_TOP("memwrite", "Control memory write transfer mode",
1957
1958 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1959 memwrite_burst)
1960
1961 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
1962 memwrite_error_fatal)
1963 ) /* memwrite */
1964
1965 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
1966 memrw_no_increment)
1967
1968 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
1969 step_irq_enable)
1970
1971 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
1972 arm11_handle_vcr)
1973
1974 RC_FINAL("mrc", "Read Coprocessor register",
1975 arm11_handle_mrc)
1976
1977 RC_FINAL("mcr", "Write Coprocessor register",
1978 arm11_handle_mcr)
1979 ) /* arm11 */
1980
1981 return ERROR_OK;
1982 }
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|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)