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Propagate wDTR/rDTR failure immediately, otherwise it's followed up by timeout errors.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
34
35
36 #if 0
37 #define _DEBUG_INSTRUCTION_EXECUTION_
38 #endif
39
40 #if 0
41 #define FNC_INFO LOG_DEBUG("-")
42 #else
43 #define FNC_INFO
44 #endif
45
46 #if 1
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #else
49 #define FNC_INFO_NOTIMPLEMENTED
50 #endif
51
52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
53
54 bool arm11_config_memwrite_burst = true;
55 bool arm11_config_memwrite_error_fatal = true;
56 uint32_t arm11_vcr = 0;
57 bool arm11_config_memrw_no_increment = false;
58 bool arm11_config_step_irq_enable = false;
59 bool arm11_config_hardware_step = false;
60
61 #define ARM11_HANDLER(x) \
62 .x = arm11_##x
63
64 target_type_t arm11_target =
65 {
66 .name = "arm11",
67
68 ARM11_HANDLER(poll),
69 ARM11_HANDLER(arch_state),
70
71 ARM11_HANDLER(target_request_data),
72
73 ARM11_HANDLER(halt),
74 ARM11_HANDLER(resume),
75 ARM11_HANDLER(step),
76
77 ARM11_HANDLER(assert_reset),
78 ARM11_HANDLER(deassert_reset),
79 ARM11_HANDLER(soft_reset_halt),
80
81 ARM11_HANDLER(get_gdb_reg_list),
82
83 ARM11_HANDLER(read_memory),
84 ARM11_HANDLER(write_memory),
85
86 ARM11_HANDLER(bulk_write_memory),
87
88 ARM11_HANDLER(checksum_memory),
89
90 ARM11_HANDLER(add_breakpoint),
91 ARM11_HANDLER(remove_breakpoint),
92 ARM11_HANDLER(add_watchpoint),
93 ARM11_HANDLER(remove_watchpoint),
94
95 ARM11_HANDLER(run_algorithm),
96
97 ARM11_HANDLER(register_commands),
98 ARM11_HANDLER(target_create),
99 ARM11_HANDLER(init_target),
100 ARM11_HANDLER(examine),
101 ARM11_HANDLER(quit),
102 };
103
104 int arm11_regs_arch_type = -1;
105
106
107 enum arm11_regtype
108 {
109 ARM11_REGISTER_CORE,
110 ARM11_REGISTER_CPSR,
111
112 ARM11_REGISTER_FX,
113 ARM11_REGISTER_FPS,
114
115 ARM11_REGISTER_FIQ,
116 ARM11_REGISTER_SVC,
117 ARM11_REGISTER_ABT,
118 ARM11_REGISTER_IRQ,
119 ARM11_REGISTER_UND,
120 ARM11_REGISTER_MON,
121
122 ARM11_REGISTER_SPSR_FIQ,
123 ARM11_REGISTER_SPSR_SVC,
124 ARM11_REGISTER_SPSR_ABT,
125 ARM11_REGISTER_SPSR_IRQ,
126 ARM11_REGISTER_SPSR_UND,
127 ARM11_REGISTER_SPSR_MON,
128
129 /* debug regs */
130 ARM11_REGISTER_DSCR,
131 ARM11_REGISTER_WDTR,
132 ARM11_REGISTER_RDTR,
133 };
134
135
136 typedef struct arm11_reg_defs_s
137 {
138 char * name;
139 uint32_t num;
140 int gdb_num;
141 enum arm11_regtype type;
142 } arm11_reg_defs_t;
143
144 /* update arm11_regcache_ids when changing this */
145 static const arm11_reg_defs_t arm11_reg_defs[] =
146 {
147 {"r0", 0, 0, ARM11_REGISTER_CORE},
148 {"r1", 1, 1, ARM11_REGISTER_CORE},
149 {"r2", 2, 2, ARM11_REGISTER_CORE},
150 {"r3", 3, 3, ARM11_REGISTER_CORE},
151 {"r4", 4, 4, ARM11_REGISTER_CORE},
152 {"r5", 5, 5, ARM11_REGISTER_CORE},
153 {"r6", 6, 6, ARM11_REGISTER_CORE},
154 {"r7", 7, 7, ARM11_REGISTER_CORE},
155 {"r8", 8, 8, ARM11_REGISTER_CORE},
156 {"r9", 9, 9, ARM11_REGISTER_CORE},
157 {"r10", 10, 10, ARM11_REGISTER_CORE},
158 {"r11", 11, 11, ARM11_REGISTER_CORE},
159 {"r12", 12, 12, ARM11_REGISTER_CORE},
160 {"sp", 13, 13, ARM11_REGISTER_CORE},
161 {"lr", 14, 14, ARM11_REGISTER_CORE},
162 {"pc", 15, 15, ARM11_REGISTER_CORE},
163
164 #if ARM11_REGCACHE_FREGS
165 {"f0", 0, 16, ARM11_REGISTER_FX},
166 {"f1", 1, 17, ARM11_REGISTER_FX},
167 {"f2", 2, 18, ARM11_REGISTER_FX},
168 {"f3", 3, 19, ARM11_REGISTER_FX},
169 {"f4", 4, 20, ARM11_REGISTER_FX},
170 {"f5", 5, 21, ARM11_REGISTER_FX},
171 {"f6", 6, 22, ARM11_REGISTER_FX},
172 {"f7", 7, 23, ARM11_REGISTER_FX},
173 {"fps", 0, 24, ARM11_REGISTER_FPS},
174 #endif
175
176 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
177
178 #if ARM11_REGCACHE_MODEREGS
179 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
180 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
181 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
182 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
183 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
184 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
185 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
186 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
187
188 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
189 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
190 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
191
192 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
193 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
194 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
195
196 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
197 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
198 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
199
200 {"r13_und", 13, -1, ARM11_REGISTER_UND},
201 {"r14_und", 14, -1, ARM11_REGISTER_UND},
202 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
203
204 /* ARM1176 only */
205 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
206 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
207 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
208 #endif
209
210 /* Debug Registers */
211 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
212 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
213 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
214 };
215
216 enum arm11_regcache_ids
217 {
218 ARM11_RC_R0,
219 ARM11_RC_RX = ARM11_RC_R0,
220
221 ARM11_RC_R1,
222 ARM11_RC_R2,
223 ARM11_RC_R3,
224 ARM11_RC_R4,
225 ARM11_RC_R5,
226 ARM11_RC_R6,
227 ARM11_RC_R7,
228 ARM11_RC_R8,
229 ARM11_RC_R9,
230 ARM11_RC_R10,
231 ARM11_RC_R11,
232 ARM11_RC_R12,
233 ARM11_RC_R13,
234 ARM11_RC_SP = ARM11_RC_R13,
235 ARM11_RC_R14,
236 ARM11_RC_LR = ARM11_RC_R14,
237 ARM11_RC_R15,
238 ARM11_RC_PC = ARM11_RC_R15,
239
240 #if ARM11_REGCACHE_FREGS
241 ARM11_RC_F0,
242 ARM11_RC_FX = ARM11_RC_F0,
243 ARM11_RC_F1,
244 ARM11_RC_F2,
245 ARM11_RC_F3,
246 ARM11_RC_F4,
247 ARM11_RC_F5,
248 ARM11_RC_F6,
249 ARM11_RC_F7,
250 ARM11_RC_FPS,
251 #endif
252
253 ARM11_RC_CPSR,
254
255 #if ARM11_REGCACHE_MODEREGS
256 ARM11_RC_R8_FIQ,
257 ARM11_RC_R9_FIQ,
258 ARM11_RC_R10_FIQ,
259 ARM11_RC_R11_FIQ,
260 ARM11_RC_R12_FIQ,
261 ARM11_RC_R13_FIQ,
262 ARM11_RC_R14_FIQ,
263 ARM11_RC_SPSR_FIQ,
264
265 ARM11_RC_R13_SVC,
266 ARM11_RC_R14_SVC,
267 ARM11_RC_SPSR_SVC,
268
269 ARM11_RC_R13_ABT,
270 ARM11_RC_R14_ABT,
271 ARM11_RC_SPSR_ABT,
272
273 ARM11_RC_R13_IRQ,
274 ARM11_RC_R14_IRQ,
275 ARM11_RC_SPSR_IRQ,
276
277 ARM11_RC_R13_UND,
278 ARM11_RC_R14_UND,
279 ARM11_RC_SPSR_UND,
280
281 ARM11_RC_R13_MON,
282 ARM11_RC_R14_MON,
283 ARM11_RC_SPSR_MON,
284 #endif
285
286 ARM11_RC_DSCR,
287 ARM11_RC_WDTR,
288 ARM11_RC_RDTR,
289
290 ARM11_RC_MAX,
291 };
292
293 #define ARM11_GDB_REGISTER_COUNT 26
294
295 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
296
297 reg_t arm11_gdb_dummy_fp_reg =
298 {
299 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
300 };
301
302 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
303
304 reg_t arm11_gdb_dummy_fps_reg =
305 {
306 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
307 };
308
309
310
311 /** Check and if necessary take control of the system
312 *
313 * \param arm11 Target state variable.
314 * \param dscr If the current DSCR content is
315 * available a pointer to a word holding the
316 * DSCR can be passed. Otherwise use NULL.
317 */
318 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
319 {
320 FNC_INFO;
321
322 uint32_t dscr_local_tmp_copy;
323
324 if (!dscr)
325 {
326 dscr = &dscr_local_tmp_copy;
327
328 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
329 }
330
331 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
332 {
333 LOG_DEBUG("Bringing target into debug mode");
334
335 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
336 arm11_write_DSCR(arm11, *dscr);
337
338 /* add further reset initialization here */
339
340 arm11->simulate_reset_on_next_halt = true;
341
342 if (*dscr & ARM11_DSCR_CORE_HALTED)
343 {
344 /** \todo TODO: this needs further scrutiny because
345 * arm11_on_enter_debug_state() never gets properly called.
346 * As a result we don't read the actual register states from
347 * the target.
348 */
349
350 arm11->target->state = TARGET_HALTED;
351 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
352 }
353 else
354 {
355 arm11->target->state = TARGET_RUNNING;
356 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
357 }
358
359 arm11_sc7_clear_vbw(arm11);
360 }
361
362 return ERROR_OK;
363 }
364
365
366
367 #define R(x) \
368 (arm11->reg_values[ARM11_RC_##x])
369
370 /** Save processor state.
371 *
372 * This is called when the HALT instruction has succeeded
373 * or on other occasions that stop the processor.
374 *
375 */
376 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
377 {
378 int retval;
379 FNC_INFO;
380
381 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
382 {
383 arm11->reg_list[i].valid = 1;
384 arm11->reg_list[i].dirty = 0;
385 }
386
387 /* Save DSCR */
388 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
389
390 /* Save wDTR */
391
392 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
393 {
394 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
395
396 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
397
398 scan_field_t chain5_fields[3];
399
400 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
402 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
403
404 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
405 }
406 else
407 {
408 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
409 }
410
411
412 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
413 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
414 ARM1136 seems to require this to issue ITR's as well */
415
416 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
417
418 /* this executes JTAG queue: */
419
420 arm11_write_DSCR(arm11, new_dscr);
421
422
423 /* From the spec:
424 Before executing any instruction in debug state you have to drain the write buffer.
425 This ensures that no imprecise Data Aborts can return at a later point:*/
426
427 /** \todo TODO: Test drain write buffer. */
428
429 #if 0
430 while (1)
431 {
432 /* MRC p14,0,R0,c5,c10,0 */
433 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
434
435 /* mcr 15, 0, r0, cr7, cr10, {4} */
436 arm11_run_instr_no_data1(arm11, 0xee070f9a);
437
438 uint32_t dscr = arm11_read_DSCR(arm11);
439
440 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
441
442 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
443 {
444 arm11_run_instr_no_data1(arm11, 0xe320f000);
445
446 dscr = arm11_read_DSCR(arm11);
447
448 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
449
450 break;
451 }
452 }
453 #endif
454
455 retval = arm11_run_instr_data_prepare(arm11);
456 if (retval != ERROR_OK)
457 return retval;
458
459 /* save r0 - r14 */
460
461 /** \todo TODO: handle other mode registers */
462
463 for (size_t i = 0; i < 15; i++)
464 {
465 /* MCR p14,0,R?,c0,c5,0 */
466 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
467 if (retval != ERROR_OK)
468 return retval;
469 }
470
471 /* save rDTR */
472
473 /* check rDTRfull in DSCR */
474
475 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
476 {
477 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
478 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
479 if (retval != ERROR_OK)
480 return retval;
481 }
482 else
483 {
484 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
485 }
486
487 /* save CPSR */
488
489 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
490 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
491 if (retval != ERROR_OK)
492 return retval;
493
494 /* save PC */
495
496 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
497 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
498 if (retval != ERROR_OK)
499 return retval;
500
501 /* adjust PC depending on ARM state */
502
503 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
504 {
505 arm11->reg_values[ARM11_RC_PC] -= 0;
506 }
507 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
508 {
509 arm11->reg_values[ARM11_RC_PC] -= 4;
510 }
511 else /* ARM state */
512 {
513 arm11->reg_values[ARM11_RC_PC] -= 8;
514 }
515
516 if (arm11->simulate_reset_on_next_halt)
517 {
518 arm11->simulate_reset_on_next_halt = false;
519
520 LOG_DEBUG("Reset c1 Control Register");
521
522 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
523
524 /* MCR p15,0,R0,c1,c0,0 */
525 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
526 if (retval != ERROR_OK)
527 return retval;
528
529 }
530
531 retval = arm11_run_instr_data_finish(arm11);
532 if (retval != ERROR_OK)
533 return retval;
534
535 arm11_dump_reg_changes(arm11);
536
537 return ERROR_OK;
538 }
539
540 void arm11_dump_reg_changes(arm11_common_t * arm11)
541 {
542
543 if (!(debug_level >= LOG_LVL_DEBUG))
544 {
545 return;
546 }
547
548 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
549 {
550 if (!arm11->reg_list[i].valid)
551 {
552 if (arm11->reg_history[i].valid)
553 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
554 }
555 else
556 {
557 if (arm11->reg_history[i].valid)
558 {
559 if (arm11->reg_history[i].value != arm11->reg_values[i])
560 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
561 }
562 else
563 {
564 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
565 }
566 }
567 }
568 }
569
570 /** Restore processor state
571 *
572 * This is called in preparation for the RESTART function.
573 *
574 */
575 int arm11_leave_debug_state(arm11_common_t * arm11)
576 {
577 FNC_INFO;
578 int retval;
579
580 retval = arm11_run_instr_data_prepare(arm11);
581 if (retval != ERROR_OK)
582 return retval;
583
584 /** \todo TODO: handle other mode registers */
585
586 /* restore R1 - R14 */
587
588 for (size_t i = 1; i < 15; i++)
589 {
590 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
591 continue;
592
593 /* MRC p14,0,r?,c0,c5,0 */
594 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
595
596 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
597 }
598
599 retval = arm11_run_instr_data_finish(arm11);
600 if (retval != ERROR_OK)
601 return retval;
602
603 /* spec says clear wDTR and rDTR; we assume they are clear as
604 otherwise our programming would be sloppy */
605 {
606 uint32_t DSCR;
607
608 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
609
610 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
611 {
612 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
613 return ERROR_FAIL;
614 }
615 }
616
617 retval = arm11_run_instr_data_prepare(arm11);
618 if (retval != ERROR_OK)
619 return retval;
620
621 /* restore original wDTR */
622
623 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
624 {
625 /* MCR p14,0,R0,c0,c5,0 */
626 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
627 if (retval != ERROR_OK)
628 return retval;
629 }
630
631 /* restore CPSR */
632
633 /* MSR CPSR,R0*/
634 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
635 if (retval != ERROR_OK)
636 return retval;
637
638
639 /* restore PC */
640
641 /* MOV PC,R0 */
642 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
643 if (retval != ERROR_OK)
644 return retval;
645
646
647 /* restore R0 */
648
649 /* MRC p14,0,r0,c0,c5,0 */
650 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
651
652 retval = arm11_run_instr_data_finish(arm11);
653 if (retval != ERROR_OK)
654 return retval;
655
656 /* restore DSCR */
657
658 arm11_write_DSCR(arm11, R(DSCR));
659
660 /* restore rDTR */
661
662 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
663 {
664 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
665
666 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
667
668 scan_field_t chain5_fields[3];
669
670 uint8_t Ready = 0; /* ignored */
671 uint8_t Valid = 0; /* ignored */
672
673 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
674 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
675 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
676
677 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
678 }
679
680 arm11_record_register_history(arm11);
681
682 return ERROR_OK;
683 }
684
685 void arm11_record_register_history(arm11_common_t * arm11)
686 {
687 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
688 {
689 arm11->reg_history[i].value = arm11->reg_values[i];
690 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
691
692 arm11->reg_list[i].valid = 0;
693 arm11->reg_list[i].dirty = 0;
694 }
695 }
696
697
698 /* poll current target status */
699 int arm11_poll(struct target_s *target)
700 {
701 FNC_INFO;
702 int retval;
703
704 arm11_common_t * arm11 = target->arch_info;
705
706 if (arm11->trst_active)
707 return ERROR_OK;
708
709 uint32_t dscr;
710
711 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
712
713 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
714
715 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
716
717 if (dscr & ARM11_DSCR_CORE_HALTED)
718 {
719 if (target->state != TARGET_HALTED)
720 {
721 enum target_state old_state = target->state;
722
723 LOG_DEBUG("enter TARGET_HALTED");
724 target->state = TARGET_HALTED;
725 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
726 retval = arm11_on_enter_debug_state(arm11);
727 if (retval != ERROR_OK)
728 return retval;
729
730 target_call_event_callbacks(target,
731 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
732 }
733 }
734 else
735 {
736 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
737 {
738 LOG_DEBUG("enter TARGET_RUNNING");
739 target->state = TARGET_RUNNING;
740 target->debug_reason = DBG_REASON_NOTHALTED;
741 }
742 }
743
744 return ERROR_OK;
745 }
746 /* architecture specific status reply */
747 int arm11_arch_state(struct target_s *target)
748 {
749 arm11_common_t * arm11 = target->arch_info;
750
751 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
752 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
753 R(CPSR),
754 R(PC));
755
756 return ERROR_OK;
757 }
758
759 /* target request support */
760 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
761 {
762 FNC_INFO_NOTIMPLEMENTED;
763
764 return ERROR_OK;
765 }
766
767 /* target execution control */
768 int arm11_halt(struct target_s *target)
769 {
770 FNC_INFO;
771
772 arm11_common_t * arm11 = target->arch_info;
773
774 LOG_DEBUG("target->state: %s",
775 target_state_name(target));
776
777 if (target->state == TARGET_UNKNOWN)
778 {
779 arm11->simulate_reset_on_next_halt = true;
780 }
781
782 if (target->state == TARGET_HALTED)
783 {
784 LOG_DEBUG("target was already halted");
785 return ERROR_OK;
786 }
787
788 if (arm11->trst_active)
789 {
790 arm11->halt_requested = true;
791 return ERROR_OK;
792 }
793
794 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
795
796 CHECK_RETVAL(jtag_execute_queue());
797
798 uint32_t dscr;
799
800 int i = 0;
801 while (1)
802 {
803 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
804
805 if (dscr & ARM11_DSCR_CORE_HALTED)
806 break;
807
808
809 long long then = 0;
810 if (i == 1000)
811 {
812 then = timeval_ms();
813 }
814 if (i >= 1000)
815 {
816 if ((timeval_ms()-then) > 1000)
817 {
818 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
819 return ERROR_FAIL;
820 }
821 }
822 i++;
823 }
824
825 arm11_on_enter_debug_state(arm11);
826
827 enum target_state old_state = target->state;
828
829 target->state = TARGET_HALTED;
830 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
831
832 CHECK_RETVAL(
833 target_call_event_callbacks(target,
834 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
835
836 return ERROR_OK;
837 }
838
839 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
840 {
841 FNC_INFO;
842
843 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
844 // current, address, handle_breakpoints, debug_execution);
845
846 arm11_common_t * arm11 = target->arch_info;
847
848 LOG_DEBUG("target->state: %s",
849 target_state_name(target));
850
851
852 if (target->state != TARGET_HALTED)
853 {
854 LOG_ERROR("Target not halted");
855 return ERROR_TARGET_NOT_HALTED;
856 }
857
858 if (!current)
859 R(PC) = address;
860
861 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
862
863 /* clear breakpoints/watchpoints and VCR*/
864 arm11_sc7_clear_vbw(arm11);
865
866 /* Set up breakpoints */
867 if (!debug_execution)
868 {
869 /* check if one matches PC and step over it if necessary */
870
871 breakpoint_t * bp;
872
873 for (bp = target->breakpoints; bp; bp = bp->next)
874 {
875 if (bp->address == R(PC))
876 {
877 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
878 arm11_step(target, 1, 0, 0);
879 break;
880 }
881 }
882
883 /* set all breakpoints */
884
885 size_t brp_num = 0;
886
887 for (bp = target->breakpoints; bp; bp = bp->next)
888 {
889 arm11_sc7_action_t brp[2];
890
891 brp[0].write = 1;
892 brp[0].address = ARM11_SC7_BVR0 + brp_num;
893 brp[0].value = bp->address;
894 brp[1].write = 1;
895 brp[1].address = ARM11_SC7_BCR0 + brp_num;
896 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
897
898 arm11_sc7_run(arm11, brp, asizeof(brp));
899
900 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
901
902 brp_num++;
903 }
904
905 arm11_sc7_set_vcr(arm11, arm11_vcr);
906 }
907
908 arm11_leave_debug_state(arm11);
909
910 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
911
912 CHECK_RETVAL(jtag_execute_queue());
913
914 int i = 0;
915 while (1)
916 {
917 uint32_t dscr;
918
919 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
920
921 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
922
923 if (dscr & ARM11_DSCR_CORE_RESTARTED)
924 break;
925
926
927 long long then = 0;
928 if (i == 1000)
929 {
930 then = timeval_ms();
931 }
932 if (i >= 1000)
933 {
934 if ((timeval_ms()-then) > 1000)
935 {
936 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
937 return ERROR_FAIL;
938 }
939 }
940 i++;
941 }
942
943 if (!debug_execution)
944 {
945 target->state = TARGET_RUNNING;
946 target->debug_reason = DBG_REASON_NOTHALTED;
947
948 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
949 }
950 else
951 {
952 target->state = TARGET_DEBUG_RUNNING;
953 target->debug_reason = DBG_REASON_NOTHALTED;
954
955 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
956 }
957
958 return ERROR_OK;
959 }
960
961
962 static int armv4_5_to_arm11(int reg)
963 {
964 if (reg < 16)
965 return reg;
966 switch (reg)
967 {
968 case ARMV4_5_CPSR:
969 return ARM11_RC_CPSR;
970 case 16:
971 /* FIX!!! handle thumb better! */
972 return ARM11_RC_CPSR;
973 default:
974 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
975 exit(-1);
976 }
977 }
978
979
980 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
981 {
982 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
983
984 reg=armv4_5_to_arm11(reg);
985
986 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
987 }
988
989 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
990 {
991 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
992
993 reg=armv4_5_to_arm11(reg);
994
995 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
996 }
997
998 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
999 {
1000 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1001
1002 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
1003 }
1004
1005 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
1006 {
1007 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1008
1009 /* FIX!!!! we should implement thumb for arm11 */
1010 return ARMV4_5_STATE_ARM;
1011 }
1012
1013 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
1014 {
1015 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1016
1017 /* FIX!!!! we should implement thumb for arm11 */
1018 LOG_ERROR("Not implemetned!");
1019 }
1020
1021
1022 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1023 {
1024 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1025
1026 /* FIX!!!! we should implement something that returns the current mode here!!! */
1027 return ARMV4_5_MODE_USR;
1028 }
1029
1030 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1031 {
1032 struct arm_sim_interface sim;
1033
1034 sim.user_data=target->arch_info;
1035 sim.get_reg=&arm11_sim_get_reg;
1036 sim.set_reg=&arm11_sim_set_reg;
1037 sim.get_reg_mode=&arm11_sim_get_reg;
1038 sim.set_reg_mode=&arm11_sim_set_reg;
1039 sim.get_cpsr=&arm11_sim_get_cpsr;
1040 sim.get_mode=&arm11_sim_get_mode;
1041 sim.get_state=&arm11_sim_get_state;
1042 sim.set_state=&arm11_sim_set_state;
1043
1044 return arm_simulate_step_core(target, dry_run_pc, &sim);
1045
1046 }
1047
1048 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1049 {
1050 FNC_INFO;
1051
1052 LOG_DEBUG("target->state: %s",
1053 target_state_name(target));
1054
1055 if (target->state != TARGET_HALTED)
1056 {
1057 LOG_WARNING("target was not halted");
1058 return ERROR_TARGET_NOT_HALTED;
1059 }
1060
1061 arm11_common_t * arm11 = target->arch_info;
1062
1063 if (!current)
1064 R(PC) = address;
1065
1066 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1067
1068
1069 /** \todo TODO: Thumb not supported here */
1070
1071 uint32_t next_instruction;
1072
1073 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1074
1075 /* skip over BKPT */
1076 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1077 {
1078 R(PC) += 4;
1079 arm11->reg_list[ARM11_RC_PC].valid = 1;
1080 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1081 LOG_DEBUG("Skipping BKPT");
1082 }
1083 /* skip over Wait for interrupt / Standby */
1084 /* mcr 15, 0, r?, cr7, cr0, {4} */
1085 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1086 {
1087 R(PC) += 4;
1088 arm11->reg_list[ARM11_RC_PC].valid = 1;
1089 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1090 LOG_DEBUG("Skipping WFI");
1091 }
1092 /* ignore B to self */
1093 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1094 {
1095 LOG_DEBUG("Not stepping jump to self");
1096 }
1097 else
1098 {
1099 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1100 * with this. */
1101
1102 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1103 * the VCR might be something worth looking into. */
1104
1105
1106 /* Set up breakpoint for stepping */
1107
1108 arm11_sc7_action_t brp[2];
1109
1110 brp[0].write = 1;
1111 brp[0].address = ARM11_SC7_BVR0;
1112 brp[1].write = 1;
1113 brp[1].address = ARM11_SC7_BCR0;
1114
1115 if (arm11_config_hardware_step)
1116 {
1117 /* hardware single stepping be used if possible or is it better to
1118 * always use the same code path? Hardware single stepping is not supported
1119 * on all hardware
1120 */
1121 brp[0].value = R(PC);
1122 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1123 } else
1124 {
1125 /* sets a breakpoint on the next PC(calculated by simulation),
1126 */
1127 uint32_t next_pc;
1128 int retval;
1129 retval = arm11_simulate_step(target, &next_pc);
1130 if (retval != ERROR_OK)
1131 return retval;
1132
1133 brp[0].value = next_pc;
1134 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1135 }
1136
1137 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1138
1139 /* resume */
1140
1141
1142 if (arm11_config_step_irq_enable)
1143 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1144 else
1145 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1146
1147
1148 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1149
1150 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1151
1152 CHECK_RETVAL(jtag_execute_queue());
1153
1154 /* wait for halt */
1155 int i = 0;
1156 while (1)
1157 {
1158 uint32_t dscr;
1159
1160 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1161
1162 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1163
1164 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1165 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1166 break;
1167
1168 long long then = 0;
1169 if (i == 1000)
1170 {
1171 then = timeval_ms();
1172 }
1173 if (i >= 1000)
1174 {
1175 if ((timeval_ms()-then) > 1000)
1176 {
1177 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1178 return ERROR_FAIL;
1179 }
1180 }
1181 i++;
1182 }
1183
1184 /* clear breakpoint */
1185 arm11_sc7_clear_vbw(arm11);
1186
1187 /* save state */
1188 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1189
1190 /* restore default state */
1191 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1192
1193 }
1194
1195 // target->state = TARGET_HALTED;
1196 target->debug_reason = DBG_REASON_SINGLESTEP;
1197
1198 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1199
1200 return ERROR_OK;
1201 }
1202
1203 /* target reset control */
1204 int arm11_assert_reset(struct target_s *target)
1205 {
1206 FNC_INFO;
1207
1208 #if 0
1209 /* assert reset lines */
1210 /* resets only the DBGTAP, not the ARM */
1211
1212 jtag_add_reset(1, 0);
1213 jtag_add_sleep(5000);
1214
1215 arm11_common_t * arm11 = target->arch_info;
1216 arm11->trst_active = true;
1217 #endif
1218
1219 if (target->reset_halt)
1220 {
1221 CHECK_RETVAL(target_halt(target));
1222 }
1223
1224 return ERROR_OK;
1225 }
1226
1227 int arm11_deassert_reset(struct target_s *target)
1228 {
1229 FNC_INFO;
1230
1231 #if 0
1232 LOG_DEBUG("target->state: %s",
1233 target_state_name(target));
1234
1235
1236 /* deassert reset lines */
1237 jtag_add_reset(0, 0);
1238
1239 arm11_common_t * arm11 = target->arch_info;
1240 arm11->trst_active = false;
1241
1242 if (arm11->halt_requested)
1243 return arm11_halt(target);
1244 #endif
1245
1246 return ERROR_OK;
1247 }
1248
1249 int arm11_soft_reset_halt(struct target_s *target)
1250 {
1251 FNC_INFO_NOTIMPLEMENTED;
1252
1253 return ERROR_OK;
1254 }
1255
1256 /* target register access for gdb */
1257 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1258 {
1259 FNC_INFO;
1260
1261 arm11_common_t * arm11 = target->arch_info;
1262
1263 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1264 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1265
1266 for (size_t i = 16; i < 24; i++)
1267 {
1268 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1269 }
1270
1271 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1272
1273 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1274 {
1275 if (arm11_reg_defs[i].gdb_num == -1)
1276 continue;
1277
1278 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1279 }
1280
1281 return ERROR_OK;
1282 }
1283
1284 /* target memory access
1285 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1286 * count: number of items of <size>
1287 */
1288 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1289 {
1290 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1291 int retval;
1292
1293 FNC_INFO;
1294
1295 if (target->state != TARGET_HALTED)
1296 {
1297 LOG_WARNING("target was not halted");
1298 return ERROR_TARGET_NOT_HALTED;
1299 }
1300
1301 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1302
1303 arm11_common_t * arm11 = target->arch_info;
1304
1305 retval = arm11_run_instr_data_prepare(arm11);
1306 if (retval != ERROR_OK)
1307 return retval;
1308
1309 /* MRC p14,0,r0,c0,c5,0 */
1310 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1311 if (retval != ERROR_OK)
1312 return retval;
1313
1314 switch (size)
1315 {
1316 case 1:
1317 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1318 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1319
1320 for (size_t i = 0; i < count; i++)
1321 {
1322 /* ldrb r1, [r0], #1 */
1323 /* ldrb r1, [r0] */
1324 arm11_run_instr_no_data1(arm11,
1325 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1326
1327 uint32_t res;
1328 /* MCR p14,0,R1,c0,c5,0 */
1329 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1330
1331 *buffer++ = res;
1332 }
1333
1334 break;
1335
1336 case 2:
1337 {
1338 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1339
1340 for (size_t i = 0; i < count; i++)
1341 {
1342 /* ldrh r1, [r0], #2 */
1343 arm11_run_instr_no_data1(arm11,
1344 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1345
1346 uint32_t res;
1347
1348 /* MCR p14,0,R1,c0,c5,0 */
1349 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1350
1351 uint16_t svalue = res;
1352 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1353 }
1354
1355 break;
1356 }
1357
1358 case 4:
1359 {
1360 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1361 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1362 uint32_t *words = (uint32_t *)buffer;
1363
1364 /* LDC p14,c5,[R0],#4 */
1365 /* LDC p14,c5,[R0] */
1366 arm11_run_instr_data_from_core(arm11, instr, words, count);
1367 break;
1368 }
1369 }
1370
1371 return arm11_run_instr_data_finish(arm11);
1372 }
1373
1374 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1375 {
1376 int retval;
1377 FNC_INFO;
1378
1379 if (target->state != TARGET_HALTED)
1380 {
1381 LOG_WARNING("target was not halted");
1382 return ERROR_TARGET_NOT_HALTED;
1383 }
1384
1385 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1386
1387 arm11_common_t * arm11 = target->arch_info;
1388
1389 arm11_run_instr_data_prepare(arm11);
1390
1391 /* MRC p14,0,r0,c0,c5,0 */
1392 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1393 if (retval != ERROR_OK)
1394 return retval;
1395
1396 switch (size)
1397 {
1398 case 1:
1399 {
1400 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1401
1402 for (size_t i = 0; i < count; i++)
1403 {
1404 /* MRC p14,0,r1,c0,c5,0 */
1405 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1406 if (retval != ERROR_OK)
1407 return retval;
1408
1409 /* strb r1, [r0], #1 */
1410 /* strb r1, [r0] */
1411 retval = arm11_run_instr_no_data1(arm11,
1412 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1413 if (retval != ERROR_OK)
1414 return retval;
1415 }
1416
1417 break;
1418 }
1419
1420 case 2:
1421 {
1422 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1423
1424 for (size_t i = 0; i < count; i++)
1425 {
1426 uint16_t value;
1427 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1428
1429 /* MRC p14,0,r1,c0,c5,0 */
1430 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1431 if (retval != ERROR_OK)
1432 return retval;
1433
1434 /* strh r1, [r0], #2 */
1435 /* strh r1, [r0] */
1436 retval = arm11_run_instr_no_data1(arm11,
1437 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1438 if (retval != ERROR_OK)
1439 return retval;
1440 }
1441
1442 break;
1443 }
1444
1445 case 4: {
1446 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1447
1448 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1449 uint32_t *words = (uint32_t*)buffer;
1450
1451 if (!arm11_config_memwrite_burst)
1452 {
1453 /* STC p14,c5,[R0],#4 */
1454 /* STC p14,c5,[R0]*/
1455 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1456 if (retval != ERROR_OK)
1457 return retval;
1458 }
1459 else
1460 {
1461 /* STC p14,c5,[R0],#4 */
1462 /* STC p14,c5,[R0]*/
1463 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1464 if (retval != ERROR_OK)
1465 return retval;
1466 }
1467
1468 break;
1469 }
1470 }
1471
1472 /* r0 verification */
1473 if (!arm11_config_memrw_no_increment)
1474 {
1475 uint32_t r0;
1476
1477 /* MCR p14,0,R0,c0,c5,0 */
1478 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1479 if (retval != ERROR_OK)
1480 return retval;
1481
1482 if (address + size * count != r0)
1483 {
1484 LOG_ERROR("Data transfer failed. Expected end "
1485 "address 0x%08x, got 0x%08x",
1486 (unsigned) (address + size * count),
1487 (unsigned) r0);
1488
1489 if (arm11_config_memwrite_burst)
1490 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1491
1492 if (arm11_config_memwrite_error_fatal)
1493 return ERROR_FAIL;
1494 }
1495 }
1496
1497 return arm11_run_instr_data_finish(arm11);
1498 }
1499
1500
1501 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1502 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1503 {
1504 FNC_INFO;
1505
1506 if (target->state != TARGET_HALTED)
1507 {
1508 LOG_WARNING("target was not halted");
1509 return ERROR_TARGET_NOT_HALTED;
1510 }
1511
1512 return arm11_write_memory(target, address, 4, count, buffer);
1513 }
1514
1515 /* here we have nothing target specific to contribute, so we fail and then the
1516 * fallback code will read data from the target and calculate the CRC on the
1517 * host.
1518 */
1519 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1520 {
1521 return ERROR_FAIL;
1522 }
1523
1524 /* target break-/watchpoint control
1525 * rw: 0 = write, 1 = read, 2 = access
1526 */
1527 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1528 {
1529 FNC_INFO;
1530
1531 arm11_common_t * arm11 = target->arch_info;
1532
1533 #if 0
1534 if (breakpoint->type == BKPT_SOFT)
1535 {
1536 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1537 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1538 }
1539 #endif
1540
1541 if (!arm11->free_brps)
1542 {
1543 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1544 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1545 }
1546
1547 if (breakpoint->length != 4)
1548 {
1549 LOG_DEBUG("only breakpoints of four bytes length supported");
1550 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1551 }
1552
1553 arm11->free_brps--;
1554
1555 return ERROR_OK;
1556 }
1557
1558 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1559 {
1560 FNC_INFO;
1561
1562 arm11_common_t * arm11 = target->arch_info;
1563
1564 arm11->free_brps++;
1565
1566 return ERROR_OK;
1567 }
1568
1569 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1570 {
1571 FNC_INFO_NOTIMPLEMENTED;
1572
1573 return ERROR_OK;
1574 }
1575
1576 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1577 {
1578 FNC_INFO_NOTIMPLEMENTED;
1579
1580 return ERROR_OK;
1581 }
1582
1583 // HACKHACKHACK - FIXME mode/state
1584 /* target algorithm support */
1585 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1586 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1587 int timeout_ms, void *arch_info)
1588 {
1589 arm11_common_t *arm11 = target->arch_info;
1590 // enum armv4_5_state core_state = arm11->core_state;
1591 // enum armv4_5_mode core_mode = arm11->core_mode;
1592 uint32_t context[16];
1593 uint32_t cpsr;
1594 int exit_breakpoint_size = 0;
1595 int retval = ERROR_OK;
1596 LOG_DEBUG("Running algorithm");
1597
1598
1599 if (target->state != TARGET_HALTED)
1600 {
1601 LOG_WARNING("target not halted");
1602 return ERROR_TARGET_NOT_HALTED;
1603 }
1604
1605 // FIXME
1606 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1607 // return ERROR_FAIL;
1608
1609 // Save regs
1610 for (size_t i = 0; i < 16; i++)
1611 {
1612 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1613 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1614 }
1615
1616 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1617 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1618
1619 for (int i = 0; i < num_mem_params; i++)
1620 {
1621 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1622 }
1623
1624 // Set register parameters
1625 for (int i = 0; i < num_reg_params; i++)
1626 {
1627 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1628 if (!reg)
1629 {
1630 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1631 exit(-1);
1632 }
1633
1634 if (reg->size != reg_params[i].size)
1635 {
1636 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1637 exit(-1);
1638 }
1639 arm11_set_reg(reg,reg_params[i].value);
1640 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1641 }
1642
1643 exit_breakpoint_size = 4;
1644
1645 /* arm11->core_state = arm11_algorithm_info->core_state;
1646 if (arm11->core_state == ARMV4_5_STATE_ARM)
1647 exit_breakpoint_size = 4;
1648 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1649 exit_breakpoint_size = 2;
1650 else
1651 {
1652 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1653 exit(-1);
1654 }
1655 */
1656
1657
1658 /* arm11 at this point only supports ARM not THUMB mode
1659 however if this test needs to be reactivated the current state can be read back
1660 from CPSR */
1661 #if 0
1662 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1663 {
1664 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1665 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1666 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1667 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1668 }
1669 #endif
1670
1671 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1672 {
1673 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1674 retval = ERROR_TARGET_FAILURE;
1675 goto restore;
1676 }
1677
1678 // no debug, otherwise breakpoint is not set
1679 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1680
1681 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1682
1683 if (target->state != TARGET_HALTED)
1684 {
1685 CHECK_RETVAL(target_halt(target));
1686
1687 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1688
1689 retval = ERROR_TARGET_TIMEOUT;
1690
1691 goto del_breakpoint;
1692 }
1693
1694 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1695 {
1696 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1697 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1698 retval = ERROR_TARGET_TIMEOUT;
1699 goto del_breakpoint;
1700 }
1701
1702 for (int i = 0; i < num_mem_params; i++)
1703 {
1704 if (mem_params[i].direction != PARAM_OUT)
1705 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1706 }
1707
1708 for (int i = 0; i < num_reg_params; i++)
1709 {
1710 if (reg_params[i].direction != PARAM_OUT)
1711 {
1712 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1713 if (!reg)
1714 {
1715 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1716 exit(-1);
1717 }
1718
1719 if (reg->size != reg_params[i].size)
1720 {
1721 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1722 exit(-1);
1723 }
1724
1725 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1726 }
1727 }
1728
1729 del_breakpoint:
1730 breakpoint_remove(target, exit_point);
1731
1732 restore:
1733 // Restore context
1734 for (size_t i = 0; i < 16; i++)
1735 {
1736 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1737 arm11->reg_list[i].name, context[i]);
1738 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1739 }
1740 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1741 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1742
1743 // arm11->core_state = core_state;
1744 // arm11->core_mode = core_mode;
1745
1746 return retval;
1747 }
1748
1749 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1750 {
1751 FNC_INFO;
1752
1753 NEW(arm11_common_t, arm11, 1);
1754
1755 arm11->target = target;
1756
1757 if (target->tap == NULL)
1758 return ERROR_FAIL;
1759
1760 if (target->tap->ir_length != 5)
1761 {
1762 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1763 return ERROR_COMMAND_SYNTAX_ERROR;
1764 }
1765
1766 target->arch_info = arm11;
1767
1768 return ERROR_OK;
1769 }
1770
1771 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1772 {
1773 /* Initialize anything we can set up without talking to the target */
1774 return arm11_build_reg_cache(target);
1775 }
1776
1777 /* talk to the target and set things up */
1778 int arm11_examine(struct target_s *target)
1779 {
1780 FNC_INFO;
1781
1782 arm11_common_t * arm11 = target->arch_info;
1783
1784 /* check IDCODE */
1785
1786 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1787
1788 scan_field_t idcode_field;
1789
1790 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1791
1792 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1793
1794 /* check DIDR */
1795
1796 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1797
1798 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1799
1800 scan_field_t chain0_fields[2];
1801
1802 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1803 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1804
1805 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1806
1807 CHECK_RETVAL(jtag_execute_queue());
1808
1809 switch (arm11->device_id & 0x0FFFF000)
1810 {
1811 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1812 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1813 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1814 default:
1815 {
1816 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1817 return ERROR_FAIL;
1818 }
1819 }
1820
1821 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1822
1823 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1824 arm11->debug_version != ARM11_DEBUG_V61)
1825 {
1826 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1827 return ERROR_FAIL;
1828 }
1829
1830 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1831 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1832
1833 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1834 arm11->free_brps = arm11->brp;
1835 arm11->free_wrps = arm11->wrp;
1836
1837 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1838 arm11->device_id,
1839 (int)(arm11->implementor),
1840 arm11->didr);
1841
1842 /* as a side-effect this reads DSCR and thus
1843 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1844 * as suggested by the spec.
1845 */
1846
1847 arm11_check_init(arm11, NULL);
1848
1849 target_set_examined(target);
1850
1851 return ERROR_OK;
1852 }
1853
1854 int arm11_quit(void)
1855 {
1856 FNC_INFO_NOTIMPLEMENTED;
1857
1858 return ERROR_OK;
1859 }
1860
1861 /** Load a register that is marked !valid in the register cache */
1862 int arm11_get_reg(reg_t *reg)
1863 {
1864 FNC_INFO;
1865
1866 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1867
1868 if (target->state != TARGET_HALTED)
1869 {
1870 LOG_WARNING("target was not halted");
1871 return ERROR_TARGET_NOT_HALTED;
1872 }
1873
1874 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1875
1876 #if 0
1877 arm11_common_t *arm11 = target->arch_info;
1878 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1879 #endif
1880
1881 return ERROR_OK;
1882 }
1883
1884 /** Change a value in the register cache */
1885 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1886 {
1887 FNC_INFO;
1888
1889 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1890 arm11_common_t *arm11 = target->arch_info;
1891 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1892
1893 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1894 reg->valid = 1;
1895 reg->dirty = 1;
1896
1897 return ERROR_OK;
1898 }
1899
1900 int arm11_build_reg_cache(target_t *target)
1901 {
1902 arm11_common_t *arm11 = target->arch_info;
1903
1904 NEW(reg_cache_t, cache, 1);
1905 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1906 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1907
1908 if (arm11_regs_arch_type == -1)
1909 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1910
1911 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1912 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1913
1914 arm11->reg_list = reg_list;
1915
1916 /* Build the process context cache */
1917 cache->name = "arm11 registers";
1918 cache->next = NULL;
1919 cache->reg_list = reg_list;
1920 cache->num_regs = ARM11_REGCACHE_COUNT;
1921
1922 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1923 (*cache_p) = cache;
1924
1925 arm11->core_cache = cache;
1926 // armv7m->process_context = cache;
1927
1928 size_t i;
1929
1930 /* Not very elegant assertion */
1931 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1932 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1933 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1934 {
1935 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1936 exit(-1);
1937 }
1938
1939 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1940 {
1941 reg_t * r = reg_list + i;
1942 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1943 arm11_reg_state_t * rs = arm11_reg_states + i;
1944
1945 r->name = rd->name;
1946 r->size = 32;
1947 r->value = (uint8_t *)(arm11->reg_values + i);
1948 r->dirty = 0;
1949 r->valid = 0;
1950 r->bitfield_desc = NULL;
1951 r->num_bitfields = 0;
1952 r->arch_type = arm11_regs_arch_type;
1953 r->arch_info = rs;
1954
1955 rs->def_index = i;
1956 rs->target = target;
1957 }
1958
1959 return ERROR_OK;
1960 }
1961
1962 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1963 {
1964 if (argc == 0)
1965 {
1966 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1967 return ERROR_OK;
1968 }
1969
1970 if (argc != 1)
1971 return ERROR_COMMAND_SYNTAX_ERROR;
1972
1973 switch (args[0][0])
1974 {
1975 case '0': /* 0 */
1976 case 'f': /* false */
1977 case 'F':
1978 case 'd': /* disable */
1979 case 'D':
1980 *var = false;
1981 break;
1982
1983 case '1': /* 1 */
1984 case 't': /* true */
1985 case 'T':
1986 case 'e': /* enable */
1987 case 'E':
1988 *var = true;
1989 break;
1990 }
1991
1992 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1993
1994 return ERROR_OK;
1995 }
1996
1997 #define BOOL_WRAPPER(name, print_name) \
1998 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1999 { \
2000 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
2001 }
2002
2003 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2004 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2005 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
2006 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2007 BOOL_WRAPPER(hardware_step, "hardware single step")
2008
2009 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2010 {
2011 if (argc == 1)
2012 {
2013 arm11_vcr = strtoul(args[0], NULL, 0);
2014 }
2015 else if (argc != 0)
2016 {
2017 return ERROR_COMMAND_SYNTAX_ERROR;
2018 }
2019
2020 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2021 return ERROR_OK;
2022 }
2023
2024 const uint32_t arm11_coproc_instruction_limits[] =
2025 {
2026 15, /* coprocessor */
2027 7, /* opcode 1 */
2028 15, /* CRn */
2029 15, /* CRm */
2030 7, /* opcode 2 */
2031 0xFFFFFFFF, /* value */
2032 };
2033
2034 arm11_common_t * arm11_find_target(const char * arg)
2035 {
2036 jtag_tap_t * tap;
2037 target_t * t;
2038
2039 tap = jtag_tap_by_string(arg);
2040
2041 if (!tap)
2042 return 0;
2043
2044 for (t = all_targets; t; t = t->next)
2045 {
2046 if (t->tap != tap)
2047 continue;
2048
2049 /* if (t->type == arm11_target) */
2050 if (0 == strcmp(target_get_name(t), "arm11"))
2051 return t->arch_info;
2052 }
2053
2054 return 0;
2055 }
2056
2057 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2058 {
2059 int retval;
2060
2061 if (argc != (read ? 6 : 7))
2062 {
2063 LOG_ERROR("Invalid number of arguments.");
2064 return ERROR_COMMAND_SYNTAX_ERROR;
2065 }
2066
2067 arm11_common_t * arm11 = arm11_find_target(args[0]);
2068
2069 if (!arm11)
2070 {
2071 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2072 return ERROR_COMMAND_SYNTAX_ERROR;
2073 }
2074
2075 if (arm11->target->state != TARGET_HALTED)
2076 {
2077 LOG_WARNING("target was not halted");
2078 return ERROR_TARGET_NOT_HALTED;
2079 }
2080
2081 uint32_t values[6];
2082
2083 for (size_t i = 0; i < (read ? 5 : 6); i++)
2084 {
2085 values[i] = strtoul(args[i + 1], NULL, 0);
2086
2087 if (values[i] > arm11_coproc_instruction_limits[i])
2088 {
2089 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2090 (long)(i + 2),
2091 arm11_coproc_instruction_limits[i]);
2092 return ERROR_COMMAND_SYNTAX_ERROR;
2093 }
2094 }
2095
2096 uint32_t instr = 0xEE000010 |
2097 (values[0] << 8) |
2098 (values[1] << 21) |
2099 (values[2] << 16) |
2100 (values[3] << 0) |
2101 (values[4] << 5);
2102
2103 if (read)
2104 instr |= 0x00100000;
2105
2106 retval = arm11_run_instr_data_prepare(arm11);
2107 if (retval != ERROR_OK)
2108 return retval;
2109
2110 if (read)
2111 {
2112 uint32_t result;
2113 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2114 if (retval != ERROR_OK)
2115 return retval;
2116
2117 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2118 (int)(values[0]),
2119 (int)(values[1]),
2120 (int)(values[2]),
2121 (int)(values[3]),
2122 (int)(values[4]), result, result);
2123 }
2124 else
2125 {
2126 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2127 if (retval != ERROR_OK)
2128 return retval;
2129
2130 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2131 (int)(values[0]), (int)(values[1]),
2132 values[5],
2133 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2134 }
2135
2136 return arm11_run_instr_data_finish(arm11);
2137 }
2138
2139 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2140 {
2141 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2142 }
2143
2144 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2145 {
2146 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2147 }
2148
2149 int arm11_register_commands(struct command_context_s *cmd_ctx)
2150 {
2151 FNC_INFO;
2152
2153 command_t *top_cmd, *mw_cmd;
2154
2155 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2156 NULL, COMMAND_ANY, NULL);
2157
2158 /* "hardware_step" is only here to check if the default
2159 * simulate + breakpoint implementation is broken.
2160 * TEMPORARY! NOT DOCUMENTED!
2161 */
2162 register_command(cmd_ctx, top_cmd, "hardware_step",
2163 arm11_handle_bool_hardware_step, COMMAND_ANY,
2164 "DEBUG ONLY - Hardware single stepping"
2165 " (default: disabled)");
2166
2167 register_command(cmd_ctx, top_cmd, "mcr",
2168 arm11_handle_mcr, COMMAND_ANY,
2169 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2170
2171 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2172 NULL, COMMAND_ANY, NULL);
2173 register_command(cmd_ctx, mw_cmd, "burst",
2174 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2175 "Enable/Disable non-standard but fast burst mode"
2176 " (default: enabled)");
2177 register_command(cmd_ctx, mw_cmd, "error_fatal",
2178 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2179 "Terminate program if transfer error was found"
2180 " (default: enabled)");
2181
2182 register_command(cmd_ctx, top_cmd, "mrc",
2183 arm11_handle_mrc, COMMAND_ANY,
2184 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2185 register_command(cmd_ctx, top_cmd, "no_increment",
2186 arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
2187 "Don't increment address on multi-read/-write"
2188 " (default: disabled)");
2189 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2190 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2191 "Enable interrupts while stepping"
2192 " (default: disabled)");
2193 register_command(cmd_ctx, top_cmd, "vcr",
2194 arm11_handle_vcr, COMMAND_ANY,
2195 "Control (Interrupt) Vector Catch Register");
2196
2197 return ERROR_OK;
2198 }
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