1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
37 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #define FNC_INFO LOG_DEBUG("-")
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
49 #define FNC_INFO_NOTIMPLEMENTED
52 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
);
54 bool arm11_config_memwrite_burst
= true;
55 bool arm11_config_memwrite_error_fatal
= true;
56 uint32_t arm11_vcr
= 0;
57 bool arm11_config_step_irq_enable
= false;
58 bool arm11_config_hardware_step
= false;
60 #define ARM11_HANDLER(x) \
63 target_type_t arm11_target
=
68 ARM11_HANDLER(arch_state
),
70 ARM11_HANDLER(target_request_data
),
73 ARM11_HANDLER(resume
),
76 ARM11_HANDLER(assert_reset
),
77 ARM11_HANDLER(deassert_reset
),
78 ARM11_HANDLER(soft_reset_halt
),
80 ARM11_HANDLER(get_gdb_reg_list
),
82 ARM11_HANDLER(read_memory
),
83 ARM11_HANDLER(write_memory
),
85 ARM11_HANDLER(bulk_write_memory
),
87 ARM11_HANDLER(checksum_memory
),
89 ARM11_HANDLER(add_breakpoint
),
90 ARM11_HANDLER(remove_breakpoint
),
91 ARM11_HANDLER(add_watchpoint
),
92 ARM11_HANDLER(remove_watchpoint
),
94 ARM11_HANDLER(run_algorithm
),
96 ARM11_HANDLER(register_commands
),
97 ARM11_HANDLER(target_create
),
98 ARM11_HANDLER(init_target
),
99 ARM11_HANDLER(examine
),
103 int arm11_regs_arch_type
= -1;
121 ARM11_REGISTER_SPSR_FIQ
,
122 ARM11_REGISTER_SPSR_SVC
,
123 ARM11_REGISTER_SPSR_ABT
,
124 ARM11_REGISTER_SPSR_IRQ
,
125 ARM11_REGISTER_SPSR_UND
,
126 ARM11_REGISTER_SPSR_MON
,
135 typedef struct arm11_reg_defs_s
140 enum arm11_regtype type
;
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs
[] =
146 {"r0", 0, 0, ARM11_REGISTER_CORE
},
147 {"r1", 1, 1, ARM11_REGISTER_CORE
},
148 {"r2", 2, 2, ARM11_REGISTER_CORE
},
149 {"r3", 3, 3, ARM11_REGISTER_CORE
},
150 {"r4", 4, 4, ARM11_REGISTER_CORE
},
151 {"r5", 5, 5, ARM11_REGISTER_CORE
},
152 {"r6", 6, 6, ARM11_REGISTER_CORE
},
153 {"r7", 7, 7, ARM11_REGISTER_CORE
},
154 {"r8", 8, 8, ARM11_REGISTER_CORE
},
155 {"r9", 9, 9, ARM11_REGISTER_CORE
},
156 {"r10", 10, 10, ARM11_REGISTER_CORE
},
157 {"r11", 11, 11, ARM11_REGISTER_CORE
},
158 {"r12", 12, 12, ARM11_REGISTER_CORE
},
159 {"sp", 13, 13, ARM11_REGISTER_CORE
},
160 {"lr", 14, 14, ARM11_REGISTER_CORE
},
161 {"pc", 15, 15, ARM11_REGISTER_CORE
},
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX
},
165 {"f1", 1, 17, ARM11_REGISTER_FX
},
166 {"f2", 2, 18, ARM11_REGISTER_FX
},
167 {"f3", 3, 19, ARM11_REGISTER_FX
},
168 {"f4", 4, 20, ARM11_REGISTER_FX
},
169 {"f5", 5, 21, ARM11_REGISTER_FX
},
170 {"f6", 6, 22, ARM11_REGISTER_FX
},
171 {"f7", 7, 23, ARM11_REGISTER_FX
},
172 {"fps", 0, 24, ARM11_REGISTER_FPS
},
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
199 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
215 enum arm11_regcache_ids
218 ARM11_RC_RX
= ARM11_RC_R0
,
233 ARM11_RC_SP
= ARM11_RC_R13
,
235 ARM11_RC_LR
= ARM11_RC_R14
,
237 ARM11_RC_PC
= ARM11_RC_R15
,
239 #if ARM11_REGCACHE_FREGS
241 ARM11_RC_FX
= ARM11_RC_F0
,
254 #if ARM11_REGCACHE_MODEREGS
292 #define ARM11_GDB_REGISTER_COUNT 26
294 uint8_t arm11_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
296 reg_t arm11_gdb_dummy_fp_reg
=
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
301 uint8_t arm11_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
303 reg_t arm11_gdb_dummy_fps_reg
=
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
310 /** Check and if necessary take control of the system
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
317 int arm11_check_init(arm11_common_t
* arm11
, uint32_t * dscr
)
321 uint32_t dscr_local_tmp_copy
;
325 dscr
= &dscr_local_tmp_copy
;
327 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
330 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
332 LOG_DEBUG("Bringing target into debug mode");
334 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
335 arm11_write_DSCR(arm11
, *dscr
);
337 /* add further reset initialization here */
339 arm11
->simulate_reset_on_next_halt
= true;
341 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
349 arm11
->target
->state
= TARGET_HALTED
;
350 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
354 arm11
->target
->state
= TARGET_RUNNING
;
355 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
358 arm11_sc7_clear_vbw(arm11
);
367 (arm11->reg_values[ARM11_RC_##x])
369 /** Save processor state.
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
375 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
)
380 for (size_t i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
382 arm11
->reg_list
[i
].valid
= 1;
383 arm11
->reg_list
[i
].dirty
= 0;
387 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
391 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
393 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
395 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
397 scan_field_t chain5_fields
[3];
399 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
400 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
401 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
403 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
407 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
415 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
417 /* this executes JTAG queue: */
419 arm11_write_DSCR(arm11
, new_dscr
);
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
426 /** \todo TODO: Test drain write buffer. */
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
437 uint32_t dscr
= arm11_read_DSCR(arm11
);
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
441 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
443 arm11_run_instr_no_data1(arm11
, 0xe320f000);
445 dscr
= arm11_read_DSCR(arm11
);
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
454 retval
= arm11_run_instr_data_prepare(arm11
);
455 if (retval
!= ERROR_OK
)
460 /** \todo TODO: handle other mode registers */
462 for (size_t i
= 0; i
< 15; i
++)
464 /* MCR p14,0,R?,c0,c5,0 */
465 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
466 if (retval
!= ERROR_OK
)
472 /* check rDTRfull in DSCR */
474 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
476 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
477 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
478 if (retval
!= ERROR_OK
)
483 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
488 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
489 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
490 if (retval
!= ERROR_OK
)
495 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
496 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
497 if (retval
!= ERROR_OK
)
500 /* adjust PC depending on ARM state */
502 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
504 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
506 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
508 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
512 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
515 if (arm11
->simulate_reset_on_next_halt
)
517 arm11
->simulate_reset_on_next_halt
= false;
519 LOG_DEBUG("Reset c1 Control Register");
521 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
523 /* MCR p15,0,R0,c1,c0,0 */
524 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
525 if (retval
!= ERROR_OK
)
530 retval
= arm11_run_instr_data_finish(arm11
);
531 if (retval
!= ERROR_OK
)
534 arm11_dump_reg_changes(arm11
);
539 void arm11_dump_reg_changes(arm11_common_t
* arm11
)
542 if (!(debug_level
>= LOG_LVL_DEBUG
))
547 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
549 if (!arm11
->reg_list
[i
].valid
)
551 if (arm11
->reg_history
[i
].valid
)
552 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
556 if (arm11
->reg_history
[i
].valid
)
558 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
559 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
563 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
569 /** Restore processor state
571 * This is called in preparation for the RESTART function.
574 int arm11_leave_debug_state(arm11_common_t
* arm11
)
579 retval
= arm11_run_instr_data_prepare(arm11
);
580 if (retval
!= ERROR_OK
)
583 /** \todo TODO: handle other mode registers */
585 /* restore R1 - R14 */
587 for (size_t i
= 1; i
< 15; i
++)
589 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
592 /* MRC p14,0,r?,c0,c5,0 */
593 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
595 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
598 retval
= arm11_run_instr_data_finish(arm11
);
599 if (retval
!= ERROR_OK
)
602 /* spec says clear wDTR and rDTR; we assume they are clear as
603 otherwise our programming would be sloppy */
607 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
609 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
612 The wDTR/rDTR two registers that are used to send/receive data to/from
613 the core in tandem with corresponding instruction codes that are
614 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
615 registers hold data that was written by one side (CPU or JTAG) and not
616 read out by the other side.
618 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
623 retval
= arm11_run_instr_data_prepare(arm11
);
624 if (retval
!= ERROR_OK
)
627 /* restore original wDTR */
629 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
631 /* MCR p14,0,R0,c0,c5,0 */
632 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
633 if (retval
!= ERROR_OK
)
640 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
641 if (retval
!= ERROR_OK
)
648 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
649 if (retval
!= ERROR_OK
)
655 /* MRC p14,0,r0,c0,c5,0 */
656 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
658 retval
= arm11_run_instr_data_finish(arm11
);
659 if (retval
!= ERROR_OK
)
664 arm11_write_DSCR(arm11
, R(DSCR
));
668 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
670 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
672 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
674 scan_field_t chain5_fields
[3];
676 uint8_t Ready
= 0; /* ignored */
677 uint8_t Valid
= 0; /* ignored */
679 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
680 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
681 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
683 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
686 arm11_record_register_history(arm11
);
691 void arm11_record_register_history(arm11_common_t
* arm11
)
693 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
695 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
696 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
698 arm11
->reg_list
[i
].valid
= 0;
699 arm11
->reg_list
[i
].dirty
= 0;
704 /* poll current target status */
705 int arm11_poll(struct target_s
*target
)
710 arm11_common_t
* arm11
= target
->arch_info
;
714 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
716 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
718 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
720 if (dscr
& ARM11_DSCR_CORE_HALTED
)
722 if (target
->state
!= TARGET_HALTED
)
724 enum target_state old_state
= target
->state
;
726 LOG_DEBUG("enter TARGET_HALTED");
727 target
->state
= TARGET_HALTED
;
728 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
729 retval
= arm11_on_enter_debug_state(arm11
);
730 if (retval
!= ERROR_OK
)
733 target_call_event_callbacks(target
,
734 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
739 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
741 LOG_DEBUG("enter TARGET_RUNNING");
742 target
->state
= TARGET_RUNNING
;
743 target
->debug_reason
= DBG_REASON_NOTHALTED
;
749 /* architecture specific status reply */
750 int arm11_arch_state(struct target_s
*target
)
752 arm11_common_t
* arm11
= target
->arch_info
;
754 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
755 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
762 /* target request support */
763 int arm11_target_request_data(struct target_s
*target
, uint32_t size
, uint8_t *buffer
)
765 FNC_INFO_NOTIMPLEMENTED
;
770 /* target execution control */
771 int arm11_halt(struct target_s
*target
)
775 arm11_common_t
* arm11
= target
->arch_info
;
777 LOG_DEBUG("target->state: %s",
778 target_state_name(target
));
780 if (target
->state
== TARGET_UNKNOWN
)
782 arm11
->simulate_reset_on_next_halt
= true;
785 if (target
->state
== TARGET_HALTED
)
787 LOG_DEBUG("target was already halted");
791 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
793 CHECK_RETVAL(jtag_execute_queue());
800 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
802 if (dscr
& ARM11_DSCR_CORE_HALTED
)
813 if ((timeval_ms()-then
) > 1000)
815 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
822 arm11_on_enter_debug_state(arm11
);
824 enum target_state old_state
= target
->state
;
826 target
->state
= TARGET_HALTED
;
827 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
830 target_call_event_callbacks(target
,
831 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
836 int arm11_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
840 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
841 // current, address, handle_breakpoints, debug_execution);
843 arm11_common_t
* arm11
= target
->arch_info
;
845 LOG_DEBUG("target->state: %s",
846 target_state_name(target
));
849 if (target
->state
!= TARGET_HALTED
)
851 LOG_ERROR("Target not halted");
852 return ERROR_TARGET_NOT_HALTED
;
858 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
860 /* clear breakpoints/watchpoints and VCR*/
861 arm11_sc7_clear_vbw(arm11
);
863 /* Set up breakpoints */
864 if (!debug_execution
)
866 /* check if one matches PC and step over it if necessary */
870 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
872 if (bp
->address
== R(PC
))
874 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
875 arm11_step(target
, 1, 0, 0);
880 /* set all breakpoints */
884 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
886 arm11_sc7_action_t brp
[2];
889 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
890 brp
[0].value
= bp
->address
;
892 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
893 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
895 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
897 LOG_DEBUG("Add BP " ZU
" at %08" PRIx32
"", brp_num
, bp
->address
);
902 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
905 arm11_leave_debug_state(arm11
);
907 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
909 CHECK_RETVAL(jtag_execute_queue());
916 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
918 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
920 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
931 if ((timeval_ms()-then
) > 1000)
933 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
940 if (!debug_execution
)
942 target
->state
= TARGET_RUNNING
;
943 target
->debug_reason
= DBG_REASON_NOTHALTED
;
945 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
949 target
->state
= TARGET_DEBUG_RUNNING
;
950 target
->debug_reason
= DBG_REASON_NOTHALTED
;
952 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
959 static int armv4_5_to_arm11(int reg
)
966 return ARM11_RC_CPSR
;
968 /* FIX!!! handle thumb better! */
969 return ARM11_RC_CPSR
;
971 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
977 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
979 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
981 reg
=armv4_5_to_arm11(reg
);
983 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
986 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
, int reg
, uint32_t value
)
988 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
990 reg
=armv4_5_to_arm11(reg
);
992 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
995 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
, int pos
, int bits
)
997 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
999 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
1002 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
1004 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1006 /* FIX!!!! we should implement thumb for arm11 */
1007 return ARMV4_5_STATE_ARM
;
1010 static void arm11_sim_set_state(struct arm_sim_interface
*sim
, enum armv4_5_state mode
)
1012 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1014 /* FIX!!!! we should implement thumb for arm11 */
1015 LOG_ERROR("Not implemetned!");
1019 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
1021 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1023 /* FIX!!!! we should implement something that returns the current mode here!!! */
1024 return ARMV4_5_MODE_USR
;
1027 static int arm11_simulate_step(target_t
*target
, uint32_t *dry_run_pc
)
1029 struct arm_sim_interface sim
;
1031 sim
.user_data
=target
->arch_info
;
1032 sim
.get_reg
=&arm11_sim_get_reg
;
1033 sim
.set_reg
=&arm11_sim_set_reg
;
1034 sim
.get_reg_mode
=&arm11_sim_get_reg
;
1035 sim
.set_reg_mode
=&arm11_sim_set_reg
;
1036 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
1037 sim
.get_mode
=&arm11_sim_get_mode
;
1038 sim
.get_state
=&arm11_sim_get_state
;
1039 sim
.set_state
=&arm11_sim_set_state
;
1041 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
1045 int arm11_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1049 LOG_DEBUG("target->state: %s",
1050 target_state_name(target
));
1052 if (target
->state
!= TARGET_HALTED
)
1054 LOG_WARNING("target was not halted");
1055 return ERROR_TARGET_NOT_HALTED
;
1058 arm11_common_t
* arm11
= target
->arch_info
;
1063 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
1066 /** \todo TODO: Thumb not supported here */
1068 uint32_t next_instruction
;
1070 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
1072 /* skip over BKPT */
1073 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
1076 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1077 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1078 LOG_DEBUG("Skipping BKPT");
1080 /* skip over Wait for interrupt / Standby */
1081 /* mcr 15, 0, r?, cr7, cr0, {4} */
1082 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
1085 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1086 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1087 LOG_DEBUG("Skipping WFI");
1089 /* ignore B to self */
1090 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
1092 LOG_DEBUG("Not stepping jump to self");
1096 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1099 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1100 * the VCR might be something worth looking into. */
1103 /* Set up breakpoint for stepping */
1105 arm11_sc7_action_t brp
[2];
1108 brp
[0].address
= ARM11_SC7_BVR0
;
1110 brp
[1].address
= ARM11_SC7_BCR0
;
1112 if (arm11_config_hardware_step
)
1114 /* hardware single stepping be used if possible or is it better to
1115 * always use the same code path? Hardware single stepping is not supported
1118 brp
[0].value
= R(PC
);
1119 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1122 /* sets a breakpoint on the next PC(calculated by simulation),
1126 retval
= arm11_simulate_step(target
, &next_pc
);
1127 if (retval
!= ERROR_OK
)
1130 brp
[0].value
= next_pc
;
1131 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1134 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, asizeof(brp
)));
1139 if (arm11_config_step_irq_enable
)
1140 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1142 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1145 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
1147 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1149 CHECK_RETVAL(jtag_execute_queue());
1157 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1159 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1161 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1162 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1168 then
= timeval_ms();
1172 if ((timeval_ms()-then
) > 1000)
1174 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1181 /* clear breakpoint */
1182 arm11_sc7_clear_vbw(arm11
);
1185 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1187 /* restore default state */
1188 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1192 // target->state = TARGET_HALTED;
1193 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1195 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1200 int arm11_assert_reset(target_t
*target
)
1204 /* FIX! we really should assert srst here, but
1205 * how do we reset the target into the halted state?
1207 * Also arm11 behaves "funny" when srst is asserted
1208 * (as of writing the rules are not understood).
1210 if (target
->reset_halt
)
1212 CHECK_RETVAL(target_halt(target
));
1218 int arm11_deassert_reset(target_t
*target
)
1223 int arm11_soft_reset_halt(struct target_s
*target
)
1225 FNC_INFO_NOTIMPLEMENTED
;
1230 /* target register access for gdb */
1231 int arm11_get_gdb_reg_list(struct target_s
*target
, struct reg_s
**reg_list
[], int *reg_list_size
)
1235 arm11_common_t
* arm11
= target
->arch_info
;
1237 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1238 *reg_list
= malloc(sizeof(reg_t
*) * ARM11_GDB_REGISTER_COUNT
);
1240 for (size_t i
= 16; i
< 24; i
++)
1242 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1245 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1247 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1249 if (arm11_reg_defs
[i
].gdb_num
== -1)
1252 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1258 /* target memory access
1259 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1260 * count: number of items of <size>
1262 * arm11_config_memrw_no_increment - in the future we may want to be able
1263 * to read/write a range of data to a "port". a "port" is an action on
1264 * read memory address for some peripheral.
1266 int arm11_read_memory_inner(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1267 bool arm11_config_memrw_no_increment
)
1269 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1274 if (target
->state
!= TARGET_HALTED
)
1276 LOG_WARNING("target was not halted");
1277 return ERROR_TARGET_NOT_HALTED
;
1280 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1282 arm11_common_t
* arm11
= target
->arch_info
;
1284 retval
= arm11_run_instr_data_prepare(arm11
);
1285 if (retval
!= ERROR_OK
)
1288 /* MRC p14,0,r0,c0,c5,0 */
1289 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1290 if (retval
!= ERROR_OK
)
1296 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1297 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1299 for (size_t i
= 0; i
< count
; i
++)
1301 /* ldrb r1, [r0], #1 */
1303 arm11_run_instr_no_data1(arm11
,
1304 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1307 /* MCR p14,0,R1,c0,c5,0 */
1308 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1317 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1319 for (size_t i
= 0; i
< count
; i
++)
1321 /* ldrh r1, [r0], #2 */
1322 arm11_run_instr_no_data1(arm11
,
1323 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1327 /* MCR p14,0,R1,c0,c5,0 */
1328 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1330 uint16_t svalue
= res
;
1331 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1339 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1340 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1341 uint32_t *words
= (uint32_t *)buffer
;
1343 /* LDC p14,c5,[R0],#4 */
1344 /* LDC p14,c5,[R0] */
1345 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1350 return arm11_run_instr_data_finish(arm11
);
1353 int arm11_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1355 return arm11_read_memory_inner(target
, address
, size
, count
, buffer
, false);
1359 * arm11_config_memrw_no_increment - in the future we may want to be able
1360 * to read/write a range of data to a "port". a "port" is an action on
1361 * read memory address for some peripheral.
1363 int arm11_write_memory_inner(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1364 bool arm11_config_memrw_no_increment
)
1369 if (target
->state
!= TARGET_HALTED
)
1371 LOG_WARNING("target was not halted");
1372 return ERROR_TARGET_NOT_HALTED
;
1375 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1377 arm11_common_t
* arm11
= target
->arch_info
;
1379 retval
= arm11_run_instr_data_prepare(arm11
);
1380 if (retval
!= ERROR_OK
)
1383 /* MRC p14,0,r0,c0,c5,0 */
1384 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1385 if (retval
!= ERROR_OK
)
1388 /* burst writes are not used for single words as those may well be
1389 * reset init script writes.
1391 * The other advantage is that as burst writes are default, we'll
1392 * now exercise both burst and non-burst code paths with the
1393 * default settings, increasing code coverage.
1395 bool burst
= arm11_config_memwrite_burst
&& (count
> 1);
1401 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1403 for (size_t i
= 0; i
< count
; i
++)
1405 /* MRC p14,0,r1,c0,c5,0 */
1406 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1407 if (retval
!= ERROR_OK
)
1410 /* strb r1, [r0], #1 */
1412 retval
= arm11_run_instr_no_data1(arm11
,
1413 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1414 if (retval
!= ERROR_OK
)
1423 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1425 for (size_t i
= 0; i
< count
; i
++)
1428 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1430 /* MRC p14,0,r1,c0,c5,0 */
1431 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1432 if (retval
!= ERROR_OK
)
1435 /* strh r1, [r0], #2 */
1437 retval
= arm11_run_instr_no_data1(arm11
,
1438 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1439 if (retval
!= ERROR_OK
)
1447 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1449 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1450 uint32_t *words
= (uint32_t*)buffer
;
1454 /* STC p14,c5,[R0],#4 */
1455 /* STC p14,c5,[R0]*/
1456 retval
= arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1457 if (retval
!= ERROR_OK
)
1462 /* STC p14,c5,[R0],#4 */
1463 /* STC p14,c5,[R0]*/
1464 retval
= arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1465 if (retval
!= ERROR_OK
)
1473 /* r0 verification */
1474 if (!arm11_config_memrw_no_increment
)
1478 /* MCR p14,0,R0,c0,c5,0 */
1479 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1480 if (retval
!= ERROR_OK
)
1483 if (address
+ size
* count
!= r0
)
1485 LOG_ERROR("Data transfer failed. Expected end "
1486 "address 0x%08x, got 0x%08x",
1487 (unsigned) (address
+ size
* count
),
1491 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1493 if (arm11_config_memwrite_error_fatal
)
1498 return arm11_run_instr_data_finish(arm11
);
1501 int arm11_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1503 return arm11_write_memory_inner(target
, address
, size
, count
, buffer
, false);
1506 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1507 int arm11_bulk_write_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
1511 if (target
->state
!= TARGET_HALTED
)
1513 LOG_WARNING("target was not halted");
1514 return ERROR_TARGET_NOT_HALTED
;
1517 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1520 /* here we have nothing target specific to contribute, so we fail and then the
1521 * fallback code will read data from the target and calculate the CRC on the
1524 int arm11_checksum_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
)
1529 /* target break-/watchpoint control
1530 * rw: 0 = write, 1 = read, 2 = access
1532 int arm11_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1536 arm11_common_t
* arm11
= target
->arch_info
;
1539 if (breakpoint
->type
== BKPT_SOFT
)
1541 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1542 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1546 if (!arm11
->free_brps
)
1548 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1549 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1552 if (breakpoint
->length
!= 4)
1554 LOG_DEBUG("only breakpoints of four bytes length supported");
1555 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1563 int arm11_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1567 arm11_common_t
* arm11
= target
->arch_info
;
1574 int arm11_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1576 FNC_INFO_NOTIMPLEMENTED
;
1581 int arm11_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1583 FNC_INFO_NOTIMPLEMENTED
;
1588 // HACKHACKHACK - FIXME mode/state
1589 /* target algorithm support */
1590 int arm11_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
,
1591 int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
,
1592 int timeout_ms
, void *arch_info
)
1594 arm11_common_t
*arm11
= target
->arch_info
;
1595 // enum armv4_5_state core_state = arm11->core_state;
1596 // enum armv4_5_mode core_mode = arm11->core_mode;
1597 uint32_t context
[16];
1599 int exit_breakpoint_size
= 0;
1600 int retval
= ERROR_OK
;
1601 LOG_DEBUG("Running algorithm");
1604 if (target
->state
!= TARGET_HALTED
)
1606 LOG_WARNING("target not halted");
1607 return ERROR_TARGET_NOT_HALTED
;
1611 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1612 // return ERROR_FAIL;
1615 for (size_t i
= 0; i
< 16; i
++)
1617 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1618 LOG_DEBUG("Save %zi: 0x%" PRIx32
"",i
,context
[i
]);
1621 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1622 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1624 for (int i
= 0; i
< num_mem_params
; i
++)
1626 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1629 // Set register parameters
1630 for (int i
= 0; i
< num_reg_params
; i
++)
1632 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1635 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1639 if (reg
->size
!= reg_params
[i
].size
)
1641 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1644 arm11_set_reg(reg
,reg_params
[i
].value
);
1645 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1648 exit_breakpoint_size
= 4;
1650 /* arm11->core_state = arm11_algorithm_info->core_state;
1651 if (arm11->core_state == ARMV4_5_STATE_ARM)
1652 exit_breakpoint_size = 4;
1653 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1654 exit_breakpoint_size = 2;
1657 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1663 /* arm11 at this point only supports ARM not THUMB mode
1664 however if this test needs to be reactivated the current state can be read back
1667 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1669 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1670 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1671 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1672 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1676 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1678 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1679 retval
= ERROR_TARGET_FAILURE
;
1683 // no debug, otherwise breakpoint is not set
1684 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1686 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1688 if (target
->state
!= TARGET_HALTED
)
1690 CHECK_RETVAL(target_halt(target
));
1692 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1694 retval
= ERROR_TARGET_TIMEOUT
;
1696 goto del_breakpoint
;
1699 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1701 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1702 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1703 retval
= ERROR_TARGET_TIMEOUT
;
1704 goto del_breakpoint
;
1707 for (int i
= 0; i
< num_mem_params
; i
++)
1709 if (mem_params
[i
].direction
!= PARAM_OUT
)
1710 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1713 for (int i
= 0; i
< num_reg_params
; i
++)
1715 if (reg_params
[i
].direction
!= PARAM_OUT
)
1717 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1720 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1724 if (reg
->size
!= reg_params
[i
].size
)
1726 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1730 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1735 breakpoint_remove(target
, exit_point
);
1739 for (size_t i
= 0; i
< 16; i
++)
1741 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1742 arm11
->reg_list
[i
].name
, context
[i
]);
1743 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1745 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1746 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1748 // arm11->core_state = core_state;
1749 // arm11->core_mode = core_mode;
1754 int arm11_target_create(struct target_s
*target
, Jim_Interp
*interp
)
1758 NEW(arm11_common_t
, arm11
, 1);
1760 arm11
->target
= target
;
1762 if (target
->tap
== NULL
)
1765 if (target
->tap
->ir_length
!= 5)
1767 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1768 return ERROR_COMMAND_SYNTAX_ERROR
;
1771 target
->arch_info
= arm11
;
1776 int arm11_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
1778 /* Initialize anything we can set up without talking to the target */
1779 return arm11_build_reg_cache(target
);
1782 /* talk to the target and set things up */
1783 int arm11_examine(struct target_s
*target
)
1789 arm11_common_t
* arm11
= target
->arch_info
;
1793 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1795 scan_field_t idcode_field
;
1797 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1799 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1803 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1805 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1807 scan_field_t chain0_fields
[2];
1809 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1810 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1812 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_IDLE
);
1814 CHECK_RETVAL(jtag_execute_queue());
1816 switch (arm11
->device_id
& 0x0FFFF000)
1818 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1819 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1820 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1823 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1828 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1830 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1831 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1833 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1837 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1838 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1840 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1841 arm11
->free_brps
= arm11
->brp
;
1842 arm11
->free_wrps
= arm11
->wrp
;
1844 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1846 (int)(arm11
->implementor
),
1849 /* as a side-effect this reads DSCR and thus
1850 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1851 * as suggested by the spec.
1854 retval
= arm11_check_init(arm11
, NULL
);
1855 if (retval
!= ERROR_OK
)
1858 target_set_examined(target
);
1863 int arm11_quit(void)
1865 FNC_INFO_NOTIMPLEMENTED
;
1870 /** Load a register that is marked !valid in the register cache */
1871 int arm11_get_reg(reg_t
*reg
)
1875 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1877 if (target
->state
!= TARGET_HALTED
)
1879 LOG_WARNING("target was not halted");
1880 return ERROR_TARGET_NOT_HALTED
;
1883 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1886 arm11_common_t
*arm11
= target
->arch_info
;
1887 const arm11_reg_defs_t
* arm11_reg_info
= arm11_reg_defs
+ ((arm11_reg_state_t
*)reg
->arch_info
)->def_index
;
1893 /** Change a value in the register cache */
1894 int arm11_set_reg(reg_t
*reg
, uint8_t *buf
)
1898 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1899 arm11_common_t
*arm11
= target
->arch_info
;
1900 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1902 arm11
->reg_values
[((arm11_reg_state_t
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1909 int arm11_build_reg_cache(target_t
*target
)
1911 arm11_common_t
*arm11
= target
->arch_info
;
1913 NEW(reg_cache_t
, cache
, 1);
1914 NEW(reg_t
, reg_list
, ARM11_REGCACHE_COUNT
);
1915 NEW(arm11_reg_state_t
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1917 if (arm11_regs_arch_type
== -1)
1918 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1920 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1921 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1923 arm11
->reg_list
= reg_list
;
1925 /* Build the process context cache */
1926 cache
->name
= "arm11 registers";
1928 cache
->reg_list
= reg_list
;
1929 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1931 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1934 arm11
->core_cache
= cache
;
1935 // armv7m->process_context = cache;
1939 /* Not very elegant assertion */
1940 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1941 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1942 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1944 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1948 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1950 reg_t
* r
= reg_list
+ i
;
1951 const arm11_reg_defs_t
* rd
= arm11_reg_defs
+ i
;
1952 arm11_reg_state_t
* rs
= arm11_reg_states
+ i
;
1956 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1959 r
->bitfield_desc
= NULL
;
1960 r
->num_bitfields
= 0;
1961 r
->arch_type
= arm11_regs_arch_type
;
1965 rs
->target
= target
;
1971 int arm11_handle_bool(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool * var
, char * name
)
1975 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
1980 return ERROR_COMMAND_SYNTAX_ERROR
;
1985 case 'f': /* false */
1987 case 'd': /* disable */
1993 case 't': /* true */
1995 case 'e': /* enable */
2001 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
2006 #define BOOL_WRAPPER(name, print_name) \
2007 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
2009 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
2012 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
2013 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
2014 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
2015 BOOL_WRAPPER(hardware_step
, "hardware single step")
2017 int arm11_handle_vcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2021 arm11_vcr
= strtoul(args
[0], NULL
, 0);
2025 return ERROR_COMMAND_SYNTAX_ERROR
;
2028 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
2032 const uint32_t arm11_coproc_instruction_limits
[] =
2034 15, /* coprocessor */
2039 0xFFFFFFFF, /* value */
2042 arm11_common_t
* arm11_find_target(const char * arg
)
2047 tap
= jtag_tap_by_string(arg
);
2052 for (t
= all_targets
; t
; t
= t
->next
)
2057 /* if (t->type == arm11_target) */
2058 if (0 == strcmp(target_get_name(t
), "arm11"))
2059 return t
->arch_info
;
2065 int arm11_handle_mrc_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool read
)
2069 if (argc
!= (read
? 6 : 7))
2071 LOG_ERROR("Invalid number of arguments.");
2072 return ERROR_COMMAND_SYNTAX_ERROR
;
2075 arm11_common_t
* arm11
= arm11_find_target(args
[0]);
2079 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2080 return ERROR_COMMAND_SYNTAX_ERROR
;
2083 if (arm11
->target
->state
!= TARGET_HALTED
)
2085 LOG_WARNING("target was not halted");
2086 return ERROR_TARGET_NOT_HALTED
;
2091 for (size_t i
= 0; i
< (read
? 5 : 6); i
++)
2093 values
[i
] = strtoul(args
[i
+ 1], NULL
, 0);
2095 if (values
[i
] > arm11_coproc_instruction_limits
[i
])
2097 LOG_ERROR("Parameter %ld out of bounds (%" PRId32
" max).",
2099 arm11_coproc_instruction_limits
[i
]);
2100 return ERROR_COMMAND_SYNTAX_ERROR
;
2104 uint32_t instr
= 0xEE000010 |
2112 instr
|= 0x00100000;
2114 retval
= arm11_run_instr_data_prepare(arm11
);
2115 if (retval
!= ERROR_OK
)
2121 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, instr
, &result
);
2122 if (retval
!= ERROR_OK
)
2125 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32
" (%" PRId32
")",
2130 (int)(values
[4]), result
, result
);
2134 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, instr
, values
[5]);
2135 if (retval
!= ERROR_OK
)
2138 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32
"), c%d, c%d, %d",
2139 (int)(values
[0]), (int)(values
[1]),
2141 (int)(values
[2]), (int)(values
[3]), (int)(values
[4]));
2144 return arm11_run_instr_data_finish(arm11
);
2147 int arm11_handle_mrc(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2149 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, true);
2152 int arm11_handle_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2154 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, false);
2157 int arm11_register_commands(struct command_context_s
*cmd_ctx
)
2161 command_t
*top_cmd
, *mw_cmd
;
2163 top_cmd
= register_command(cmd_ctx
, NULL
, "arm11",
2164 NULL
, COMMAND_ANY
, NULL
);
2166 /* "hardware_step" is only here to check if the default
2167 * simulate + breakpoint implementation is broken.
2168 * TEMPORARY! NOT DOCUMENTED!
2170 register_command(cmd_ctx
, top_cmd
, "hardware_step",
2171 arm11_handle_bool_hardware_step
, COMMAND_ANY
,
2172 "DEBUG ONLY - Hardware single stepping"
2173 " (default: disabled)");
2175 register_command(cmd_ctx
, top_cmd
, "mcr",
2176 arm11_handle_mcr
, COMMAND_ANY
,
2177 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2179 mw_cmd
= register_command(cmd_ctx
, top_cmd
, "memwrite",
2180 NULL
, COMMAND_ANY
, NULL
);
2181 register_command(cmd_ctx
, mw_cmd
, "burst",
2182 arm11_handle_bool_memwrite_burst
, COMMAND_ANY
,
2183 "Enable/Disable non-standard but fast burst mode"
2184 " (default: enabled)");
2185 register_command(cmd_ctx
, mw_cmd
, "error_fatal",
2186 arm11_handle_bool_memwrite_error_fatal
, COMMAND_ANY
,
2187 "Terminate program if transfer error was found"
2188 " (default: enabled)");
2190 register_command(cmd_ctx
, top_cmd
, "mrc",
2191 arm11_handle_mrc
, COMMAND_ANY
,
2192 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2193 register_command(cmd_ctx
, top_cmd
, "step_irq_enable",
2194 arm11_handle_bool_step_irq_enable
, COMMAND_ANY
,
2195 "Enable interrupts while stepping"
2196 " (default: disabled)");
2197 register_command(cmd_ctx
, top_cmd
, "vcr",
2198 arm11_handle_vcr
, COMMAND_ANY
,
2199 "Control (Interrupt) Vector Catch Register");
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