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Michael Bruck:
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm11.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35
36 #if 0
37 #define FNC_INFO DEBUG("-")
38 #else
39 #define FNC_INFO
40 #endif
41
42 #if 1
43 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
44 #else
45 #define FNC_INFO_NOTIMPLEMENTED
46 #endif
47
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
49
50
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 u32 arm11_vcr = 0;
54
55
56 #define ARM11_HANDLER(x) \
57 .x = arm11_##x
58
59 target_type_t arm11_target =
60 {
61 .name = "arm11",
62
63 ARM11_HANDLER(poll),
64 ARM11_HANDLER(arch_state),
65
66 ARM11_HANDLER(target_request_data),
67
68 ARM11_HANDLER(halt),
69 ARM11_HANDLER(resume),
70 ARM11_HANDLER(step),
71
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75 ARM11_HANDLER(prepare_reset_halt),
76
77 ARM11_HANDLER(get_gdb_reg_list),
78
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
81
82 ARM11_HANDLER(bulk_write_memory),
83
84 ARM11_HANDLER(checksum_memory),
85
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
90
91 ARM11_HANDLER(run_algorithm),
92
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_command),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(quit),
97 };
98
99 int arm11_regs_arch_type = -1;
100
101
102 enum arm11_regtype
103 {
104 ARM11_REGISTER_CORE,
105 ARM11_REGISTER_CPSR,
106
107 ARM11_REGISTER_FX,
108 ARM11_REGISTER_FPS,
109
110 ARM11_REGISTER_FIQ,
111 ARM11_REGISTER_SVC,
112 ARM11_REGISTER_ABT,
113 ARM11_REGISTER_IRQ,
114 ARM11_REGISTER_UND,
115 ARM11_REGISTER_MON,
116
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
123
124 /* debug regs */
125 ARM11_REGISTER_DSCR,
126 ARM11_REGISTER_WDTR,
127 ARM11_REGISTER_RDTR,
128 };
129
130
131 typedef struct arm11_reg_defs_s
132 {
133 char * name;
134 u32 num;
135 int gdb_num;
136 enum arm11_regtype type;
137 } arm11_reg_defs_t;
138
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
141 {
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
158
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
169 #endif
170
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
172
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
182
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
186
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
190
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
194
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
198
199 /* ARM1176 only */
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
203 #endif
204
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
209 };
210
211 enum arm11_regcache_ids
212 {
213 ARM11_RC_R0,
214 ARM11_RC_RX = ARM11_RC_R0,
215
216 ARM11_RC_R1,
217 ARM11_RC_R2,
218 ARM11_RC_R3,
219 ARM11_RC_R4,
220 ARM11_RC_R5,
221 ARM11_RC_R6,
222 ARM11_RC_R7,
223 ARM11_RC_R8,
224 ARM11_RC_R9,
225 ARM11_RC_R10,
226 ARM11_RC_R11,
227 ARM11_RC_R12,
228 ARM11_RC_R13,
229 ARM11_RC_SP = ARM11_RC_R13,
230 ARM11_RC_R14,
231 ARM11_RC_LR = ARM11_RC_R14,
232 ARM11_RC_R15,
233 ARM11_RC_PC = ARM11_RC_R15,
234
235 #if ARM11_REGCACHE_FREGS
236 ARM11_RC_F0,
237 ARM11_RC_FX = ARM11_RC_F0,
238 ARM11_RC_F1,
239 ARM11_RC_F2,
240 ARM11_RC_F3,
241 ARM11_RC_F4,
242 ARM11_RC_F5,
243 ARM11_RC_F6,
244 ARM11_RC_F7,
245 ARM11_RC_FPS,
246 #endif
247
248 ARM11_RC_CPSR,
249
250 #if ARM11_REGCACHE_MODEREGS
251 ARM11_RC_R8_FIQ,
252 ARM11_RC_R9_FIQ,
253 ARM11_RC_R10_FIQ,
254 ARM11_RC_R11_FIQ,
255 ARM11_RC_R12_FIQ,
256 ARM11_RC_R13_FIQ,
257 ARM11_RC_R14_FIQ,
258 ARM11_RC_SPSR_FIQ,
259
260 ARM11_RC_R13_SVC,
261 ARM11_RC_R14_SVC,
262 ARM11_RC_SPSR_SVC,
263
264 ARM11_RC_R13_ABT,
265 ARM11_RC_R14_ABT,
266 ARM11_RC_SPSR_ABT,
267
268 ARM11_RC_R13_IRQ,
269 ARM11_RC_R14_IRQ,
270 ARM11_RC_SPSR_IRQ,
271
272 ARM11_RC_R13_UND,
273 ARM11_RC_R14_UND,
274 ARM11_RC_SPSR_UND,
275
276 ARM11_RC_R13_MON,
277 ARM11_RC_R14_MON,
278 ARM11_RC_SPSR_MON,
279 #endif
280
281 ARM11_RC_DSCR,
282 ARM11_RC_WDTR,
283 ARM11_RC_RDTR,
284
285 ARM11_RC_MAX,
286 };
287
288 #define ARM11_GDB_REGISTER_COUNT 26
289
290 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
291
292 reg_t arm11_gdb_dummy_fp_reg =
293 {
294 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
295 };
296
297 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
298
299 reg_t arm11_gdb_dummy_fps_reg =
300 {
301 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
302 };
303
304
305
306 /** Check and if necessary take control of the system
307 *
308 * \param arm11 Target state variable.
309 * \param dscr If the current DSCR content is
310 * available a pointer to a word holding the
311 * DSCR can be passed. Otherwise use NULL.
312 */
313 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
314 {
315 FNC_INFO;
316
317 u32 dscr_local_tmp_copy;
318
319 if (!dscr)
320 {
321 dscr = &dscr_local_tmp_copy;
322 *dscr = arm11_read_DSCR(arm11);
323 }
324
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
326 {
327 DEBUG("Bringing target into debug mode");
328
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
331
332 /* add further reset initialization here */
333
334 arm11->simulate_reset_on_next_halt = true;
335
336 if (*dscr & ARM11_DSCR_CORE_HALTED)
337 {
338 /** \todo TODO: this needs further scrutiny because
339 * arm11_on_enter_debug_state() never gets properly called
340 */
341
342 arm11->target->state = TARGET_HALTED;
343 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
344 }
345 else
346 {
347 arm11->target->state = TARGET_RUNNING;
348 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
349 }
350
351 arm11_sc7_clear_vbw(arm11);
352 }
353 }
354
355
356
357 #define R(x) \
358 (arm11->reg_values[ARM11_RC_##x])
359
360 /** Save processor state.
361 *
362 * This is called when the HALT instruction has succeeded
363 * or on other occasions that stop the processor.
364 *
365 */
366 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
367 {
368 FNC_INFO;
369
370 {size_t i;
371 for(i = 0; i < asizeof(arm11->reg_values); i++)
372 {
373 arm11->reg_list[i].valid = 1;
374 arm11->reg_list[i].dirty = 0;
375 }}
376
377 /* Save DSCR */
378
379 R(DSCR) = arm11_read_DSCR(arm11);
380
381 /* Save wDTR */
382
383 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
384 {
385 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
386
387 arm11_add_IR(arm11, ARM11_INTEST, -1);
388
389 scan_field_t chain5_fields[3];
390
391 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
394
395 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
396 }
397 else
398 {
399 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
400 }
401
402
403 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
404 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
405 ARM1136 seems to require this to issue ITR's as well */
406
407 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
408
409 /* this executes JTAG queue: */
410
411 arm11_write_DSCR(arm11, new_dscr);
412
413
414 /* From the spec:
415 Before executing any instruction in debug state you have to drain the write buffer.
416 This ensures that no imprecise Data Aborts can return at a later point:*/
417
418 /** \todo TODO: Test drain write buffer. */
419
420 #if 0
421 while (1)
422 {
423 /* MRC p14,0,R0,c5,c10,0 */
424 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
425
426 /* mcr 15, 0, r0, cr7, cr10, {4} */
427 arm11_run_instr_no_data1(arm11, 0xee070f9a);
428
429 u32 dscr = arm11_read_DSCR(arm11);
430
431 DEBUG("DRAIN, DSCR %08x", dscr);
432
433 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
434 {
435 arm11_run_instr_no_data1(arm11, 0xe320f000);
436
437 dscr = arm11_read_DSCR(arm11);
438
439 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
440
441 break;
442 }
443 }
444 #endif
445
446
447 arm11_run_instr_data_prepare(arm11);
448
449 /* save r0 - r14 */
450
451
452 /** \todo TODO: handle other mode registers */
453
454 {size_t i;
455 for (i = 0; i < 15; i++)
456 {
457 /* MCR p14,0,R?,c0,c5,0 */
458 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
459 }}
460
461
462 /* save rDTR */
463
464 /* check rDTRfull in DSCR */
465
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
467 {
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
470 }
471 else
472 {
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
474 }
475
476 /* save CPSR */
477
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
480
481 /* save PC */
482
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
485
486 /* adjust PC depending on ARM state */
487
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
489 {
490 arm11->reg_values[ARM11_RC_PC] -= 0;
491 }
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 4;
495 }
496 else /* ARM state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 8;
499 }
500
501 if (arm11->simulate_reset_on_next_halt)
502 {
503 arm11->simulate_reset_on_next_halt = false;
504
505 DEBUG("Reset c1 Control Register");
506
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
508
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
511
512 }
513
514
515
516 arm11_run_instr_data_finish(arm11);
517
518 arm11_dump_reg_changes(arm11);
519 }
520
521 void arm11_dump_reg_changes(arm11_common_t * arm11)
522 {
523 {size_t i;
524 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
525 {
526 if (!arm11->reg_list[i].valid)
527 {
528 if (arm11->reg_history[i].valid)
529 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
530 }
531 else
532 {
533 if (arm11->reg_history[i].valid)
534 {
535 if (arm11->reg_history[i].value != arm11->reg_values[i])
536 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
537 }
538 else
539 {
540 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
541 }
542 }
543 }}
544 }
545
546
547 /** Restore processor state
548 *
549 * This is called in preparation for the RESTART function.
550 *
551 */
552 void arm11_leave_debug_state(arm11_common_t * arm11)
553 {
554 FNC_INFO;
555
556 arm11_run_instr_data_prepare(arm11);
557
558 /** \todo TODO: handle other mode registers */
559
560 /* restore R1 - R14 */
561 {size_t i;
562 for (i = 1; i < 15; i++)
563 {
564 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
565 continue;
566
567 /* MRC p14,0,r?,c0,c5,0 */
568 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
569
570 // DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
571 }}
572
573 arm11_run_instr_data_finish(arm11);
574
575
576 /* spec says clear wDTR and rDTR; we assume they are clear as
577 otherwise our programming would be sloppy */
578
579 {
580 u32 DSCR = arm11_read_DSCR(arm11);
581
582 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
583 {
584 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
585 }
586 }
587
588 arm11_run_instr_data_prepare(arm11);
589
590 /* restore original wDTR */
591
592 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
593 {
594 /* MCR p14,0,R0,c0,c5,0 */
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
596 }
597
598 /* restore CPSR */
599
600 /* MSR CPSR,R0*/
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
602
603
604 /* restore PC */
605
606 /* MOV PC,R0 */
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
608
609
610 /* restore R0 */
611
612 /* MRC p14,0,r0,c0,c5,0 */
613 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
614
615 arm11_run_instr_data_finish(arm11);
616
617
618 /* restore DSCR */
619
620 arm11_write_DSCR(arm11, R(DSCR));
621
622
623 /* restore rDTR */
624
625 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
626 {
627 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
628
629 arm11_add_IR(arm11, ARM11_EXTEST, -1);
630
631 scan_field_t chain5_fields[3];
632
633 u8 Ready = 0; /* ignored */
634 u8 Valid = 0; /* ignored */
635
636 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
637 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
638 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
639
640 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
641 }
642
643 arm11_record_register_history(arm11);
644 }
645
646 void arm11_record_register_history(arm11_common_t * arm11)
647 {
648 {size_t i;
649 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
650 {
651 arm11->reg_history[i].value = arm11->reg_values[i];
652 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
653
654 arm11->reg_list[i].valid = 0;
655 arm11->reg_list[i].dirty = 0;
656 }}
657 }
658
659
660 /* poll current target status */
661 int arm11_poll(struct target_s *target)
662 {
663 FNC_INFO;
664
665 arm11_common_t * arm11 = target->arch_info;
666
667 if (arm11->trst_active)
668 return ERROR_OK;
669
670 u32 dscr = arm11_read_DSCR(arm11);
671
672 DEBUG("DSCR %08x", dscr);
673
674 arm11_check_init(arm11, &dscr);
675
676 if (dscr & ARM11_DSCR_CORE_HALTED)
677 {
678 if (target->state != TARGET_HALTED)
679 {
680 enum target_state old_state = target->state;
681
682 DEBUG("enter TARGET_HALTED");
683 target->state = TARGET_HALTED;
684 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
685 arm11_on_enter_debug_state(arm11);
686
687 target_call_event_callbacks(target,
688 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
689 }
690 }
691 else
692 {
693 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
694 {
695 DEBUG("enter TARGET_RUNNING");
696 target->state = TARGET_RUNNING;
697 target->debug_reason = DBG_REASON_NOTHALTED;
698 }
699 }
700
701 return ERROR_OK;
702 }
703 /* architecture specific status reply */
704 int arm11_arch_state(struct target_s *target)
705 {
706 FNC_INFO_NOTIMPLEMENTED;
707
708 return ERROR_OK;
709 }
710
711
712 /* target request support */
713 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
714 {
715 FNC_INFO_NOTIMPLEMENTED;
716
717 return ERROR_OK;
718 }
719
720
721
722 /* target execution control */
723 int arm11_halt(struct target_s *target)
724 {
725 FNC_INFO;
726
727 arm11_common_t * arm11 = target->arch_info;
728
729 DEBUG("target->state: %s", target_state_strings[target->state]);
730
731 if (target->state == TARGET_UNKNOWN)
732 {
733 arm11->simulate_reset_on_next_halt = true;
734 }
735
736 if (target->state == TARGET_HALTED)
737 {
738 WARNING("target was already halted");
739 return ERROR_TARGET_ALREADY_HALTED;
740 }
741
742 if (arm11->trst_active)
743 {
744 arm11->halt_requested = true;
745 return ERROR_OK;
746 }
747
748 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
749
750 jtag_execute_queue();
751
752 u32 dscr;
753
754 while (1)
755 {
756 dscr = arm11_read_DSCR(arm11);
757
758 if (dscr & ARM11_DSCR_CORE_HALTED)
759 break;
760 }
761
762 arm11_on_enter_debug_state(arm11);
763
764 enum target_state old_state = target->state;
765
766 target->state = TARGET_HALTED;
767 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
768
769 target_call_event_callbacks(target,
770 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
771
772 return ERROR_OK;
773 }
774
775
776 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
777 {
778 FNC_INFO;
779
780 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
781 // current, address, handle_breakpoints, debug_execution);
782
783 arm11_common_t * arm11 = target->arch_info;
784
785 DEBUG("target->state: %s", target_state_strings[target->state]);
786
787 if (target->state != TARGET_HALTED)
788 {
789 WARNING("target was not halted");
790 return ERROR_TARGET_NOT_HALTED;
791 }
792
793 if (!current)
794 R(PC) = address;
795
796 INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
797
798 /* clear breakpoints/watchpoints and VCR*/
799 arm11_sc7_clear_vbw(arm11);
800
801 /* Set up breakpoints */
802 if (!debug_execution)
803 {
804 /* check if one matches PC and step over it if necessary */
805
806 breakpoint_t * bp;
807
808 for (bp = target->breakpoints; bp; bp = bp->next)
809 {
810 if (bp->address == R(PC))
811 {
812 DEBUG("must step over %08x", bp->address);
813 arm11_step(target, 1, 0, 0);
814 break;
815 }
816 }
817
818 /* set all breakpoints */
819
820 size_t brp_num = 0;
821
822 for (bp = target->breakpoints; bp; bp = bp->next)
823 {
824 arm11_sc7_action_t brp[2];
825
826 brp[0].write = 1;
827 brp[0].address = ARM11_SC7_BVR0 + brp_num;
828 brp[0].value = bp->address;
829 brp[1].write = 1;
830 brp[1].address = ARM11_SC7_BCR0 + brp_num;
831 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
832
833 arm11_sc7_run(arm11, brp, asizeof(brp));
834
835 DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
836
837 brp_num++;
838 }
839
840 arm11_sc7_set_vcr(arm11, arm11_vcr);
841 }
842
843
844 arm11_leave_debug_state(arm11);
845
846 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
847
848 jtag_execute_queue();
849
850 while (1)
851 {
852 u32 dscr = arm11_read_DSCR(arm11);
853
854 DEBUG("DSCR %08x", dscr);
855
856 if (dscr & ARM11_DSCR_CORE_RESTARTED)
857 break;
858 }
859
860 if (!debug_execution)
861 {
862 target->state = TARGET_RUNNING;
863 target->debug_reason = DBG_REASON_NOTHALTED;
864 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
865 }
866 else
867 {
868 target->state = TARGET_DEBUG_RUNNING;
869 target->debug_reason = DBG_REASON_NOTHALTED;
870 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
871 }
872
873 return ERROR_OK;
874 }
875
876 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
877 {
878 FNC_INFO;
879
880 DEBUG("target->state: %s", target_state_strings[target->state]);
881
882 if (target->state != TARGET_HALTED)
883 {
884 WARNING("target was not halted");
885 return ERROR_TARGET_NOT_HALTED;
886 }
887
888 arm11_common_t * arm11 = target->arch_info;
889
890 if (!current)
891 R(PC) = address;
892
893 INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
894
895 /** \todo TODO: Thumb not supported here */
896
897 u32 next_instruction;
898
899 arm11_read_memory_word(arm11, R(PC), &next_instruction);
900
901 /* skip over BKPT */
902 if ((next_instruction & 0xFFF00070) == 0xe1200070)
903 {
904 R(PC) += 4;
905 arm11->reg_list[ARM11_RC_PC].valid = 1;
906 arm11->reg_list[ARM11_RC_PC].dirty = 0;
907 INFO("Skipping BKPT");
908 }
909 /* skip over Wait for interrupt / Standby */
910 /* mcr 15, 0, r?, cr7, cr0, {4} */
911 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
912 {
913 R(PC) += 4;
914 arm11->reg_list[ARM11_RC_PC].valid = 1;
915 arm11->reg_list[ARM11_RC_PC].dirty = 0;
916 INFO("Skipping WFI");
917 }
918 /* ignore B to self */
919 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
920 {
921 INFO("Not stepping jump to self");
922 }
923 else
924 {
925 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
926 * with this. */
927
928 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
929 * the VCR might be something worth looking into. */
930
931
932 /* Set up breakpoint for stepping */
933
934 arm11_sc7_action_t brp[2];
935
936 brp[0].write = 1;
937 brp[0].address = ARM11_SC7_BVR0;
938 brp[0].value = R(PC);
939 brp[1].write = 1;
940 brp[1].address = ARM11_SC7_BCR0;
941 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
942
943 arm11_sc7_run(arm11, brp, asizeof(brp));
944
945 /* resume */
946
947 arm11_leave_debug_state(arm11);
948
949 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
950
951 jtag_execute_queue();
952
953 /** \todo TODO: add a timeout */
954
955 /* wait for halt */
956
957 while (1)
958 {
959 u32 dscr = arm11_read_DSCR(arm11);
960
961 DEBUG("DSCR %08x", dscr);
962
963 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
964 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
965 break;
966 }
967
968 /* clear breakpoint */
969 arm11_sc7_clear_vbw(arm11);
970
971 /* save state */
972 arm11_on_enter_debug_state(arm11);
973 }
974
975 // target->state = TARGET_HALTED;
976 target->debug_reason = DBG_REASON_SINGLESTEP;
977
978 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
979
980 return ERROR_OK;
981 }
982
983
984 /* target reset control */
985 int arm11_assert_reset(struct target_s *target)
986 {
987 FNC_INFO;
988
989 #if 0
990 /* assert reset lines */
991 /* resets only the DBGTAP, not the ARM */
992
993 jtag_add_reset(1, 0);
994 jtag_add_sleep(5000);
995
996 arm11_common_t * arm11 = target->arch_info;
997 arm11->trst_active = true;
998 #endif
999
1000 return ERROR_OK;
1001 }
1002
1003 int arm11_deassert_reset(struct target_s *target)
1004 {
1005 FNC_INFO;
1006
1007 #if 0
1008 DEBUG("target->state: %s", target_state_strings[target->state]);
1009
1010 /* deassert reset lines */
1011 jtag_add_reset(0, 0);
1012
1013 arm11_common_t * arm11 = target->arch_info;
1014 arm11->trst_active = false;
1015
1016 if (arm11->halt_requested)
1017 return arm11_halt(target);
1018 #endif
1019
1020 return ERROR_OK;
1021 }
1022
1023 int arm11_soft_reset_halt(struct target_s *target)
1024 {
1025 FNC_INFO_NOTIMPLEMENTED;
1026
1027 return ERROR_OK;
1028 }
1029
1030 int arm11_prepare_reset_halt(struct target_s *target)
1031 {
1032 FNC_INFO_NOTIMPLEMENTED;
1033
1034 return ERROR_OK;
1035 }
1036
1037
1038 /* target register access for gdb */
1039 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1040 {
1041 FNC_INFO;
1042
1043 arm11_common_t * arm11 = target->arch_info;
1044
1045 if (target->state != TARGET_HALTED)
1046 {
1047 return ERROR_TARGET_NOT_HALTED;
1048 }
1049
1050 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1051 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1052
1053 {size_t i;
1054 for (i = 16; i < 24; i++)
1055 {
1056 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1057 }}
1058
1059 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1060
1061
1062 {size_t i;
1063 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1064 {
1065 if (arm11_reg_defs[i].gdb_num == -1)
1066 continue;
1067
1068 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1069 }}
1070
1071 return ERROR_OK;
1072 }
1073
1074
1075 /* target memory access
1076 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1077 * count: number of items of <size>
1078 */
1079 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1080 {
1081 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1082
1083 FNC_INFO;
1084
1085 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1086
1087 arm11_common_t * arm11 = target->arch_info;
1088
1089 arm11_run_instr_data_prepare(arm11);
1090
1091 /* MRC p14,0,r0,c0,c5,0 */
1092 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1093
1094 switch (size)
1095 {
1096 case 1:
1097 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1098 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1099
1100 {size_t i;
1101 for (i = 0; i < count; i++)
1102 {
1103 /* ldrb r1, [r0], #1 */
1104 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1105
1106 u32 res;
1107 /* MCR p14,0,R1,c0,c5,0 */
1108 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1109
1110 *buffer++ = res;
1111 }}
1112
1113 break;
1114
1115 case 2:
1116 {
1117 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1118
1119 u16 * buf16 = (u16*)buffer;
1120
1121 {size_t i;
1122 for (i = 0; i < count; i++)
1123 {
1124 /* ldrh r1, [r0], #2 */
1125 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1126
1127 u32 res;
1128
1129 /* MCR p14,0,R1,c0,c5,0 */
1130 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1131
1132 *buf16++ = res;
1133 }}
1134
1135 break;
1136 }
1137
1138 case 4:
1139
1140 /* LDC p14,c5,[R0],#4 */
1141 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1142 break;
1143 }
1144
1145 arm11_run_instr_data_finish(arm11);
1146
1147 return ERROR_OK;
1148 }
1149
1150 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1151 {
1152 FNC_INFO;
1153
1154 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1155
1156 arm11_common_t * arm11 = target->arch_info;
1157
1158 arm11_run_instr_data_prepare(arm11);
1159
1160 /* MRC p14,0,r0,c0,c5,0 */
1161 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1162
1163 switch (size)
1164 {
1165 case 1:
1166 {
1167 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1168
1169 {size_t i;
1170 for (i = 0; i < count; i++)
1171 {
1172 /* MRC p14,0,r1,c0,c5,0 */
1173 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1174
1175 /* strb r1, [r0], #1 */
1176 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1177 }}
1178
1179 break;
1180 }
1181
1182 case 2:
1183 {
1184 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1185
1186 u16 * buf16 = (u16*)buffer;
1187
1188 {size_t i;
1189 for (i = 0; i < count; i++)
1190 {
1191 /* MRC p14,0,r1,c0,c5,0 */
1192 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1193
1194 /* strh r1, [r0], #2 */
1195 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1196 }}
1197
1198 break;
1199 }
1200
1201 case 4:
1202 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1203
1204 if (!arm11_config_memwrite_burst)
1205 {
1206 /* STC p14,c5,[R0],#4 */
1207 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1208 }
1209 else
1210 {
1211 /* STC p14,c5,[R0],#4 */
1212 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1213 }
1214
1215 break;
1216 }
1217
1218 #if 1
1219 /* r0 verification */
1220 {
1221 u32 r0;
1222
1223 /* MCR p14,0,R0,c0,c5,0 */
1224 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1225
1226 if (address + size * count != r0)
1227 {
1228 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1229
1230 if (arm11_config_memwrite_burst)
1231 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1232
1233 if (arm11_config_memwrite_error_fatal)
1234 exit(-1);
1235 }
1236 }
1237 #endif
1238
1239
1240 arm11_run_instr_data_finish(arm11);
1241
1242
1243
1244
1245 return ERROR_OK;
1246 }
1247
1248
1249 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1250 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1251 {
1252 FNC_INFO;
1253
1254 return arm11_write_memory(target, address, 4, count, buffer);
1255 }
1256
1257
1258 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1259 {
1260 FNC_INFO_NOTIMPLEMENTED;
1261
1262 return ERROR_OK;
1263 }
1264
1265
1266 /* target break-/watchpoint control
1267 * rw: 0 = write, 1 = read, 2 = access
1268 */
1269 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1270 {
1271 FNC_INFO;
1272
1273 arm11_common_t * arm11 = target->arch_info;
1274
1275 #if 0
1276 if (breakpoint->type == BKPT_SOFT)
1277 {
1278 INFO("sw breakpoint requested, but software breakpoints not enabled");
1279 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1280 }
1281 #endif
1282
1283 if (!arm11->free_brps)
1284 {
1285 INFO("no breakpoint unit available for hardware breakpoint");
1286 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1287 }
1288
1289 if (breakpoint->length != 4)
1290 {
1291 INFO("only breakpoints of four bytes length supported");
1292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1293 }
1294
1295 arm11->free_brps--;
1296
1297 return ERROR_OK;
1298 }
1299
1300 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1301 {
1302 FNC_INFO;
1303
1304 arm11_common_t * arm11 = target->arch_info;
1305
1306 arm11->free_brps++;
1307
1308 return ERROR_OK;
1309 }
1310
1311 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1312 {
1313 FNC_INFO_NOTIMPLEMENTED;
1314
1315 return ERROR_OK;
1316 }
1317
1318 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1319 {
1320 FNC_INFO_NOTIMPLEMENTED;
1321
1322 return ERROR_OK;
1323 }
1324
1325
1326 /* target algorithm support */
1327 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1328 {
1329 FNC_INFO_NOTIMPLEMENTED;
1330
1331 return ERROR_OK;
1332 }
1333
1334 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1335 {
1336 FNC_INFO;
1337
1338 if (argc < 4)
1339 {
1340 ERROR("'target arm11' 4th argument <jtag chain pos>");
1341 exit(-1);
1342 }
1343
1344 int chain_pos = strtoul(args[3], NULL, 0);
1345
1346 NEW(arm11_common_t, arm11, 1);
1347
1348 arm11->target = target;
1349
1350 /* prepare JTAG information for the new target */
1351 arm11->jtag_info.chain_pos = chain_pos;
1352 arm11->jtag_info.scann_size = 5;
1353
1354 arm_jtag_setup_connection(&arm11->jtag_info);
1355
1356 jtag_device_t *device = jtag_get_device(chain_pos);
1357
1358 if (device->ir_length != 5)
1359 {
1360 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1361 exit(-1);
1362 }
1363
1364 target->arch_info = arm11;
1365
1366 return ERROR_OK;
1367 }
1368
1369 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1370 {
1371 FNC_INFO;
1372
1373 arm11_common_t * arm11 = target->arch_info;
1374
1375 /* check IDCODE */
1376
1377 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1378
1379 scan_field_t idcode_field;
1380
1381 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1382
1383 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1384
1385 /* check DIDR */
1386
1387 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1388
1389 arm11_add_IR(arm11, ARM11_INTEST, -1);
1390
1391 scan_field_t chain0_fields[2];
1392
1393 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1394 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1395
1396 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1397
1398 jtag_execute_queue();
1399
1400
1401 switch (arm11->device_id & 0x0FFFF000)
1402 {
1403 case 0x07B36000: INFO("found ARM1136"); break;
1404 case 0x07B56000: INFO("found ARM1156"); break;
1405 case 0x07B76000: INFO("found ARM1176"); break;
1406 default:
1407 {
1408 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1409 exit(-1);
1410 }
1411 }
1412
1413 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1414
1415 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1416 arm11->debug_version != ARM11_DEBUG_V61)
1417 {
1418 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1419 exit(-1);
1420 }
1421
1422
1423 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1424 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1425
1426 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1427 arm11->free_brps = arm11->brp;
1428 arm11->free_wrps = arm11->wrp;
1429
1430 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1431 arm11->device_id,
1432 arm11->implementor,
1433 arm11->didr);
1434
1435 arm11_build_reg_cache(target);
1436
1437
1438 /* as a side-effect this reads DSCR and thus
1439 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1440 * as suggested by the spec.
1441 */
1442
1443 arm11_check_init(arm11, NULL);
1444
1445 return ERROR_OK;
1446 }
1447
1448 int arm11_quit(void)
1449 {
1450 FNC_INFO_NOTIMPLEMENTED;
1451
1452 return ERROR_OK;
1453 }
1454
1455 /** Load a register that is marked !valid in the register cache */
1456 int arm11_get_reg(reg_t *reg)
1457 {
1458 FNC_INFO;
1459
1460 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1461
1462 if (target->state != TARGET_HALTED)
1463 {
1464 return ERROR_TARGET_NOT_HALTED;
1465 }
1466
1467 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1468
1469 #if 0
1470 arm11_common_t *arm11 = target->arch_info;
1471 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1472 #endif
1473
1474 return ERROR_OK;
1475 }
1476
1477 /** Change a value in the register cache */
1478 int arm11_set_reg(reg_t *reg, u8 *buf)
1479 {
1480 FNC_INFO;
1481
1482 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1483 arm11_common_t *arm11 = target->arch_info;
1484 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1485
1486 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1487 reg->valid = 1;
1488 reg->dirty = 1;
1489
1490 return ERROR_OK;
1491 }
1492
1493
1494 void arm11_build_reg_cache(target_t *target)
1495 {
1496 arm11_common_t *arm11 = target->arch_info;
1497
1498 NEW(reg_cache_t, cache, 1);
1499 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1500 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1501
1502 if (arm11_regs_arch_type == -1)
1503 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1504
1505 arm11->reg_list = reg_list;
1506
1507 /* Build the process context cache */
1508 cache->name = "arm11 registers";
1509 cache->next = NULL;
1510 cache->reg_list = reg_list;
1511 cache->num_regs = ARM11_REGCACHE_COUNT;
1512
1513 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1514 (*cache_p) = cache;
1515
1516 // armv7m->core_cache = cache;
1517 // armv7m->process_context = cache;
1518
1519 size_t i;
1520
1521 /* Not very elegant assertion */
1522 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1523 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1524 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1525 {
1526 ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1527 exit(-1);
1528 }
1529
1530 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1531 {
1532 reg_t * r = reg_list + i;
1533 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1534 arm11_reg_state_t * rs = arm11_reg_states + i;
1535
1536 r->name = rd->name;
1537 r->size = 32;
1538 r->value = (u8 *)(arm11->reg_values + i);
1539 r->dirty = 0;
1540 r->valid = 0;
1541 r->bitfield_desc = NULL;
1542 r->num_bitfields = 0;
1543 r->arch_type = arm11_regs_arch_type;
1544 r->arch_info = rs;
1545
1546 rs->def_index = i;
1547 rs->target = target;
1548 }
1549 }
1550
1551
1552
1553 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1554 {
1555 if (argc == 0)
1556 {
1557 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1558 return ERROR_OK;
1559 }
1560
1561 if (argc != 1)
1562 return ERROR_COMMAND_SYNTAX_ERROR;
1563
1564 switch (args[0][0])
1565 {
1566 case '0': /* 0 */
1567 case 'f': /* false */
1568 case 'F':
1569 case 'd': /* disable */
1570 case 'D':
1571 *var = false;
1572 break;
1573
1574 case '1': /* 1 */
1575 case 't': /* true */
1576 case 'T':
1577 case 'e': /* enable */
1578 case 'E':
1579 *var = true;
1580 break;
1581 }
1582
1583 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1584
1585 return ERROR_OK;
1586 }
1587
1588
1589 #define BOOL_WRAPPER(name, print_name) \
1590 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1591 { \
1592 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1593 }
1594
1595 #define RC_TOP(name, descr, more) \
1596 { \
1597 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1598 command_t * top_cmd = new_cmd; \
1599 more \
1600 }
1601
1602 #define RC_FINAL(name, descr, handler) \
1603 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1604
1605 #define RC_FINAL_BOOL(name, descr, var) \
1606 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1607
1608
1609 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1610 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1611
1612
1613 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1614 {
1615 if (argc == 1)
1616 {
1617 arm11_vcr = strtoul(args[0], NULL, 0);
1618 }
1619 else if (argc != 0)
1620 {
1621 return ERROR_COMMAND_SYNTAX_ERROR;
1622 }
1623
1624 INFO("VCR 0x%08X", arm11_vcr);
1625 return ERROR_OK;
1626 }
1627
1628
1629 int arm11_register_commands(struct command_context_s *cmd_ctx)
1630 {
1631 FNC_INFO;
1632
1633 command_t * top_cmd = NULL;
1634
1635 RC_TOP( "arm11", "arm11 specific commands",
1636
1637 RC_TOP( "memwrite", "Control memory write transfer mode",
1638
1639 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1640 memwrite_burst)
1641
1642 RC_FINAL_BOOL( "error_fatal",
1643 "Terminate program if transfer error was found (default: enabled)",
1644 memwrite_error_fatal)
1645 )
1646
1647 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1648 arm11_handle_vcr)
1649 )
1650
1651 return ERROR_OK;
1652 }
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