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Michael Bruck <mbruck@digenius.de> ARM11 various updates + fix formatting.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "arm11.h"
29 #include "jtag.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 u32 arm11_vcr = 0;
56 bool arm11_config_memrw_no_increment = false;
57 bool arm11_config_step_irq_enable = false;
58
59 #define ARM11_HANDLER(x) \
60 .x = arm11_##x
61
62 target_type_t arm11_target =
63 {
64 .name = "arm11",
65
66 ARM11_HANDLER(poll),
67 ARM11_HANDLER(arch_state),
68
69 ARM11_HANDLER(target_request_data),
70
71 ARM11_HANDLER(halt),
72 ARM11_HANDLER(resume),
73 ARM11_HANDLER(step),
74
75 ARM11_HANDLER(assert_reset),
76 ARM11_HANDLER(deassert_reset),
77 ARM11_HANDLER(soft_reset_halt),
78
79 ARM11_HANDLER(get_gdb_reg_list),
80
81 ARM11_HANDLER(read_memory),
82 ARM11_HANDLER(write_memory),
83
84 ARM11_HANDLER(bulk_write_memory),
85
86 ARM11_HANDLER(checksum_memory),
87
88 ARM11_HANDLER(add_breakpoint),
89 ARM11_HANDLER(remove_breakpoint),
90 ARM11_HANDLER(add_watchpoint),
91 ARM11_HANDLER(remove_watchpoint),
92
93 ARM11_HANDLER(run_algorithm),
94
95 ARM11_HANDLER(register_commands),
96 ARM11_HANDLER(target_create),
97 ARM11_HANDLER(init_target),
98 ARM11_HANDLER(examine),
99 ARM11_HANDLER(quit),
100 };
101
102 int arm11_regs_arch_type = -1;
103
104
105 enum arm11_regtype
106 {
107 ARM11_REGISTER_CORE,
108 ARM11_REGISTER_CPSR,
109
110 ARM11_REGISTER_FX,
111 ARM11_REGISTER_FPS,
112
113 ARM11_REGISTER_FIQ,
114 ARM11_REGISTER_SVC,
115 ARM11_REGISTER_ABT,
116 ARM11_REGISTER_IRQ,
117 ARM11_REGISTER_UND,
118 ARM11_REGISTER_MON,
119
120 ARM11_REGISTER_SPSR_FIQ,
121 ARM11_REGISTER_SPSR_SVC,
122 ARM11_REGISTER_SPSR_ABT,
123 ARM11_REGISTER_SPSR_IRQ,
124 ARM11_REGISTER_SPSR_UND,
125 ARM11_REGISTER_SPSR_MON,
126
127 /* debug regs */
128 ARM11_REGISTER_DSCR,
129 ARM11_REGISTER_WDTR,
130 ARM11_REGISTER_RDTR,
131 };
132
133
134 typedef struct arm11_reg_defs_s
135 {
136 char * name;
137 u32 num;
138 int gdb_num;
139 enum arm11_regtype type;
140 } arm11_reg_defs_t;
141
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs[] =
144 {
145 {"r0", 0, 0, ARM11_REGISTER_CORE},
146 {"r1", 1, 1, ARM11_REGISTER_CORE},
147 {"r2", 2, 2, ARM11_REGISTER_CORE},
148 {"r3", 3, 3, ARM11_REGISTER_CORE},
149 {"r4", 4, 4, ARM11_REGISTER_CORE},
150 {"r5", 5, 5, ARM11_REGISTER_CORE},
151 {"r6", 6, 6, ARM11_REGISTER_CORE},
152 {"r7", 7, 7, ARM11_REGISTER_CORE},
153 {"r8", 8, 8, ARM11_REGISTER_CORE},
154 {"r9", 9, 9, ARM11_REGISTER_CORE},
155 {"r10", 10, 10, ARM11_REGISTER_CORE},
156 {"r11", 11, 11, ARM11_REGISTER_CORE},
157 {"r12", 12, 12, ARM11_REGISTER_CORE},
158 {"sp", 13, 13, ARM11_REGISTER_CORE},
159 {"lr", 14, 14, ARM11_REGISTER_CORE},
160 {"pc", 15, 15, ARM11_REGISTER_CORE},
161
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX},
164 {"f1", 1, 17, ARM11_REGISTER_FX},
165 {"f2", 2, 18, ARM11_REGISTER_FX},
166 {"f3", 3, 19, ARM11_REGISTER_FX},
167 {"f4", 4, 20, ARM11_REGISTER_FX},
168 {"f5", 5, 21, ARM11_REGISTER_FX},
169 {"f6", 6, 22, ARM11_REGISTER_FX},
170 {"f7", 7, 23, ARM11_REGISTER_FX},
171 {"fps", 0, 24, ARM11_REGISTER_FPS},
172 #endif
173
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
175
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
185
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
189
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
193
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
197
198 {"r13_und", 13, -1, ARM11_REGISTER_UND},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
201
202 /* ARM1176 only */
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
206 #endif
207
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
212 };
213
214 enum arm11_regcache_ids
215 {
216 ARM11_RC_R0,
217 ARM11_RC_RX = ARM11_RC_R0,
218
219 ARM11_RC_R1,
220 ARM11_RC_R2,
221 ARM11_RC_R3,
222 ARM11_RC_R4,
223 ARM11_RC_R5,
224 ARM11_RC_R6,
225 ARM11_RC_R7,
226 ARM11_RC_R8,
227 ARM11_RC_R9,
228 ARM11_RC_R10,
229 ARM11_RC_R11,
230 ARM11_RC_R12,
231 ARM11_RC_R13,
232 ARM11_RC_SP = ARM11_RC_R13,
233 ARM11_RC_R14,
234 ARM11_RC_LR = ARM11_RC_R14,
235 ARM11_RC_R15,
236 ARM11_RC_PC = ARM11_RC_R15,
237
238 #if ARM11_REGCACHE_FREGS
239 ARM11_RC_F0,
240 ARM11_RC_FX = ARM11_RC_F0,
241 ARM11_RC_F1,
242 ARM11_RC_F2,
243 ARM11_RC_F3,
244 ARM11_RC_F4,
245 ARM11_RC_F5,
246 ARM11_RC_F6,
247 ARM11_RC_F7,
248 ARM11_RC_FPS,
249 #endif
250
251 ARM11_RC_CPSR,
252
253 #if ARM11_REGCACHE_MODEREGS
254 ARM11_RC_R8_FIQ,
255 ARM11_RC_R9_FIQ,
256 ARM11_RC_R10_FIQ,
257 ARM11_RC_R11_FIQ,
258 ARM11_RC_R12_FIQ,
259 ARM11_RC_R13_FIQ,
260 ARM11_RC_R14_FIQ,
261 ARM11_RC_SPSR_FIQ,
262
263 ARM11_RC_R13_SVC,
264 ARM11_RC_R14_SVC,
265 ARM11_RC_SPSR_SVC,
266
267 ARM11_RC_R13_ABT,
268 ARM11_RC_R14_ABT,
269 ARM11_RC_SPSR_ABT,
270
271 ARM11_RC_R13_IRQ,
272 ARM11_RC_R14_IRQ,
273 ARM11_RC_SPSR_IRQ,
274
275 ARM11_RC_R13_UND,
276 ARM11_RC_R14_UND,
277 ARM11_RC_SPSR_UND,
278
279 ARM11_RC_R13_MON,
280 ARM11_RC_R14_MON,
281 ARM11_RC_SPSR_MON,
282 #endif
283
284 ARM11_RC_DSCR,
285 ARM11_RC_WDTR,
286 ARM11_RC_RDTR,
287
288 ARM11_RC_MAX,
289 };
290
291 #define ARM11_GDB_REGISTER_COUNT 26
292
293 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
294
295 reg_t arm11_gdb_dummy_fp_reg =
296 {
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 };
299
300 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
301
302 reg_t arm11_gdb_dummy_fps_reg =
303 {
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
305 };
306
307
308
309 /** Check and if necessary take control of the system
310 *
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
315 */
316 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
317 {
318 FNC_INFO;
319
320 u32 dscr_local_tmp_copy;
321
322 if (!dscr)
323 {
324 dscr = &dscr_local_tmp_copy;
325 *dscr = arm11_read_DSCR(arm11);
326 }
327
328 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
329 {
330 LOG_DEBUG("Bringing target into debug mode");
331
332 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
333 arm11_write_DSCR(arm11, *dscr);
334
335 /* add further reset initialization here */
336
337 arm11->simulate_reset_on_next_halt = true;
338
339 if (*dscr & ARM11_DSCR_CORE_HALTED)
340 {
341 /** \todo TODO: this needs further scrutiny because
342 * arm11_on_enter_debug_state() never gets properly called
343 */
344
345 arm11->target->state = TARGET_HALTED;
346 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
347 }
348 else
349 {
350 arm11->target->state = TARGET_RUNNING;
351 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
352 }
353
354 arm11_sc7_clear_vbw(arm11);
355 }
356 }
357
358
359
360 #define R(x) \
361 (arm11->reg_values[ARM11_RC_##x])
362
363 /** Save processor state.
364 *
365 * This is called when the HALT instruction has succeeded
366 * or on other occasions that stop the processor.
367 *
368 */
369 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
370 {
371 FNC_INFO;
372
373 {size_t i;
374 for(i = 0; i < asizeof(arm11->reg_values); i++)
375 {
376 arm11->reg_list[i].valid = 1;
377 arm11->reg_list[i].dirty = 0;
378 }}
379
380 /* Save DSCR */
381
382 R(DSCR) = arm11_read_DSCR(arm11);
383
384 /* Save wDTR */
385
386 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
387 {
388 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
389
390 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
391
392 scan_field_t chain5_fields[3];
393
394 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
395 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
396 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
397
398 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
399 }
400 else
401 {
402 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
403 }
404
405
406 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
407 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
408 ARM1136 seems to require this to issue ITR's as well */
409
410 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
411
412 /* this executes JTAG queue: */
413
414 arm11_write_DSCR(arm11, new_dscr);
415
416
417 /* From the spec:
418 Before executing any instruction in debug state you have to drain the write buffer.
419 This ensures that no imprecise Data Aborts can return at a later point:*/
420
421 /** \todo TODO: Test drain write buffer. */
422
423 #if 0
424 while (1)
425 {
426 /* MRC p14,0,R0,c5,c10,0 */
427 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
428
429 /* mcr 15, 0, r0, cr7, cr10, {4} */
430 arm11_run_instr_no_data1(arm11, 0xee070f9a);
431
432 u32 dscr = arm11_read_DSCR(arm11);
433
434 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
435
436 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
437 {
438 arm11_run_instr_no_data1(arm11, 0xe320f000);
439
440 dscr = arm11_read_DSCR(arm11);
441
442 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
443
444 break;
445 }
446 }
447 #endif
448
449 arm11_run_instr_data_prepare(arm11);
450
451 /* save r0 - r14 */
452
453 /** \todo TODO: handle other mode registers */
454
455 {size_t i;
456 for (i = 0; i < 15; i++)
457 {
458 /* MCR p14,0,R?,c0,c5,0 */
459 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
460 }}
461
462 /* save rDTR */
463
464 /* check rDTRfull in DSCR */
465
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
467 {
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
470 }
471 else
472 {
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
474 }
475
476 /* save CPSR */
477
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
480
481 /* save PC */
482
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
485
486 /* adjust PC depending on ARM state */
487
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
489 {
490 arm11->reg_values[ARM11_RC_PC] -= 0;
491 }
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 4;
495 }
496 else /* ARM state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 8;
499 }
500
501 if (arm11->simulate_reset_on_next_halt)
502 {
503 arm11->simulate_reset_on_next_halt = false;
504
505 LOG_DEBUG("Reset c1 Control Register");
506
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
508
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
511
512 }
513
514 arm11_run_instr_data_finish(arm11);
515
516 arm11_dump_reg_changes(arm11);
517 }
518
519 void arm11_dump_reg_changes(arm11_common_t * arm11)
520 {
521 {size_t i;
522 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
523 {
524 if (!arm11->reg_list[i].valid)
525 {
526 if (arm11->reg_history[i].valid)
527 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
528 }
529 else
530 {
531 if (arm11->reg_history[i].valid)
532 {
533 if (arm11->reg_history[i].value != arm11->reg_values[i])
534 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
535 }
536 else
537 {
538 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
539 }
540 }
541 }}
542 }
543
544 /** Restore processor state
545 *
546 * This is called in preparation for the RESTART function.
547 *
548 */
549 void arm11_leave_debug_state(arm11_common_t * arm11)
550 {
551 FNC_INFO;
552
553 arm11_run_instr_data_prepare(arm11);
554
555 /** \todo TODO: handle other mode registers */
556
557 /* restore R1 - R14 */
558 {size_t i;
559 for (i = 1; i < 15; i++)
560 {
561 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
562 continue;
563
564 /* MRC p14,0,r?,c0,c5,0 */
565 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
566
567 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
568 }}
569
570 arm11_run_instr_data_finish(arm11);
571
572 /* spec says clear wDTR and rDTR; we assume they are clear as
573 otherwise our programming would be sloppy */
574 {
575 u32 DSCR = arm11_read_DSCR(arm11);
576
577 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
578 {
579 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
580 }
581 }
582
583 arm11_run_instr_data_prepare(arm11);
584
585 /* restore original wDTR */
586
587 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
588 {
589 /* MCR p14,0,R0,c0,c5,0 */
590 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
591 }
592
593 /* restore CPSR */
594
595 /* MSR CPSR,R0*/
596 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
597
598 /* restore PC */
599
600 /* MOV PC,R0 */
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
602
603 /* restore R0 */
604
605 /* MRC p14,0,r0,c0,c5,0 */
606 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
607
608 arm11_run_instr_data_finish(arm11);
609
610 /* restore DSCR */
611
612 arm11_write_DSCR(arm11, R(DSCR));
613
614 /* restore rDTR */
615
616 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
617 {
618 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
619
620 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
621
622 scan_field_t chain5_fields[3];
623
624 u8 Ready = 0; /* ignored */
625 u8 Valid = 0; /* ignored */
626
627 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
628 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
629 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
630
631 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
632 }
633
634 arm11_record_register_history(arm11);
635 }
636
637 void arm11_record_register_history(arm11_common_t * arm11)
638 {
639 {size_t i;
640 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
641 {
642 arm11->reg_history[i].value = arm11->reg_values[i];
643 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
644
645 arm11->reg_list[i].valid = 0;
646 arm11->reg_list[i].dirty = 0;
647 }}
648 }
649
650
651 /* poll current target status */
652 int arm11_poll(struct target_s *target)
653 {
654 FNC_INFO;
655
656 arm11_common_t * arm11 = target->arch_info;
657
658 if (arm11->trst_active)
659 return ERROR_OK;
660
661 u32 dscr = arm11_read_DSCR(arm11);
662
663 LOG_DEBUG("DSCR %08x", dscr);
664
665 arm11_check_init(arm11, &dscr);
666
667 if (dscr & ARM11_DSCR_CORE_HALTED)
668 {
669 if (target->state != TARGET_HALTED)
670 {
671 enum target_state old_state = target->state;
672
673 LOG_DEBUG("enter TARGET_HALTED");
674 target->state = TARGET_HALTED;
675 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
676 arm11_on_enter_debug_state(arm11);
677
678 target_call_event_callbacks(target,
679 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
680 }
681 }
682 else
683 {
684 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
685 {
686 LOG_DEBUG("enter TARGET_RUNNING");
687 target->state = TARGET_RUNNING;
688 target->debug_reason = DBG_REASON_NOTHALTED;
689 }
690 }
691
692 return ERROR_OK;
693 }
694 /* architecture specific status reply */
695 int arm11_arch_state(struct target_s *target)
696 {
697 FNC_INFO_NOTIMPLEMENTED;
698
699 return ERROR_OK;
700 }
701
702 /* target request support */
703 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
704 {
705 FNC_INFO_NOTIMPLEMENTED;
706
707 return ERROR_OK;
708 }
709
710 /* target execution control */
711 int arm11_halt(struct target_s *target)
712 {
713 int retval = ERROR_OK;
714
715 FNC_INFO;
716
717 arm11_common_t * arm11 = target->arch_info;
718
719 LOG_DEBUG("target->state: %s",
720 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
721
722 if (target->state == TARGET_UNKNOWN)
723 {
724 arm11->simulate_reset_on_next_halt = true;
725 }
726
727 if (target->state == TARGET_HALTED)
728 {
729 LOG_DEBUG("target was already halted");
730 return ERROR_OK;
731 }
732
733 if (arm11->trst_active)
734 {
735 arm11->halt_requested = true;
736 return ERROR_OK;
737 }
738
739 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
740
741 if((retval = jtag_execute_queue()) != ERROR_OK)
742 {
743 return retval;
744 }
745
746 u32 dscr;
747
748 while (1)
749 {
750 dscr = arm11_read_DSCR(arm11);
751
752 if (dscr & ARM11_DSCR_CORE_HALTED)
753 break;
754 }
755
756 arm11_on_enter_debug_state(arm11);
757
758 enum target_state old_state = target->state;
759
760 target->state = TARGET_HALTED;
761 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
762
763 if((retval = target_call_event_callbacks(target,
764 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
765 {
766 return retval;
767 }
768
769 return ERROR_OK;
770 }
771
772 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
773 {
774 int retval = ERROR_OK;
775
776 FNC_INFO;
777
778 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
779 // current, address, handle_breakpoints, debug_execution);
780
781 arm11_common_t * arm11 = target->arch_info;
782
783 LOG_DEBUG("target->state: %s",
784 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
785
786
787 if (target->state != TARGET_HALTED)
788 {
789 LOG_ERROR("Target not halted");
790 return ERROR_TARGET_NOT_HALTED;
791 }
792
793 if (!current)
794 R(PC) = address;
795
796 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
797
798 /* clear breakpoints/watchpoints and VCR*/
799 arm11_sc7_clear_vbw(arm11);
800
801 /* Set up breakpoints */
802 if (!debug_execution)
803 {
804 /* check if one matches PC and step over it if necessary */
805
806 breakpoint_t * bp;
807
808 for (bp = target->breakpoints; bp; bp = bp->next)
809 {
810 if (bp->address == R(PC))
811 {
812 LOG_DEBUG("must step over %08x", bp->address);
813 arm11_step(target, 1, 0, 0);
814 break;
815 }
816 }
817
818 /* set all breakpoints */
819
820 size_t brp_num = 0;
821
822 for (bp = target->breakpoints; bp; bp = bp->next)
823 {
824 arm11_sc7_action_t brp[2];
825
826 brp[0].write = 1;
827 brp[0].address = ARM11_SC7_BVR0 + brp_num;
828 brp[0].value = bp->address;
829 brp[1].write = 1;
830 brp[1].address = ARM11_SC7_BCR0 + brp_num;
831 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
832
833 arm11_sc7_run(arm11, brp, asizeof(brp));
834
835 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
836
837 brp_num++;
838 }
839
840 arm11_sc7_set_vcr(arm11, arm11_vcr);
841 }
842
843 arm11_leave_debug_state(arm11);
844
845 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
846
847 if((retval = jtag_execute_queue()) != ERROR_OK)
848 {
849 return retval;
850 }
851
852 while (1)
853 {
854 u32 dscr = arm11_read_DSCR(arm11);
855
856 LOG_DEBUG("DSCR %08x", dscr);
857
858 if (dscr & ARM11_DSCR_CORE_RESTARTED)
859 break;
860 }
861
862 if (!debug_execution)
863 {
864 target->state = TARGET_RUNNING;
865 target->debug_reason = DBG_REASON_NOTHALTED;
866
867 if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
868 {
869 return retval;
870 }
871 }
872 else
873 {
874 target->state = TARGET_DEBUG_RUNNING;
875 target->debug_reason = DBG_REASON_NOTHALTED;
876 if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
877 {
878 return retval;
879 }
880 }
881
882 return ERROR_OK;
883 }
884
885 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
886 {
887 int retval = ERROR_OK;
888
889 FNC_INFO;
890
891 LOG_DEBUG("target->state: %s",
892 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
893
894 if (target->state != TARGET_HALTED)
895 {
896 LOG_WARNING("target was not halted");
897 return ERROR_TARGET_NOT_HALTED;
898 }
899
900 arm11_common_t * arm11 = target->arch_info;
901
902 if (!current)
903 R(PC) = address;
904
905 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
906
907 /** \todo TODO: Thumb not supported here */
908
909 u32 next_instruction;
910
911 arm11_read_memory_word(arm11, R(PC), &next_instruction);
912
913 /* skip over BKPT */
914 if ((next_instruction & 0xFFF00070) == 0xe1200070)
915 {
916 R(PC) += 4;
917 arm11->reg_list[ARM11_RC_PC].valid = 1;
918 arm11->reg_list[ARM11_RC_PC].dirty = 0;
919 LOG_INFO("Skipping BKPT");
920 }
921 /* skip over Wait for interrupt / Standby */
922 /* mcr 15, 0, r?, cr7, cr0, {4} */
923 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
924 {
925 R(PC) += 4;
926 arm11->reg_list[ARM11_RC_PC].valid = 1;
927 arm11->reg_list[ARM11_RC_PC].dirty = 0;
928 LOG_INFO("Skipping WFI");
929 }
930 /* ignore B to self */
931 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
932 {
933 LOG_INFO("Not stepping jump to self");
934 }
935 else
936 {
937 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
938 * with this. */
939
940 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
941 * the VCR might be something worth looking into. */
942
943
944 /* Set up breakpoint for stepping */
945
946 arm11_sc7_action_t brp[2];
947
948 brp[0].write = 1;
949 brp[0].address = ARM11_SC7_BVR0;
950 brp[0].value = R(PC);
951 brp[1].write = 1;
952 brp[1].address = ARM11_SC7_BCR0;
953 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
954
955 arm11_sc7_run(arm11, brp, asizeof(brp));
956
957 /* resume */
958
959
960 if (arm11_config_step_irq_enable)
961 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
962 else
963 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
964
965
966 arm11_leave_debug_state(arm11);
967
968 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
969
970 if((retval = jtag_execute_queue()) != ERROR_OK)
971 {
972 return retval;
973 }
974
975 /** \todo TODO: add a timeout */
976
977 /* wait for halt */
978
979 while (1)
980 {
981 u32 dscr = arm11_read_DSCR(arm11);
982
983 LOG_DEBUG("DSCR %08x", dscr);
984
985 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
986 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
987 break;
988 }
989
990 /* clear breakpoint */
991 arm11_sc7_clear_vbw(arm11);
992
993 /* save state */
994 arm11_on_enter_debug_state(arm11);
995
996 /* restore default state */
997 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
998
999 }
1000
1001 // target->state = TARGET_HALTED;
1002 target->debug_reason = DBG_REASON_SINGLESTEP;
1003
1004 if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1005 {
1006 return retval;
1007 }
1008
1009 return ERROR_OK;
1010 }
1011
1012 /* target reset control */
1013 int arm11_assert_reset(struct target_s *target)
1014 {
1015 FNC_INFO;
1016
1017 #if 0
1018 /* assert reset lines */
1019 /* resets only the DBGTAP, not the ARM */
1020
1021 jtag_add_reset(1, 0);
1022 jtag_add_sleep(5000);
1023
1024 arm11_common_t * arm11 = target->arch_info;
1025 arm11->trst_active = true;
1026 #endif
1027
1028 if (target->reset_halt)
1029 {
1030 int retval;
1031 if ((retval = target_halt(target))!=ERROR_OK)
1032 return retval;
1033 }
1034
1035 return ERROR_OK;
1036 }
1037
1038 int arm11_deassert_reset(struct target_s *target)
1039 {
1040 FNC_INFO;
1041
1042 #if 0
1043 LOG_DEBUG("target->state: %s",
1044 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1045
1046
1047 /* deassert reset lines */
1048 jtag_add_reset(0, 0);
1049
1050 arm11_common_t * arm11 = target->arch_info;
1051 arm11->trst_active = false;
1052
1053 if (arm11->halt_requested)
1054 return arm11_halt(target);
1055 #endif
1056
1057 return ERROR_OK;
1058 }
1059
1060 int arm11_soft_reset_halt(struct target_s *target)
1061 {
1062 FNC_INFO_NOTIMPLEMENTED;
1063
1064 return ERROR_OK;
1065 }
1066
1067 /* target register access for gdb */
1068 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1069 {
1070 FNC_INFO;
1071
1072 arm11_common_t * arm11 = target->arch_info;
1073
1074 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1075 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1076
1077 {size_t i;
1078 for (i = 16; i < 24; i++)
1079 {
1080 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1081 }}
1082
1083 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1084
1085 {size_t i;
1086 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1087 {
1088 if (arm11_reg_defs[i].gdb_num == -1)
1089 continue;
1090
1091 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1092 }}
1093
1094 return ERROR_OK;
1095 }
1096
1097 /* target memory access
1098 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1099 * count: number of items of <size>
1100 */
1101 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1102 {
1103 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1104
1105 FNC_INFO;
1106
1107 if (target->state != TARGET_HALTED)
1108 {
1109 LOG_WARNING("target was not halted");
1110 return ERROR_TARGET_NOT_HALTED;
1111 }
1112
1113 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1114
1115 arm11_common_t * arm11 = target->arch_info;
1116
1117 arm11_run_instr_data_prepare(arm11);
1118
1119 /* MRC p14,0,r0,c0,c5,0 */
1120 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1121
1122 switch (size)
1123 {
1124 case 1:
1125 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1126 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1127
1128 {size_t i;
1129 for (i = 0; i < count; i++)
1130 {
1131 /* ldrb r1, [r0], #1 */
1132 /* ldrb r1, [r0] */
1133 arm11_run_instr_no_data1(arm11,
1134 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1135
1136 u32 res;
1137 /* MCR p14,0,R1,c0,c5,0 */
1138 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1139
1140 *buffer++ = res;
1141 }}
1142
1143 break;
1144
1145 case 2:
1146 {
1147 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1148
1149 u16 * buf16 = (u16*)buffer;
1150
1151 {size_t i;
1152 for (i = 0; i < count; i++)
1153 {
1154 /* ldrh r1, [r0], #2 */
1155 arm11_run_instr_no_data1(arm11,
1156 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1157
1158 u32 res;
1159
1160 /* MCR p14,0,R1,c0,c5,0 */
1161 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1162
1163 *buf16++ = res;
1164 }}
1165
1166 break;
1167 }
1168
1169 case 4:
1170
1171 /* LDC p14,c5,[R0],#4 */
1172 /* LDC p14,c5,[R0] */
1173 arm11_run_instr_data_from_core(arm11,
1174 (!arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00),
1175 (u32 *)buffer, count);
1176 break;
1177 }
1178
1179 arm11_run_instr_data_finish(arm11);
1180
1181 return ERROR_OK;
1182 }
1183
1184 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1185 {
1186 FNC_INFO;
1187
1188 if (target->state != TARGET_HALTED)
1189 {
1190 LOG_WARNING("target was not halted");
1191 return ERROR_TARGET_NOT_HALTED;
1192 }
1193
1194 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1195
1196 arm11_common_t * arm11 = target->arch_info;
1197
1198 arm11_run_instr_data_prepare(arm11);
1199
1200 /* MRC p14,0,r0,c0,c5,0 */
1201 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1202
1203 switch (size)
1204 {
1205 case 1:
1206 {
1207 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1208
1209 {size_t i;
1210 for (i = 0; i < count; i++)
1211 {
1212 /* MRC p14,0,r1,c0,c5,0 */
1213 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1214
1215 /* strb r1, [r0], #1 */
1216 /* strb r1, [r0] */
1217 arm11_run_instr_no_data1(arm11,
1218 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1219 }}
1220
1221 break;
1222 }
1223
1224 case 2:
1225 {
1226 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1227
1228 u16 * buf16 = (u16*)buffer;
1229
1230 {size_t i;
1231 for (i = 0; i < count; i++)
1232 {
1233 /* MRC p14,0,r1,c0,c5,0 */
1234 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1235
1236 /* strh r1, [r0], #2 */
1237 /* strh r1, [r0] */
1238 arm11_run_instr_no_data1(arm11,
1239 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1240 }}
1241
1242 break;
1243 }
1244
1245 case 4:
1246 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1247
1248 if (!arm11_config_memwrite_burst)
1249 {
1250 /* STC p14,c5,[R0],#4 */
1251 /* STC p14,c5,[R0]*/
1252 arm11_run_instr_data_to_core(arm11,
1253 (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
1254 (u32 *)buffer, count);
1255 }
1256 else
1257 {
1258 /* STC p14,c5,[R0],#4 */
1259 /* STC p14,c5,[R0]*/
1260 arm11_run_instr_data_to_core_noack(arm11,
1261 (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
1262 (u32 *)buffer, count);
1263 }
1264
1265 break;
1266 }
1267
1268 #if 1
1269 /* r0 verification */
1270 if (!arm11_config_memrw_no_increment)
1271 {
1272 u32 r0;
1273
1274 /* MCR p14,0,R0,c0,c5,0 */
1275 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1276
1277 if (address + size * count != r0)
1278 {
1279 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1280
1281 if (arm11_config_memwrite_burst)
1282 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1283
1284 if (arm11_config_memwrite_error_fatal)
1285 return ERROR_FAIL;
1286 }
1287 }
1288 #endif
1289
1290 arm11_run_instr_data_finish(arm11);
1291
1292 return ERROR_OK;
1293 }
1294
1295
1296 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1297 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1298 {
1299 FNC_INFO;
1300
1301 if (target->state != TARGET_HALTED)
1302 {
1303 LOG_WARNING("target was not halted");
1304 return ERROR_TARGET_NOT_HALTED;
1305 }
1306
1307 return arm11_write_memory(target, address, 4, count, buffer);
1308 }
1309
1310 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1311 {
1312 FNC_INFO_NOTIMPLEMENTED;
1313
1314 return ERROR_OK;
1315 }
1316
1317 /* target break-/watchpoint control
1318 * rw: 0 = write, 1 = read, 2 = access
1319 */
1320 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1321 {
1322 FNC_INFO;
1323
1324 arm11_common_t * arm11 = target->arch_info;
1325
1326 #if 0
1327 if (breakpoint->type == BKPT_SOFT)
1328 {
1329 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1330 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1331 }
1332 #endif
1333
1334 if (!arm11->free_brps)
1335 {
1336 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1337 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1338 }
1339
1340 if (breakpoint->length != 4)
1341 {
1342 LOG_INFO("only breakpoints of four bytes length supported");
1343 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1344 }
1345
1346 arm11->free_brps--;
1347
1348 return ERROR_OK;
1349 }
1350
1351 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1352 {
1353 FNC_INFO;
1354
1355 arm11_common_t * arm11 = target->arch_info;
1356
1357 arm11->free_brps++;
1358
1359 return ERROR_OK;
1360 }
1361
1362 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1363 {
1364 FNC_INFO_NOTIMPLEMENTED;
1365
1366 return ERROR_OK;
1367 }
1368
1369 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1370 {
1371 FNC_INFO_NOTIMPLEMENTED;
1372
1373 return ERROR_OK;
1374 }
1375
1376 // HACKHACKHACK - FIXME mode/state
1377 /* target algorithm support */
1378 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1379 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1380 int timeout_ms, void *arch_info)
1381 {
1382 arm11_common_t *arm11 = target->arch_info;
1383 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1384 // enum armv4_5_state core_state = arm11->core_state;
1385 // enum armv4_5_mode core_mode = arm11->core_mode;
1386 u32 context[16];
1387 u32 cpsr;
1388 int exit_breakpoint_size = 0;
1389 int i;
1390 int retval = ERROR_OK;
1391 LOG_DEBUG("Running algorithm");
1392
1393 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1394 {
1395 LOG_ERROR("current target isn't an ARMV4/5 target");
1396 return ERROR_TARGET_INVALID;
1397 }
1398
1399 if (target->state != TARGET_HALTED)
1400 {
1401 LOG_WARNING("target not halted");
1402 return ERROR_TARGET_NOT_HALTED;
1403 }
1404
1405 // FIXME
1406 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1407 // return ERROR_FAIL;
1408
1409 // Save regs
1410 for (i = 0; i < 16; i++)
1411 {
1412 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1413 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1414 }
1415
1416 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1417 LOG_DEBUG("Save CPSR: 0x%x", cpsr);
1418
1419 for (i = 0; i < num_mem_params; i++)
1420 {
1421 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1422 }
1423
1424 // Set register parameters
1425 for (i = 0; i < num_reg_params; i++)
1426 {
1427 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1428 if (!reg)
1429 {
1430 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1431 exit(-1);
1432 }
1433
1434 if (reg->size != reg_params[i].size)
1435 {
1436 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1437 exit(-1);
1438 }
1439 arm11_set_reg(reg,reg_params[i].value);
1440 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1441 }
1442
1443 exit_breakpoint_size = 4;
1444
1445 /* arm11->core_state = arm11_algorithm_info->core_state;
1446 if (arm11->core_state == ARMV4_5_STATE_ARM)
1447 exit_breakpoint_size = 4;
1448 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1449 exit_breakpoint_size = 2;
1450 else
1451 {
1452 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1453 exit(-1);
1454 }
1455 */
1456 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1457 {
1458 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1459 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1460 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1461 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1462 }
1463
1464 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1465 {
1466 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1467 retval = ERROR_TARGET_FAILURE;
1468 goto restore;
1469 }
1470
1471 // no debug, otherwise breakpoint is not set
1472 if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
1473 {
1474 return retval;
1475 }
1476
1477 if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
1478 {
1479 return retval;
1480 }
1481
1482 if (target->state != TARGET_HALTED)
1483 {
1484 if ((retval=target_halt(target))!=ERROR_OK)
1485 return retval;
1486 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
1487 {
1488 return retval;
1489 }
1490 retval = ERROR_TARGET_TIMEOUT;
1491 goto del_breakpoint;
1492 }
1493
1494 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1495 {
1496 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1497 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1498 retval = ERROR_TARGET_TIMEOUT;
1499 goto del_breakpoint;
1500 }
1501
1502 for (i = 0; i < num_mem_params; i++)
1503 {
1504 if (mem_params[i].direction != PARAM_OUT)
1505 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1506 }
1507
1508 for (i = 0; i < num_reg_params; i++)
1509 {
1510 if (reg_params[i].direction != PARAM_OUT)
1511 {
1512 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1513 if (!reg)
1514 {
1515 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1516 exit(-1);
1517 }
1518
1519 if (reg->size != reg_params[i].size)
1520 {
1521 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1522 exit(-1);
1523 }
1524
1525 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1526 }
1527 }
1528
1529 del_breakpoint:
1530 breakpoint_remove(target, exit_point);
1531
1532 restore:
1533 // Restore context
1534 for (i = 0; i < 16; i++)
1535 {
1536 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1537 arm11->reg_list[i].name, context[i]);
1538 arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
1539 }
1540 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1541 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
1542
1543 // arm11->core_state = core_state;
1544 // arm11->core_mode = core_mode;
1545
1546 return retval;
1547 }
1548
1549 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1550 {
1551 int retval = ERROR_OK;
1552 FNC_INFO;
1553
1554 NEW(arm11_common_t, arm11, 1);
1555
1556 arm11->target = target;
1557
1558 /* prepare JTAG information for the new target */
1559 arm11->jtag_info.tap = target->tap;
1560 arm11->jtag_info.scann_size = 5;
1561
1562 if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
1563 {
1564 return retval;
1565 }
1566
1567 if (target->tap==NULL)
1568 return ERROR_FAIL;
1569
1570 if (target->tap->ir_length != 5)
1571 {
1572 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1574 }
1575
1576 target->arch_info = arm11;
1577
1578 return ERROR_OK;
1579 }
1580
1581 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1582 {
1583 /* Initialize anything we can set up without talking to the target */
1584 return arm11_build_reg_cache(target);
1585 }
1586
1587 /* talk to the target and set things up */
1588 int arm11_examine(struct target_s *target)
1589 {
1590 FNC_INFO;
1591 int retval;
1592
1593 arm11_common_t * arm11 = target->arch_info;
1594
1595 /* check IDCODE */
1596
1597 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1598
1599 scan_field_t idcode_field;
1600
1601 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1602
1603 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1604
1605 /* check DIDR */
1606
1607 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1608
1609 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1610
1611 scan_field_t chain0_fields[2];
1612
1613 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1614 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1615
1616 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1617
1618 if ((retval=jtag_execute_queue())!=ERROR_OK)
1619 return retval;
1620
1621
1622 switch (arm11->device_id & 0x0FFFF000)
1623 {
1624 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1625 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1626 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1627 default:
1628 {
1629 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1630 return ERROR_FAIL;
1631 }
1632 }
1633
1634 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1635
1636 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1637 arm11->debug_version != ARM11_DEBUG_V61)
1638 {
1639 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1640 return ERROR_FAIL;
1641 }
1642
1643 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1644 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1645
1646 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1647 arm11->free_brps = arm11->brp;
1648 arm11->free_wrps = arm11->wrp;
1649
1650 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1651 arm11->device_id,
1652 arm11->implementor,
1653 arm11->didr);
1654
1655 /* as a side-effect this reads DSCR and thus
1656 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1657 * as suggested by the spec.
1658 */
1659
1660 arm11_check_init(arm11, NULL);
1661
1662 target->type->examined = 1;
1663
1664 return ERROR_OK;
1665 }
1666
1667 int arm11_quit(void)
1668 {
1669 FNC_INFO_NOTIMPLEMENTED;
1670
1671 return ERROR_OK;
1672 }
1673
1674 /** Load a register that is marked !valid in the register cache */
1675 int arm11_get_reg(reg_t *reg)
1676 {
1677 FNC_INFO;
1678
1679 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1680
1681 if (target->state != TARGET_HALTED)
1682 {
1683 LOG_WARNING("target was not halted");
1684 return ERROR_TARGET_NOT_HALTED;
1685 }
1686
1687 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1688
1689 #if 0
1690 arm11_common_t *arm11 = target->arch_info;
1691 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1692 #endif
1693
1694 return ERROR_OK;
1695 }
1696
1697 /** Change a value in the register cache */
1698 int arm11_set_reg(reg_t *reg, u8 *buf)
1699 {
1700 FNC_INFO;
1701
1702 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1703 arm11_common_t *arm11 = target->arch_info;
1704 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1705
1706 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1707 reg->valid = 1;
1708 reg->dirty = 1;
1709
1710 return ERROR_OK;
1711 }
1712
1713 int arm11_build_reg_cache(target_t *target)
1714 {
1715 arm11_common_t *arm11 = target->arch_info;
1716
1717 NEW(reg_cache_t, cache, 1);
1718 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1719 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1720
1721 if (arm11_regs_arch_type == -1)
1722 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1723
1724 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1725 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1726
1727 arm11->reg_list = reg_list;
1728
1729 /* Build the process context cache */
1730 cache->name = "arm11 registers";
1731 cache->next = NULL;
1732 cache->reg_list = reg_list;
1733 cache->num_regs = ARM11_REGCACHE_COUNT;
1734
1735 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1736 (*cache_p) = cache;
1737
1738 arm11->core_cache = cache;
1739 // armv7m->process_context = cache;
1740
1741 size_t i;
1742
1743 /* Not very elegant assertion */
1744 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1745 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1746 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1747 {
1748 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1749 exit(-1);
1750 }
1751
1752 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1753 {
1754 reg_t * r = reg_list + i;
1755 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1756 arm11_reg_state_t * rs = arm11_reg_states + i;
1757
1758 r->name = rd->name;
1759 r->size = 32;
1760 r->value = (u8 *)(arm11->reg_values + i);
1761 r->dirty = 0;
1762 r->valid = 0;
1763 r->bitfield_desc = NULL;
1764 r->num_bitfields = 0;
1765 r->arch_type = arm11_regs_arch_type;
1766 r->arch_info = rs;
1767
1768 rs->def_index = i;
1769 rs->target = target;
1770 }
1771
1772 return ERROR_OK;
1773 }
1774
1775 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1776 {
1777 if (argc == 0)
1778 {
1779 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1780 return ERROR_OK;
1781 }
1782
1783 if (argc != 1)
1784 return ERROR_COMMAND_SYNTAX_ERROR;
1785
1786 switch (args[0][0])
1787 {
1788 case '0': /* 0 */
1789 case 'f': /* false */
1790 case 'F':
1791 case 'd': /* disable */
1792 case 'D':
1793 *var = false;
1794 break;
1795
1796 case '1': /* 1 */
1797 case 't': /* true */
1798 case 'T':
1799 case 'e': /* enable */
1800 case 'E':
1801 *var = true;
1802 break;
1803 }
1804
1805 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1806
1807 return ERROR_OK;
1808 }
1809
1810 #define BOOL_WRAPPER(name, print_name) \
1811 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1812 { \
1813 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1814 }
1815
1816 #define RC_TOP(name, descr, more) \
1817 { \
1818 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1819 command_t * top_cmd = new_cmd; \
1820 more \
1821 }
1822
1823 #define RC_FINAL(name, descr, handler) \
1824 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1825
1826 #define RC_FINAL_BOOL(name, descr, var) \
1827 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1828
1829 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1830 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1831 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1832 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1833
1834 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1835 {
1836 if (argc == 1)
1837 {
1838 arm11_vcr = strtoul(args[0], NULL, 0);
1839 }
1840 else if (argc != 0)
1841 {
1842 return ERROR_COMMAND_SYNTAX_ERROR;
1843 }
1844
1845 LOG_INFO("VCR 0x%08X", arm11_vcr);
1846 return ERROR_OK;
1847 }
1848
1849 const u32 arm11_coproc_instruction_limits[] =
1850 {
1851 15, /* coprocessor */
1852 7, /* opcode 1 */
1853 15, /* CRn */
1854 15, /* CRm */
1855 7, /* opcode 2 */
1856 0xFFFFFFFF, /* value */
1857 };
1858
1859 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1860 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1861
1862 arm11_common_t * arm11_find_target(const char * arg)
1863 {
1864 jtag_tap_t * tap;
1865 target_t * t;
1866
1867 tap = jtag_TapByString(arg);
1868
1869 if (!tap)
1870 return 0;
1871
1872 for (t = all_targets; t; t = t->next)
1873 {
1874 if (t->tap != tap)
1875 continue;
1876
1877 /* if (t->type == arm11_target) */
1878 if (0 == strcmp(t->type->name, "arm11"))
1879 return t->arch_info;
1880 }
1881
1882 return 0;
1883 }
1884
1885 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1886 {
1887 if (argc != (read ? 6 : 7))
1888 {
1889 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1890 return -1;
1891 }
1892
1893 arm11_common_t * arm11 = arm11_find_target(args[0]);
1894
1895 if (!arm11)
1896 {
1897 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1898 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1899
1900 return -1;
1901 }
1902
1903 if (arm11->target->state != TARGET_HALTED)
1904 {
1905 LOG_WARNING("target was not halted");
1906 return ERROR_TARGET_NOT_HALTED;
1907 }
1908
1909 u32 values[6];
1910
1911 {size_t i;
1912 for (i = 0; i < (read ? 5 : 6); i++)
1913 {
1914 values[i] = strtoul(args[i + 1], NULL, 0);
1915
1916 if (values[i] > arm11_coproc_instruction_limits[i])
1917 {
1918 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1919 (long)(i + 2), arm11_coproc_instruction_limits[i],
1920 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1921 return -1;
1922 }
1923 }}
1924
1925 u32 instr = 0xEE000010 |
1926 (values[0] << 8) |
1927 (values[1] << 21) |
1928 (values[2] << 16) |
1929 (values[3] << 0) |
1930 (values[4] << 5);
1931
1932 if (read)
1933 instr |= 0x00100000;
1934
1935 arm11_run_instr_data_prepare(arm11);
1936
1937 if (read)
1938 {
1939 u32 result;
1940 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1941
1942 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1943 values[0], values[1], values[2], values[3], values[4], result, result);
1944 }
1945 else
1946 {
1947 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1948
1949 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1950 values[0], values[1],
1951 values[5],
1952 values[2], values[3], values[4]);
1953 }
1954
1955 arm11_run_instr_data_finish(arm11);
1956
1957
1958 return ERROR_OK;
1959 }
1960
1961 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1962 {
1963 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1964 }
1965
1966 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1967 {
1968 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1969 }
1970
1971 int arm11_register_commands(struct command_context_s *cmd_ctx)
1972 {
1973 FNC_INFO;
1974
1975 command_t * top_cmd = NULL;
1976
1977 RC_TOP( "arm11", "arm11 specific commands",
1978
1979 RC_TOP( "memwrite", "Control memory write transfer mode",
1980
1981 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1982 memwrite_burst)
1983
1984 RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
1985 memwrite_error_fatal)
1986 )
1987
1988 RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
1989 memrw_no_increment)
1990
1991 RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
1992 step_irq_enable)
1993
1994 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1995 arm11_handle_vcr)
1996
1997 RC_FINAL( "mrc", "Read Coprocessor register",
1998 arm11_handle_mrc)
1999
2000 RC_FINAL( "mcr", "Write Coprocessor register",
2001 arm11_handle_mcr)
2002 )
2003
2004 return ERROR_OK;
2005 }
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