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Fixes SEGFAULT when setting registers from GDB.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "arm11.h"
29 #include "jtag.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39
40 #if 0
41 #define FNC_INFO LOG_DEBUG("-")
42 #else
43 #define FNC_INFO
44 #endif
45
46 #if 1
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #else
49 #define FNC_INFO_NOTIMPLEMENTED
50 #endif
51
52 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
53
54
55 bool arm11_config_memwrite_burst = true;
56 bool arm11_config_memwrite_error_fatal = true;
57 u32 arm11_vcr = 0;
58
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 ARM11_HANDLER(quit),
101 };
102
103 int arm11_regs_arch_type = -1;
104
105
106 enum arm11_regtype
107 {
108 ARM11_REGISTER_CORE,
109 ARM11_REGISTER_CPSR,
110
111 ARM11_REGISTER_FX,
112 ARM11_REGISTER_FPS,
113
114 ARM11_REGISTER_FIQ,
115 ARM11_REGISTER_SVC,
116 ARM11_REGISTER_ABT,
117 ARM11_REGISTER_IRQ,
118 ARM11_REGISTER_UND,
119 ARM11_REGISTER_MON,
120
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
127
128 /* debug regs */
129 ARM11_REGISTER_DSCR,
130 ARM11_REGISTER_WDTR,
131 ARM11_REGISTER_RDTR,
132 };
133
134
135 typedef struct arm11_reg_defs_s
136 {
137 char * name;
138 u32 num;
139 int gdb_num;
140 enum arm11_regtype type;
141 } arm11_reg_defs_t;
142
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
145 {
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
162
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
173 #endif
174
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
176
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
186
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
190
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
194
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
198
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
202
203 /* ARM1176 only */
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
207 #endif
208
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
213 };
214
215 enum arm11_regcache_ids
216 {
217 ARM11_RC_R0,
218 ARM11_RC_RX = ARM11_RC_R0,
219
220 ARM11_RC_R1,
221 ARM11_RC_R2,
222 ARM11_RC_R3,
223 ARM11_RC_R4,
224 ARM11_RC_R5,
225 ARM11_RC_R6,
226 ARM11_RC_R7,
227 ARM11_RC_R8,
228 ARM11_RC_R9,
229 ARM11_RC_R10,
230 ARM11_RC_R11,
231 ARM11_RC_R12,
232 ARM11_RC_R13,
233 ARM11_RC_SP = ARM11_RC_R13,
234 ARM11_RC_R14,
235 ARM11_RC_LR = ARM11_RC_R14,
236 ARM11_RC_R15,
237 ARM11_RC_PC = ARM11_RC_R15,
238
239 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_F0,
241 ARM11_RC_FX = ARM11_RC_F0,
242 ARM11_RC_F1,
243 ARM11_RC_F2,
244 ARM11_RC_F3,
245 ARM11_RC_F4,
246 ARM11_RC_F5,
247 ARM11_RC_F6,
248 ARM11_RC_F7,
249 ARM11_RC_FPS,
250 #endif
251
252 ARM11_RC_CPSR,
253
254 #if ARM11_REGCACHE_MODEREGS
255 ARM11_RC_R8_FIQ,
256 ARM11_RC_R9_FIQ,
257 ARM11_RC_R10_FIQ,
258 ARM11_RC_R11_FIQ,
259 ARM11_RC_R12_FIQ,
260 ARM11_RC_R13_FIQ,
261 ARM11_RC_R14_FIQ,
262 ARM11_RC_SPSR_FIQ,
263
264 ARM11_RC_R13_SVC,
265 ARM11_RC_R14_SVC,
266 ARM11_RC_SPSR_SVC,
267
268 ARM11_RC_R13_ABT,
269 ARM11_RC_R14_ABT,
270 ARM11_RC_SPSR_ABT,
271
272 ARM11_RC_R13_IRQ,
273 ARM11_RC_R14_IRQ,
274 ARM11_RC_SPSR_IRQ,
275
276 ARM11_RC_R13_UND,
277 ARM11_RC_R14_UND,
278 ARM11_RC_SPSR_UND,
279
280 ARM11_RC_R13_MON,
281 ARM11_RC_R14_MON,
282 ARM11_RC_SPSR_MON,
283 #endif
284
285 ARM11_RC_DSCR,
286 ARM11_RC_WDTR,
287 ARM11_RC_RDTR,
288
289 ARM11_RC_MAX,
290 };
291
292 #define ARM11_GDB_REGISTER_COUNT 26
293
294 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295
296 reg_t arm11_gdb_dummy_fp_reg =
297 {
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
299 };
300
301 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
302
303 reg_t arm11_gdb_dummy_fps_reg =
304 {
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 };
307
308
309
310 /** Check and if necessary take control of the system
311 *
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
316 */
317 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
318 {
319 FNC_INFO;
320
321 u32 dscr_local_tmp_copy;
322
323 if (!dscr)
324 {
325 dscr = &dscr_local_tmp_copy;
326 *dscr = arm11_read_DSCR(arm11);
327 }
328
329 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
330 {
331 LOG_DEBUG("Bringing target into debug mode");
332
333 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
334 arm11_write_DSCR(arm11, *dscr);
335
336 /* add further reset initialization here */
337
338 arm11->simulate_reset_on_next_halt = true;
339
340 if (*dscr & ARM11_DSCR_CORE_HALTED)
341 {
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called
344 */
345
346 arm11->target->state = TARGET_HALTED;
347 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
348 }
349 else
350 {
351 arm11->target->state = TARGET_RUNNING;
352 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
353 }
354
355 arm11_sc7_clear_vbw(arm11);
356 }
357 }
358
359
360
361 #define R(x) \
362 (arm11->reg_values[ARM11_RC_##x])
363
364 /** Save processor state.
365 *
366 * This is called when the HALT instruction has succeeded
367 * or on other occasions that stop the processor.
368 *
369 */
370 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
371 {
372 FNC_INFO;
373
374 {size_t i;
375 for(i = 0; i < asizeof(arm11->reg_values); i++)
376 {
377 arm11->reg_list[i].valid = 1;
378 arm11->reg_list[i].dirty = 0;
379 }}
380
381 /* Save DSCR */
382
383 R(DSCR) = arm11_read_DSCR(arm11);
384
385 /* Save wDTR */
386
387 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
388 {
389 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
390
391 arm11_add_IR(arm11, ARM11_INTEST, -1);
392
393 scan_field_t chain5_fields[3];
394
395 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
396 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
397 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
398
399 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
400 }
401 else
402 {
403 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
404 }
405
406
407 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
408 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
409 ARM1136 seems to require this to issue ITR's as well */
410
411 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
412
413 /* this executes JTAG queue: */
414
415 arm11_write_DSCR(arm11, new_dscr);
416
417
418 /* From the spec:
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
421
422 /** \todo TODO: Test drain write buffer. */
423
424 #if 0
425 while (1)
426 {
427 /* MRC p14,0,R0,c5,c10,0 */
428 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
429
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
432
433 u32 dscr = arm11_read_DSCR(arm11);
434
435 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
436
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
438 {
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
440
441 dscr = arm11_read_DSCR(arm11);
442
443 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
444
445 break;
446 }
447 }
448 #endif
449
450
451 arm11_run_instr_data_prepare(arm11);
452
453 /* save r0 - r14 */
454
455
456 /** \todo TODO: handle other mode registers */
457
458 {size_t i;
459 for (i = 0; i < 15; i++)
460 {
461 /* MCR p14,0,R?,c0,c5,0 */
462 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
463 }}
464
465
466 /* save rDTR */
467
468 /* check rDTRfull in DSCR */
469
470 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
471 {
472 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
473 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
474 }
475 else
476 {
477 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
478 }
479
480 /* save CPSR */
481
482 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
484
485 /* save PC */
486
487 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
488 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
489
490 /* adjust PC depending on ARM state */
491
492 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 0;
495 }
496 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 4;
499 }
500 else /* ARM state */
501 {
502 arm11->reg_values[ARM11_RC_PC] -= 8;
503 }
504
505 if (arm11->simulate_reset_on_next_halt)
506 {
507 arm11->simulate_reset_on_next_halt = false;
508
509 LOG_DEBUG("Reset c1 Control Register");
510
511 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
512
513 /* MCR p15,0,R0,c1,c0,0 */
514 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
515
516 }
517
518 arm11_run_instr_data_finish(arm11);
519
520 arm11_dump_reg_changes(arm11);
521 }
522
523 void arm11_dump_reg_changes(arm11_common_t * arm11)
524 {
525 {size_t i;
526 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
527 {
528 if (!arm11->reg_list[i].valid)
529 {
530 if (arm11->reg_history[i].valid)
531 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
532 }
533 else
534 {
535 if (arm11->reg_history[i].valid)
536 {
537 if (arm11->reg_history[i].value != arm11->reg_values[i])
538 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
539 }
540 else
541 {
542 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
543 }
544 }
545 }}
546 }
547
548
549 /** Restore processor state
550 *
551 * This is called in preparation for the RESTART function.
552 *
553 */
554 void arm11_leave_debug_state(arm11_common_t * arm11)
555 {
556 FNC_INFO;
557
558 arm11_run_instr_data_prepare(arm11);
559
560 /** \todo TODO: handle other mode registers */
561
562 /* restore R1 - R14 */
563 {size_t i;
564 for (i = 1; i < 15; i++)
565 {
566 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
567 continue;
568
569 /* MRC p14,0,r?,c0,c5,0 */
570 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
571
572 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
573 }}
574
575 arm11_run_instr_data_finish(arm11);
576
577
578 /* spec says clear wDTR and rDTR; we assume they are clear as
579 otherwise our programming would be sloppy */
580
581 {
582 u32 DSCR = arm11_read_DSCR(arm11);
583
584 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
585 {
586 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
587 }
588 }
589
590 arm11_run_instr_data_prepare(arm11);
591
592 /* restore original wDTR */
593
594 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
595 {
596 /* MCR p14,0,R0,c0,c5,0 */
597 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
598 }
599
600 /* restore CPSR */
601
602 /* MSR CPSR,R0*/
603 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
604
605
606 /* restore PC */
607
608 /* MOV PC,R0 */
609 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
610
611
612 /* restore R0 */
613
614 /* MRC p14,0,r0,c0,c5,0 */
615 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
616
617 arm11_run_instr_data_finish(arm11);
618
619
620 /* restore DSCR */
621
622 arm11_write_DSCR(arm11, R(DSCR));
623
624
625 /* restore rDTR */
626
627 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
628 {
629 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
630
631 arm11_add_IR(arm11, ARM11_EXTEST, -1);
632
633 scan_field_t chain5_fields[3];
634
635 u8 Ready = 0; /* ignored */
636 u8 Valid = 0; /* ignored */
637
638 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
639 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
640 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
641
642 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
643 }
644
645 arm11_record_register_history(arm11);
646 }
647
648 void arm11_record_register_history(arm11_common_t * arm11)
649 {
650 {size_t i;
651 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
652 {
653 arm11->reg_history[i].value = arm11->reg_values[i];
654 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
655
656 arm11->reg_list[i].valid = 0;
657 arm11->reg_list[i].dirty = 0;
658 }}
659 }
660
661
662 /* poll current target status */
663 int arm11_poll(struct target_s *target)
664 {
665 FNC_INFO;
666
667 arm11_common_t * arm11 = target->arch_info;
668
669 if (arm11->trst_active)
670 return ERROR_OK;
671
672 u32 dscr = arm11_read_DSCR(arm11);
673
674 LOG_DEBUG("DSCR %08x", dscr);
675
676 arm11_check_init(arm11, &dscr);
677
678 if (dscr & ARM11_DSCR_CORE_HALTED)
679 {
680 if (target->state != TARGET_HALTED)
681 {
682 enum target_state old_state = target->state;
683
684 LOG_DEBUG("enter TARGET_HALTED");
685 target->state = TARGET_HALTED;
686 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
687 arm11_on_enter_debug_state(arm11);
688
689 target_call_event_callbacks(target,
690 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
691 }
692 }
693 else
694 {
695 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
696 {
697 LOG_DEBUG("enter TARGET_RUNNING");
698 target->state = TARGET_RUNNING;
699 target->debug_reason = DBG_REASON_NOTHALTED;
700 }
701 }
702
703 return ERROR_OK;
704 }
705 /* architecture specific status reply */
706 int arm11_arch_state(struct target_s *target)
707 {
708 FNC_INFO_NOTIMPLEMENTED;
709
710 return ERROR_OK;
711 }
712
713
714 /* target request support */
715 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
716 {
717 FNC_INFO_NOTIMPLEMENTED;
718
719 return ERROR_OK;
720 }
721
722
723
724 /* target execution control */
725 int arm11_halt(struct target_s *target)
726 {
727 FNC_INFO;
728
729 arm11_common_t * arm11 = target->arch_info;
730
731 LOG_DEBUG("target->state: %s",
732 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
733
734 if (target->state == TARGET_UNKNOWN)
735 {
736 arm11->simulate_reset_on_next_halt = true;
737 }
738
739 if (target->state == TARGET_HALTED)
740 {
741 LOG_DEBUG("target was already halted");
742 return ERROR_OK;
743 }
744
745 if (arm11->trst_active)
746 {
747 arm11->halt_requested = true;
748 return ERROR_OK;
749 }
750
751 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
752
753 jtag_execute_queue();
754
755 u32 dscr;
756
757 while (1)
758 {
759 dscr = arm11_read_DSCR(arm11);
760
761 if (dscr & ARM11_DSCR_CORE_HALTED)
762 break;
763 }
764
765 arm11_on_enter_debug_state(arm11);
766
767 enum target_state old_state = target->state;
768
769 target->state = TARGET_HALTED;
770 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
771
772 target_call_event_callbacks(target,
773 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
774
775 return ERROR_OK;
776 }
777
778
779 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
780 {
781 FNC_INFO;
782
783 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
784 // current, address, handle_breakpoints, debug_execution);
785
786 arm11_common_t * arm11 = target->arch_info;
787
788 LOG_DEBUG("target->state: %s",
789 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
790
791
792 if (target->state != TARGET_HALTED)
793 {
794 LOG_ERROR("Target not halted");
795 return ERROR_TARGET_NOT_HALTED;
796 }
797
798 if (!current)
799 R(PC) = address;
800
801 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
802
803 /* clear breakpoints/watchpoints and VCR*/
804 arm11_sc7_clear_vbw(arm11);
805
806 /* Set up breakpoints */
807 if (!debug_execution)
808 {
809 /* check if one matches PC and step over it if necessary */
810
811 breakpoint_t * bp;
812
813 for (bp = target->breakpoints; bp; bp = bp->next)
814 {
815 if (bp->address == R(PC))
816 {
817 LOG_DEBUG("must step over %08x", bp->address);
818 arm11_step(target, 1, 0, 0);
819 break;
820 }
821 }
822
823 /* set all breakpoints */
824
825 size_t brp_num = 0;
826
827 for (bp = target->breakpoints; bp; bp = bp->next)
828 {
829 arm11_sc7_action_t brp[2];
830
831 brp[0].write = 1;
832 brp[0].address = ARM11_SC7_BVR0 + brp_num;
833 brp[0].value = bp->address;
834 brp[1].write = 1;
835 brp[1].address = ARM11_SC7_BCR0 + brp_num;
836 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
837
838 arm11_sc7_run(arm11, brp, asizeof(brp));
839
840 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
841
842 brp_num++;
843 }
844
845 arm11_sc7_set_vcr(arm11, arm11_vcr);
846 }
847
848
849 arm11_leave_debug_state(arm11);
850
851 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
852
853 jtag_execute_queue();
854
855 while (1)
856 {
857 u32 dscr = arm11_read_DSCR(arm11);
858
859 LOG_DEBUG("DSCR %08x", dscr);
860
861 if (dscr & ARM11_DSCR_CORE_RESTARTED)
862 break;
863 }
864
865 if (!debug_execution)
866 {
867 target->state = TARGET_RUNNING;
868 target->debug_reason = DBG_REASON_NOTHALTED;
869 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
870 }
871 else
872 {
873 target->state = TARGET_DEBUG_RUNNING;
874 target->debug_reason = DBG_REASON_NOTHALTED;
875 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
876 }
877
878 return ERROR_OK;
879 }
880
881 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
882 {
883 FNC_INFO;
884
885 LOG_DEBUG("target->state: %s",
886 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
887
888 if (target->state != TARGET_HALTED)
889 {
890 LOG_WARNING("target was not halted");
891 return ERROR_TARGET_NOT_HALTED;
892 }
893
894 arm11_common_t * arm11 = target->arch_info;
895
896 if (!current)
897 R(PC) = address;
898
899 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
900
901 /** \todo TODO: Thumb not supported here */
902
903 u32 next_instruction;
904
905 arm11_read_memory_word(arm11, R(PC), &next_instruction);
906
907 /* skip over BKPT */
908 if ((next_instruction & 0xFFF00070) == 0xe1200070)
909 {
910 R(PC) += 4;
911 arm11->reg_list[ARM11_RC_PC].valid = 1;
912 arm11->reg_list[ARM11_RC_PC].dirty = 0;
913 LOG_INFO("Skipping BKPT");
914 }
915 /* skip over Wait for interrupt / Standby */
916 /* mcr 15, 0, r?, cr7, cr0, {4} */
917 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
918 {
919 R(PC) += 4;
920 arm11->reg_list[ARM11_RC_PC].valid = 1;
921 arm11->reg_list[ARM11_RC_PC].dirty = 0;
922 LOG_INFO("Skipping WFI");
923 }
924 /* ignore B to self */
925 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
926 {
927 LOG_INFO("Not stepping jump to self");
928 }
929 else
930 {
931 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
932 * with this. */
933
934 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
935 * the VCR might be something worth looking into. */
936
937
938 /* Set up breakpoint for stepping */
939
940 arm11_sc7_action_t brp[2];
941
942 brp[0].write = 1;
943 brp[0].address = ARM11_SC7_BVR0;
944 brp[0].value = R(PC);
945 brp[1].write = 1;
946 brp[1].address = ARM11_SC7_BCR0;
947 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
948
949 arm11_sc7_run(arm11, brp, asizeof(brp));
950
951 /* resume */
952
953 arm11_leave_debug_state(arm11);
954
955 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
956
957 jtag_execute_queue();
958
959 /** \todo TODO: add a timeout */
960
961 /* wait for halt */
962
963 while (1)
964 {
965 u32 dscr = arm11_read_DSCR(arm11);
966
967 LOG_DEBUG("DSCR %08x", dscr);
968
969 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
970 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
971 break;
972 }
973
974 /* clear breakpoint */
975 arm11_sc7_clear_vbw(arm11);
976
977 /* save state */
978 arm11_on_enter_debug_state(arm11);
979 }
980
981 // target->state = TARGET_HALTED;
982 target->debug_reason = DBG_REASON_SINGLESTEP;
983
984 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
985
986 return ERROR_OK;
987 }
988
989
990 /* target reset control */
991 int arm11_assert_reset(struct target_s *target)
992 {
993 FNC_INFO;
994
995 #if 0
996 /* assert reset lines */
997 /* resets only the DBGTAP, not the ARM */
998
999 jtag_add_reset(1, 0);
1000 jtag_add_sleep(5000);
1001
1002 arm11_common_t * arm11 = target->arch_info;
1003 arm11->trst_active = true;
1004 #endif
1005
1006 if (target->reset_halt)
1007 {
1008 int retval;
1009 if ((retval = target_halt(target))!=ERROR_OK)
1010 return retval;
1011 }
1012
1013 return ERROR_OK;
1014 }
1015
1016 int arm11_deassert_reset(struct target_s *target)
1017 {
1018 FNC_INFO;
1019
1020 #if 0
1021 LOG_DEBUG("target->state: %s",
1022 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1023
1024
1025 /* deassert reset lines */
1026 jtag_add_reset(0, 0);
1027
1028 arm11_common_t * arm11 = target->arch_info;
1029 arm11->trst_active = false;
1030
1031 if (arm11->halt_requested)
1032 return arm11_halt(target);
1033 #endif
1034
1035 return ERROR_OK;
1036 }
1037
1038 int arm11_soft_reset_halt(struct target_s *target)
1039 {
1040 FNC_INFO_NOTIMPLEMENTED;
1041
1042 return ERROR_OK;
1043 }
1044
1045
1046
1047 /* target register access for gdb */
1048 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1049 {
1050 FNC_INFO;
1051
1052 arm11_common_t * arm11 = target->arch_info;
1053
1054 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1055 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1056
1057 {size_t i;
1058 for (i = 16; i < 24; i++)
1059 {
1060 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1061 }}
1062
1063 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1064
1065
1066 {size_t i;
1067 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1068 {
1069 if (arm11_reg_defs[i].gdb_num == -1)
1070 continue;
1071
1072 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1073 }}
1074
1075 return ERROR_OK;
1076 }
1077
1078
1079 /* target memory access
1080 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1081 * count: number of items of <size>
1082 */
1083 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1084 {
1085 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1086
1087 FNC_INFO;
1088
1089 if (target->state != TARGET_HALTED)
1090 {
1091 LOG_WARNING("target was not halted");
1092 return ERROR_TARGET_NOT_HALTED;
1093 }
1094
1095 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1096
1097 arm11_common_t * arm11 = target->arch_info;
1098
1099 arm11_run_instr_data_prepare(arm11);
1100
1101 /* MRC p14,0,r0,c0,c5,0 */
1102 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1103
1104 switch (size)
1105 {
1106 case 1:
1107 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1108 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1109
1110 {size_t i;
1111 for (i = 0; i < count; i++)
1112 {
1113 /* ldrb r1, [r0], #1 */
1114 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1115
1116 u32 res;
1117 /* MCR p14,0,R1,c0,c5,0 */
1118 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1119
1120 *buffer++ = res;
1121 }}
1122
1123 break;
1124
1125 case 2:
1126 {
1127 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1128
1129 u16 * buf16 = (u16*)buffer;
1130
1131 {size_t i;
1132 for (i = 0; i < count; i++)
1133 {
1134 /* ldrh r1, [r0], #2 */
1135 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1136
1137 u32 res;
1138
1139 /* MCR p14,0,R1,c0,c5,0 */
1140 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1141
1142 *buf16++ = res;
1143 }}
1144
1145 break;
1146 }
1147
1148 case 4:
1149
1150 /* LDC p14,c5,[R0],#4 */
1151 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1152 break;
1153 }
1154
1155 arm11_run_instr_data_finish(arm11);
1156
1157 return ERROR_OK;
1158 }
1159
1160 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1161 {
1162 FNC_INFO;
1163
1164 if (target->state != TARGET_HALTED)
1165 {
1166 LOG_WARNING("target was not halted");
1167 return ERROR_TARGET_NOT_HALTED;
1168 }
1169
1170 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1171
1172 arm11_common_t * arm11 = target->arch_info;
1173
1174 arm11_run_instr_data_prepare(arm11);
1175
1176 /* MRC p14,0,r0,c0,c5,0 */
1177 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1178
1179 switch (size)
1180 {
1181 case 1:
1182 {
1183 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1184
1185 {size_t i;
1186 for (i = 0; i < count; i++)
1187 {
1188 /* MRC p14,0,r1,c0,c5,0 */
1189 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1190
1191 /* strb r1, [r0], #1 */
1192 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1193 }}
1194
1195 break;
1196 }
1197
1198 case 2:
1199 {
1200 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1201
1202 u16 * buf16 = (u16*)buffer;
1203
1204 {size_t i;
1205 for (i = 0; i < count; i++)
1206 {
1207 /* MRC p14,0,r1,c0,c5,0 */
1208 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1209
1210 /* strh r1, [r0], #2 */
1211 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1212 }}
1213
1214 break;
1215 }
1216
1217 case 4:
1218 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1219
1220 if (!arm11_config_memwrite_burst)
1221 {
1222 /* STC p14,c5,[R0],#4 */
1223 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1224 }
1225 else
1226 {
1227 /* STC p14,c5,[R0],#4 */
1228 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1229 }
1230
1231 break;
1232 }
1233
1234 #if 1
1235 /* r0 verification */
1236 {
1237 u32 r0;
1238
1239 /* MCR p14,0,R0,c0,c5,0 */
1240 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1241
1242 if (address + size * count != r0)
1243 {
1244 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1245
1246 if (arm11_config_memwrite_burst)
1247 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1248
1249 if (arm11_config_memwrite_error_fatal)
1250 return ERROR_FAIL;
1251 }
1252 }
1253 #endif
1254
1255
1256 arm11_run_instr_data_finish(arm11);
1257
1258
1259
1260
1261 return ERROR_OK;
1262 }
1263
1264
1265 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1266 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1267 {
1268 FNC_INFO;
1269
1270 if (target->state != TARGET_HALTED)
1271 {
1272 LOG_WARNING("target was not halted");
1273 return ERROR_TARGET_NOT_HALTED;
1274 }
1275
1276 return arm11_write_memory(target, address, 4, count, buffer);
1277 }
1278
1279
1280 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1281 {
1282 FNC_INFO_NOTIMPLEMENTED;
1283
1284 return ERROR_OK;
1285 }
1286
1287
1288 /* target break-/watchpoint control
1289 * rw: 0 = write, 1 = read, 2 = access
1290 */
1291 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1292 {
1293 FNC_INFO;
1294
1295 arm11_common_t * arm11 = target->arch_info;
1296
1297 #if 0
1298 if (breakpoint->type == BKPT_SOFT)
1299 {
1300 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1301 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1302 }
1303 #endif
1304
1305 if (!arm11->free_brps)
1306 {
1307 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1309 }
1310
1311 if (breakpoint->length != 4)
1312 {
1313 LOG_INFO("only breakpoints of four bytes length supported");
1314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1315 }
1316
1317 arm11->free_brps--;
1318
1319 return ERROR_OK;
1320 }
1321
1322 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1323 {
1324 FNC_INFO;
1325
1326 arm11_common_t * arm11 = target->arch_info;
1327
1328 arm11->free_brps++;
1329
1330 return ERROR_OK;
1331 }
1332
1333 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1334 {
1335 FNC_INFO_NOTIMPLEMENTED;
1336
1337 return ERROR_OK;
1338 }
1339
1340 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1341 {
1342 FNC_INFO_NOTIMPLEMENTED;
1343
1344 return ERROR_OK;
1345 }
1346
1347 // HACKHACKHACK - FIXME mode/state
1348 /* target algorithm support */
1349 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1350 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1351 int timeout_ms, void *arch_info)
1352 {
1353 arm11_common_t *arm11 = target->arch_info;
1354 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1355 // enum armv4_5_state core_state = arm11->core_state;
1356 // enum armv4_5_mode core_mode = arm11->core_mode;
1357 u32 context[16];
1358 u32 cpsr;
1359 int exit_breakpoint_size = 0;
1360 int i;
1361 int retval = ERROR_OK;
1362 LOG_DEBUG("Running algorithm");
1363
1364 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1365 {
1366 LOG_ERROR("current target isn't an ARMV4/5 target");
1367 return ERROR_TARGET_INVALID;
1368 }
1369
1370 if (target->state != TARGET_HALTED)
1371 {
1372 LOG_WARNING("target not halted");
1373 return ERROR_TARGET_NOT_HALTED;
1374 }
1375
1376 // FIXME
1377 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1378 // return ERROR_FAIL;
1379
1380 // Save regs
1381 for (i = 0; i < 16; i++)
1382 {
1383 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1384 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1385 }
1386
1387 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1388 LOG_DEBUG("Save CPSR: 0x%x",i,cpsr);
1389
1390 for (i = 0; i < num_mem_params; i++)
1391 {
1392 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1393 }
1394
1395 // Set register parameters
1396 for (i = 0; i < num_reg_params; i++)
1397 {
1398 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1399 u32 val;
1400 if (!reg)
1401 {
1402 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1403 exit(-1);
1404 }
1405
1406 if (reg->size != reg_params[i].size)
1407 {
1408 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1409 exit(-1);
1410 }
1411 arm11_set_reg(reg,reg_params[i].value);
1412 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1413 }
1414
1415 exit_breakpoint_size = 4;
1416
1417 /* arm11->core_state = arm11_algorithm_info->core_state;
1418 if (arm11->core_state == ARMV4_5_STATE_ARM)
1419 exit_breakpoint_size = 4;
1420 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1421 exit_breakpoint_size = 2;
1422 else
1423 {
1424 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1425 exit(-1);
1426 }
1427 */
1428 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1429 {
1430 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1431 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1432 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1433 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1434 }
1435
1436 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1437 {
1438 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1439 retval = ERROR_TARGET_FAILURE;
1440 goto restore;
1441 }
1442
1443 target_resume(target, 0, entry_point, 1, 0); // no debug, otherwise breakpoint is not set
1444
1445 target_wait_state(target, TARGET_HALTED, timeout_ms);
1446 if (target->state != TARGET_HALTED)
1447 {
1448 if ((retval=target_halt(target))!=ERROR_OK)
1449 return retval;
1450 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
1451 {
1452 return retval;
1453 }
1454 retval = ERROR_TARGET_TIMEOUT;
1455 goto del_breakpoint;
1456 }
1457
1458 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1459 {
1460 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1461 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1462 retval = ERROR_TARGET_TIMEOUT;
1463 goto del_breakpoint;
1464 }
1465
1466 for (i = 0; i < num_mem_params; i++)
1467 {
1468 if (mem_params[i].direction != PARAM_OUT)
1469 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1470 }
1471
1472 for (i = 0; i < num_reg_params; i++)
1473 {
1474 if (reg_params[i].direction != PARAM_OUT)
1475 {
1476 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1477 if (!reg)
1478 {
1479 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1480 exit(-1);
1481 }
1482
1483 if (reg->size != reg_params[i].size)
1484 {
1485 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1486 exit(-1);
1487 }
1488
1489 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1490 }
1491 }
1492
1493 del_breakpoint:
1494 breakpoint_remove(target, exit_point);
1495
1496 restore:
1497 // Restore context
1498 for (i = 0; i < 16; i++)
1499 {
1500 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1501 arm11->reg_list[i].name, context[i]);
1502 arm11_set_reg(&arm11->reg_list[i], &context[i]);
1503 }
1504 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1505 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], &cpsr);
1506
1507 // arm11->core_state = core_state;
1508 // arm11->core_mode = core_mode;
1509
1510 return retval;
1511 }
1512
1513 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1514 {
1515 FNC_INFO;
1516
1517 NEW(arm11_common_t, arm11, 1);
1518
1519 arm11->target = target;
1520
1521 /* prepare JTAG information for the new target */
1522 arm11->jtag_info.chain_pos = target->chain_position;
1523 arm11->jtag_info.scann_size = 5;
1524
1525 arm_jtag_setup_connection(&arm11->jtag_info);
1526
1527 jtag_device_t *device = jtag_get_device(target->chain_position);
1528
1529 if (device->ir_length != 5)
1530 {
1531 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1532 return ERROR_COMMAND_SYNTAX_ERROR;
1533 }
1534
1535 target->arch_info = arm11;
1536
1537 return ERROR_OK;
1538 }
1539
1540 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1541 {
1542 /* Initialize anything we can set up without talking to the target */
1543 return ERROR_OK;
1544 }
1545
1546 /* talk to the target and set things up */
1547 int arm11_examine(struct target_s *target)
1548 {
1549 FNC_INFO;
1550 int retval;
1551
1552 arm11_common_t * arm11 = target->arch_info;
1553
1554 /* check IDCODE */
1555
1556 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1557
1558 scan_field_t idcode_field;
1559
1560 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1561
1562 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1563
1564 /* check DIDR */
1565
1566 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1567
1568 arm11_add_IR(arm11, ARM11_INTEST, -1);
1569
1570 scan_field_t chain0_fields[2];
1571
1572 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1573 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1574
1575 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1576
1577 if ((retval=jtag_execute_queue())!=ERROR_OK)
1578 return retval;
1579
1580
1581 switch (arm11->device_id & 0x0FFFF000)
1582 {
1583 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1584 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1585 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1586 default:
1587 {
1588 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1589 return ERROR_FAIL;
1590 }
1591 }
1592
1593 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1594
1595 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1596 arm11->debug_version != ARM11_DEBUG_V61)
1597 {
1598 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1599 return ERROR_FAIL;
1600 }
1601
1602
1603 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1604 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1605
1606 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1607 arm11->free_brps = arm11->brp;
1608 arm11->free_wrps = arm11->wrp;
1609
1610 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1611 arm11->device_id,
1612 arm11->implementor,
1613 arm11->didr);
1614
1615 arm11_build_reg_cache(target);
1616
1617
1618 /* as a side-effect this reads DSCR and thus
1619 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1620 * as suggested by the spec.
1621 */
1622
1623 arm11_check_init(arm11, NULL);
1624
1625 target->type->examined = 1;
1626
1627 return ERROR_OK;
1628 }
1629
1630 int arm11_quit(void)
1631 {
1632 FNC_INFO_NOTIMPLEMENTED;
1633
1634 return ERROR_OK;
1635 }
1636
1637 /** Load a register that is marked !valid in the register cache */
1638 int arm11_get_reg(reg_t *reg)
1639 {
1640 FNC_INFO;
1641
1642 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1643
1644 if (target->state != TARGET_HALTED)
1645 {
1646 LOG_WARNING("target was not halted");
1647 return ERROR_TARGET_NOT_HALTED;
1648 }
1649
1650 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1651
1652 #if 0
1653 arm11_common_t *arm11 = target->arch_info;
1654 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1655 #endif
1656
1657 return ERROR_OK;
1658 }
1659
1660 /** Change a value in the register cache */
1661 int arm11_set_reg(reg_t *reg, u8 *buf)
1662 {
1663 FNC_INFO;
1664
1665 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1666 arm11_common_t *arm11 = target->arch_info;
1667 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1668
1669 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1670 reg->valid = 1;
1671 reg->dirty = 1;
1672
1673 return ERROR_OK;
1674 }
1675
1676
1677 void arm11_build_reg_cache(target_t *target)
1678 {
1679 arm11_common_t *arm11 = target->arch_info;
1680
1681 NEW(reg_cache_t, cache, 1);
1682 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1683 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1684
1685 if (arm11_regs_arch_type == -1)
1686 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1687
1688 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1689 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1690
1691 arm11->reg_list = reg_list;
1692
1693 /* Build the process context cache */
1694 cache->name = "arm11 registers";
1695 cache->next = NULL;
1696 cache->reg_list = reg_list;
1697 cache->num_regs = ARM11_REGCACHE_COUNT;
1698
1699 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1700 (*cache_p) = cache;
1701
1702 arm11->core_cache = cache;
1703 // armv7m->process_context = cache;
1704
1705 size_t i;
1706
1707 /* Not very elegant assertion */
1708 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1709 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1710 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1711 {
1712 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1713 exit(-1);
1714 }
1715
1716 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1717 {
1718 reg_t * r = reg_list + i;
1719 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1720 arm11_reg_state_t * rs = arm11_reg_states + i;
1721
1722 r->name = rd->name;
1723 r->size = 32;
1724 r->value = (u8 *)(arm11->reg_values + i);
1725 r->dirty = 0;
1726 r->valid = 0;
1727 r->bitfield_desc = NULL;
1728 r->num_bitfields = 0;
1729 r->arch_type = arm11_regs_arch_type;
1730 r->arch_info = rs;
1731
1732 rs->def_index = i;
1733 rs->target = target;
1734 }
1735 }
1736
1737
1738
1739 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1740 {
1741 if (argc == 0)
1742 {
1743 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1744 return ERROR_OK;
1745 }
1746
1747 if (argc != 1)
1748 return ERROR_COMMAND_SYNTAX_ERROR;
1749
1750 switch (args[0][0])
1751 {
1752 case '0': /* 0 */
1753 case 'f': /* false */
1754 case 'F':
1755 case 'd': /* disable */
1756 case 'D':
1757 *var = false;
1758 break;
1759
1760 case '1': /* 1 */
1761 case 't': /* true */
1762 case 'T':
1763 case 'e': /* enable */
1764 case 'E':
1765 *var = true;
1766 break;
1767 }
1768
1769 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1770
1771 return ERROR_OK;
1772 }
1773
1774
1775 #define BOOL_WRAPPER(name, print_name) \
1776 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1777 { \
1778 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1779 }
1780
1781 #define RC_TOP(name, descr, more) \
1782 { \
1783 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1784 command_t * top_cmd = new_cmd; \
1785 more \
1786 }
1787
1788 #define RC_FINAL(name, descr, handler) \
1789 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1790
1791 #define RC_FINAL_BOOL(name, descr, var) \
1792 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1793
1794
1795 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1796 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1797
1798
1799 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1800 {
1801 if (argc == 1)
1802 {
1803 arm11_vcr = strtoul(args[0], NULL, 0);
1804 }
1805 else if (argc != 0)
1806 {
1807 return ERROR_COMMAND_SYNTAX_ERROR;
1808 }
1809
1810 LOG_INFO("VCR 0x%08X", arm11_vcr);
1811 return ERROR_OK;
1812 }
1813
1814 const u32 arm11_coproc_instruction_limits[] =
1815 {
1816 15, /* coprocessor */
1817 7, /* opcode 1 */
1818 15, /* CRn */
1819 15, /* CRm */
1820 7, /* opcode 2 */
1821 0xFFFFFFFF, /* value */
1822 };
1823
1824 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1825 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1826
1827
1828 arm11_common_t * arm11_find_target(const char * arg)
1829 {
1830 size_t jtag_target = strtoul(arg, NULL, 0);
1831
1832 {target_t * t;
1833 for (t = all_targets; t; t = t->next)
1834 {
1835 if (strcmp(t->type->name,"arm11"))
1836 continue;
1837
1838 arm11_common_t * arm11 = t->arch_info;
1839
1840 if (arm11->jtag_info.chain_pos != jtag_target)
1841 continue;
1842
1843 return arm11;
1844 }}
1845
1846 return 0;
1847 }
1848
1849 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1850 {
1851 if (argc != (read ? 6 : 7))
1852 {
1853 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1854 return -1;
1855 }
1856
1857 arm11_common_t * arm11 = arm11_find_target(args[0]);
1858
1859 if (!arm11)
1860 {
1861 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1862 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1863
1864 return -1;
1865
1866 }
1867
1868 if (arm11->target->state != TARGET_HALTED)
1869 {
1870 LOG_WARNING("target was not halted");
1871 return ERROR_TARGET_NOT_HALTED;
1872 }
1873
1874
1875 u32 values[6];
1876
1877 {size_t i;
1878 for (i = 0; i < (read ? 5 : 6); i++)
1879 {
1880 values[i] = strtoul(args[i + 1], NULL, 0);
1881
1882 if (values[i] > arm11_coproc_instruction_limits[i])
1883 {
1884 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1885 (long)(i + 2), arm11_coproc_instruction_limits[i],
1886 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1887 return -1;
1888 }
1889 }}
1890
1891 u32 instr = 0xEE000010 |
1892 (values[0] << 8) |
1893 (values[1] << 21) |
1894 (values[2] << 16) |
1895 (values[3] << 0) |
1896 (values[4] << 5);
1897
1898 if (read)
1899 instr |= 0x00100000;
1900
1901
1902 arm11_run_instr_data_prepare(arm11);
1903
1904 if (read)
1905 {
1906 u32 result;
1907 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1908
1909 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1910 values[0], values[1], values[2], values[3], values[4], result, result);
1911 }
1912 else
1913 {
1914 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1915
1916 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1917 values[0], values[1],
1918 values[5],
1919 values[2], values[3], values[4]);
1920 }
1921
1922 arm11_run_instr_data_finish(arm11);
1923
1924
1925 return ERROR_OK;
1926 }
1927
1928 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1929 {
1930 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1931 }
1932
1933 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1934 {
1935 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1936 }
1937
1938 int arm11_register_commands(struct command_context_s *cmd_ctx)
1939 {
1940 FNC_INFO;
1941
1942 command_t * top_cmd = NULL;
1943
1944 RC_TOP( "arm11", "arm11 specific commands",
1945
1946 RC_TOP( "memwrite", "Control memory write transfer mode",
1947
1948 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1949 memwrite_burst)
1950
1951 RC_FINAL_BOOL( "error_fatal",
1952 "Terminate program if transfer error was found (default: enabled)",
1953 memwrite_error_fatal)
1954 )
1955
1956 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1957 arm11_handle_vcr)
1958
1959 RC_FINAL( "mrc", "Read Coprocessor register",
1960 arm11_handle_mrc)
1961
1962 RC_FINAL( "mcr", "Write Coprocessor register",
1963 arm11_handle_mcr)
1964 )
1965
1966 return ERROR_OK;
1967 }
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