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sharpen error propagation a wee bit.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "arm11.h"
27 #include "jtag.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32
33 #if 0
34 #define _DEBUG_INSTRUCTION_EXECUTION_
35 #endif
36
37
38 #if 0
39 #define FNC_INFO LOG_DEBUG("-")
40 #else
41 #define FNC_INFO
42 #endif
43
44 #if 1
45 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
46 #else
47 #define FNC_INFO_NOTIMPLEMENTED
48 #endif
49
50 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
51
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 u32 arm11_vcr = 0;
56
57
58 #define ARM11_HANDLER(x) \
59 .x = arm11_##x
60
61 target_type_t arm11_target =
62 {
63 .name = "arm11",
64
65 ARM11_HANDLER(poll),
66 ARM11_HANDLER(arch_state),
67
68 ARM11_HANDLER(target_request_data),
69
70 ARM11_HANDLER(halt),
71 ARM11_HANDLER(resume),
72 ARM11_HANDLER(step),
73
74 ARM11_HANDLER(assert_reset),
75 ARM11_HANDLER(deassert_reset),
76 ARM11_HANDLER(soft_reset_halt),
77
78 ARM11_HANDLER(get_gdb_reg_list),
79
80 ARM11_HANDLER(read_memory),
81 ARM11_HANDLER(write_memory),
82
83 ARM11_HANDLER(bulk_write_memory),
84
85 ARM11_HANDLER(checksum_memory),
86
87 ARM11_HANDLER(add_breakpoint),
88 ARM11_HANDLER(remove_breakpoint),
89 ARM11_HANDLER(add_watchpoint),
90 ARM11_HANDLER(remove_watchpoint),
91
92 ARM11_HANDLER(run_algorithm),
93
94 ARM11_HANDLER(register_commands),
95 ARM11_HANDLER(target_command),
96 ARM11_HANDLER(init_target),
97 ARM11_HANDLER(examine),
98 ARM11_HANDLER(quit),
99 };
100
101 int arm11_regs_arch_type = -1;
102
103
104 enum arm11_regtype
105 {
106 ARM11_REGISTER_CORE,
107 ARM11_REGISTER_CPSR,
108
109 ARM11_REGISTER_FX,
110 ARM11_REGISTER_FPS,
111
112 ARM11_REGISTER_FIQ,
113 ARM11_REGISTER_SVC,
114 ARM11_REGISTER_ABT,
115 ARM11_REGISTER_IRQ,
116 ARM11_REGISTER_UND,
117 ARM11_REGISTER_MON,
118
119 ARM11_REGISTER_SPSR_FIQ,
120 ARM11_REGISTER_SPSR_SVC,
121 ARM11_REGISTER_SPSR_ABT,
122 ARM11_REGISTER_SPSR_IRQ,
123 ARM11_REGISTER_SPSR_UND,
124 ARM11_REGISTER_SPSR_MON,
125
126 /* debug regs */
127 ARM11_REGISTER_DSCR,
128 ARM11_REGISTER_WDTR,
129 ARM11_REGISTER_RDTR,
130 };
131
132
133 typedef struct arm11_reg_defs_s
134 {
135 char * name;
136 u32 num;
137 int gdb_num;
138 enum arm11_regtype type;
139 } arm11_reg_defs_t;
140
141 /* update arm11_regcache_ids when changing this */
142 static const arm11_reg_defs_t arm11_reg_defs[] =
143 {
144 {"r0", 0, 0, ARM11_REGISTER_CORE},
145 {"r1", 1, 1, ARM11_REGISTER_CORE},
146 {"r2", 2, 2, ARM11_REGISTER_CORE},
147 {"r3", 3, 3, ARM11_REGISTER_CORE},
148 {"r4", 4, 4, ARM11_REGISTER_CORE},
149 {"r5", 5, 5, ARM11_REGISTER_CORE},
150 {"r6", 6, 6, ARM11_REGISTER_CORE},
151 {"r7", 7, 7, ARM11_REGISTER_CORE},
152 {"r8", 8, 8, ARM11_REGISTER_CORE},
153 {"r9", 9, 9, ARM11_REGISTER_CORE},
154 {"r10", 10, 10, ARM11_REGISTER_CORE},
155 {"r11", 11, 11, ARM11_REGISTER_CORE},
156 {"r12", 12, 12, ARM11_REGISTER_CORE},
157 {"sp", 13, 13, ARM11_REGISTER_CORE},
158 {"lr", 14, 14, ARM11_REGISTER_CORE},
159 {"pc", 15, 15, ARM11_REGISTER_CORE},
160
161 #if ARM11_REGCACHE_FREGS
162 {"f0", 0, 16, ARM11_REGISTER_FX},
163 {"f1", 1, 17, ARM11_REGISTER_FX},
164 {"f2", 2, 18, ARM11_REGISTER_FX},
165 {"f3", 3, 19, ARM11_REGISTER_FX},
166 {"f4", 4, 20, ARM11_REGISTER_FX},
167 {"f5", 5, 21, ARM11_REGISTER_FX},
168 {"f6", 6, 22, ARM11_REGISTER_FX},
169 {"f7", 7, 23, ARM11_REGISTER_FX},
170 {"fps", 0, 24, ARM11_REGISTER_FPS},
171 #endif
172
173 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
174
175 #if ARM11_REGCACHE_MODEREGS
176 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
177 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
178 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
179 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
180 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
181 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
182 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
183 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
184
185 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
186 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
187 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
188
189 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
190 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
191 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
192
193 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
194 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
195 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
196
197 {"r13_und", 13, -1, ARM11_REGISTER_UND},
198 {"r14_und", 14, -1, ARM11_REGISTER_UND},
199 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
200
201 /* ARM1176 only */
202 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
203 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
204 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
205 #endif
206
207 /* Debug Registers */
208 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
209 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
210 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
211 };
212
213 enum arm11_regcache_ids
214 {
215 ARM11_RC_R0,
216 ARM11_RC_RX = ARM11_RC_R0,
217
218 ARM11_RC_R1,
219 ARM11_RC_R2,
220 ARM11_RC_R3,
221 ARM11_RC_R4,
222 ARM11_RC_R5,
223 ARM11_RC_R6,
224 ARM11_RC_R7,
225 ARM11_RC_R8,
226 ARM11_RC_R9,
227 ARM11_RC_R10,
228 ARM11_RC_R11,
229 ARM11_RC_R12,
230 ARM11_RC_R13,
231 ARM11_RC_SP = ARM11_RC_R13,
232 ARM11_RC_R14,
233 ARM11_RC_LR = ARM11_RC_R14,
234 ARM11_RC_R15,
235 ARM11_RC_PC = ARM11_RC_R15,
236
237 #if ARM11_REGCACHE_FREGS
238 ARM11_RC_F0,
239 ARM11_RC_FX = ARM11_RC_F0,
240 ARM11_RC_F1,
241 ARM11_RC_F2,
242 ARM11_RC_F3,
243 ARM11_RC_F4,
244 ARM11_RC_F5,
245 ARM11_RC_F6,
246 ARM11_RC_F7,
247 ARM11_RC_FPS,
248 #endif
249
250 ARM11_RC_CPSR,
251
252 #if ARM11_REGCACHE_MODEREGS
253 ARM11_RC_R8_FIQ,
254 ARM11_RC_R9_FIQ,
255 ARM11_RC_R10_FIQ,
256 ARM11_RC_R11_FIQ,
257 ARM11_RC_R12_FIQ,
258 ARM11_RC_R13_FIQ,
259 ARM11_RC_R14_FIQ,
260 ARM11_RC_SPSR_FIQ,
261
262 ARM11_RC_R13_SVC,
263 ARM11_RC_R14_SVC,
264 ARM11_RC_SPSR_SVC,
265
266 ARM11_RC_R13_ABT,
267 ARM11_RC_R14_ABT,
268 ARM11_RC_SPSR_ABT,
269
270 ARM11_RC_R13_IRQ,
271 ARM11_RC_R14_IRQ,
272 ARM11_RC_SPSR_IRQ,
273
274 ARM11_RC_R13_UND,
275 ARM11_RC_R14_UND,
276 ARM11_RC_SPSR_UND,
277
278 ARM11_RC_R13_MON,
279 ARM11_RC_R14_MON,
280 ARM11_RC_SPSR_MON,
281 #endif
282
283 ARM11_RC_DSCR,
284 ARM11_RC_WDTR,
285 ARM11_RC_RDTR,
286
287 ARM11_RC_MAX,
288 };
289
290 #define ARM11_GDB_REGISTER_COUNT 26
291
292 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
293
294 reg_t arm11_gdb_dummy_fp_reg =
295 {
296 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
297 };
298
299 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
300
301 reg_t arm11_gdb_dummy_fps_reg =
302 {
303 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
304 };
305
306
307
308 /** Check and if necessary take control of the system
309 *
310 * \param arm11 Target state variable.
311 * \param dscr If the current DSCR content is
312 * available a pointer to a word holding the
313 * DSCR can be passed. Otherwise use NULL.
314 */
315 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
316 {
317 FNC_INFO;
318
319 u32 dscr_local_tmp_copy;
320
321 if (!dscr)
322 {
323 dscr = &dscr_local_tmp_copy;
324 *dscr = arm11_read_DSCR(arm11);
325 }
326
327 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
328 {
329 LOG_DEBUG("Bringing target into debug mode");
330
331 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
332 arm11_write_DSCR(arm11, *dscr);
333
334 /* add further reset initialization here */
335
336 arm11->simulate_reset_on_next_halt = true;
337
338 if (*dscr & ARM11_DSCR_CORE_HALTED)
339 {
340 /** \todo TODO: this needs further scrutiny because
341 * arm11_on_enter_debug_state() never gets properly called
342 */
343
344 arm11->target->state = TARGET_HALTED;
345 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
346 }
347 else
348 {
349 arm11->target->state = TARGET_RUNNING;
350 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
351 }
352
353 arm11_sc7_clear_vbw(arm11);
354 }
355 }
356
357
358
359 #define R(x) \
360 (arm11->reg_values[ARM11_RC_##x])
361
362 /** Save processor state.
363 *
364 * This is called when the HALT instruction has succeeded
365 * or on other occasions that stop the processor.
366 *
367 */
368 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
369 {
370 FNC_INFO;
371
372 {size_t i;
373 for(i = 0; i < asizeof(arm11->reg_values); i++)
374 {
375 arm11->reg_list[i].valid = 1;
376 arm11->reg_list[i].dirty = 0;
377 }}
378
379 /* Save DSCR */
380
381 R(DSCR) = arm11_read_DSCR(arm11);
382
383 /* Save wDTR */
384
385 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
386 {
387 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
388
389 arm11_add_IR(arm11, ARM11_INTEST, -1);
390
391 scan_field_t chain5_fields[3];
392
393 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
394 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
395 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
396
397 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
398 }
399 else
400 {
401 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
402 }
403
404
405 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
406 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
407 ARM1136 seems to require this to issue ITR's as well */
408
409 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
410
411 /* this executes JTAG queue: */
412
413 arm11_write_DSCR(arm11, new_dscr);
414
415
416 /* From the spec:
417 Before executing any instruction in debug state you have to drain the write buffer.
418 This ensures that no imprecise Data Aborts can return at a later point:*/
419
420 /** \todo TODO: Test drain write buffer. */
421
422 #if 0
423 while (1)
424 {
425 /* MRC p14,0,R0,c5,c10,0 */
426 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
427
428 /* mcr 15, 0, r0, cr7, cr10, {4} */
429 arm11_run_instr_no_data1(arm11, 0xee070f9a);
430
431 u32 dscr = arm11_read_DSCR(arm11);
432
433 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
434
435 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
436 {
437 arm11_run_instr_no_data1(arm11, 0xe320f000);
438
439 dscr = arm11_read_DSCR(arm11);
440
441 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
442
443 break;
444 }
445 }
446 #endif
447
448
449 arm11_run_instr_data_prepare(arm11);
450
451 /* save r0 - r14 */
452
453
454 /** \todo TODO: handle other mode registers */
455
456 {size_t i;
457 for (i = 0; i < 15; i++)
458 {
459 /* MCR p14,0,R?,c0,c5,0 */
460 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
461 }}
462
463
464 /* save rDTR */
465
466 /* check rDTRfull in DSCR */
467
468 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
469 {
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
472 }
473 else
474 {
475 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
476 }
477
478 /* save CPSR */
479
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
482
483 /* save PC */
484
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
487
488 /* adjust PC depending on ARM state */
489
490 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
491 {
492 arm11->reg_values[ARM11_RC_PC] -= 0;
493 }
494 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
495 {
496 arm11->reg_values[ARM11_RC_PC] -= 4;
497 }
498 else /* ARM state */
499 {
500 arm11->reg_values[ARM11_RC_PC] -= 8;
501 }
502
503 if (arm11->simulate_reset_on_next_halt)
504 {
505 arm11->simulate_reset_on_next_halt = false;
506
507 LOG_DEBUG("Reset c1 Control Register");
508
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
510
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
513
514 }
515
516 arm11_run_instr_data_finish(arm11);
517
518 arm11_dump_reg_changes(arm11);
519 }
520
521 void arm11_dump_reg_changes(arm11_common_t * arm11)
522 {
523 {size_t i;
524 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
525 {
526 if (!arm11->reg_list[i].valid)
527 {
528 if (arm11->reg_history[i].valid)
529 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
530 }
531 else
532 {
533 if (arm11->reg_history[i].valid)
534 {
535 if (arm11->reg_history[i].value != arm11->reg_values[i])
536 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
537 }
538 else
539 {
540 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
541 }
542 }
543 }}
544 }
545
546
547 /** Restore processor state
548 *
549 * This is called in preparation for the RESTART function.
550 *
551 */
552 void arm11_leave_debug_state(arm11_common_t * arm11)
553 {
554 FNC_INFO;
555
556 arm11_run_instr_data_prepare(arm11);
557
558 /** \todo TODO: handle other mode registers */
559
560 /* restore R1 - R14 */
561 {size_t i;
562 for (i = 1; i < 15; i++)
563 {
564 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
565 continue;
566
567 /* MRC p14,0,r?,c0,c5,0 */
568 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
569
570 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
571 }}
572
573 arm11_run_instr_data_finish(arm11);
574
575
576 /* spec says clear wDTR and rDTR; we assume they are clear as
577 otherwise our programming would be sloppy */
578
579 {
580 u32 DSCR = arm11_read_DSCR(arm11);
581
582 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
583 {
584 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
585 }
586 }
587
588 arm11_run_instr_data_prepare(arm11);
589
590 /* restore original wDTR */
591
592 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
593 {
594 /* MCR p14,0,R0,c0,c5,0 */
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
596 }
597
598 /* restore CPSR */
599
600 /* MSR CPSR,R0*/
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
602
603
604 /* restore PC */
605
606 /* MOV PC,R0 */
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
608
609
610 /* restore R0 */
611
612 /* MRC p14,0,r0,c0,c5,0 */
613 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
614
615 arm11_run_instr_data_finish(arm11);
616
617
618 /* restore DSCR */
619
620 arm11_write_DSCR(arm11, R(DSCR));
621
622
623 /* restore rDTR */
624
625 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
626 {
627 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
628
629 arm11_add_IR(arm11, ARM11_EXTEST, -1);
630
631 scan_field_t chain5_fields[3];
632
633 u8 Ready = 0; /* ignored */
634 u8 Valid = 0; /* ignored */
635
636 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
637 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
638 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
639
640 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
641 }
642
643 arm11_record_register_history(arm11);
644 }
645
646 void arm11_record_register_history(arm11_common_t * arm11)
647 {
648 {size_t i;
649 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
650 {
651 arm11->reg_history[i].value = arm11->reg_values[i];
652 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
653
654 arm11->reg_list[i].valid = 0;
655 arm11->reg_list[i].dirty = 0;
656 }}
657 }
658
659
660 /* poll current target status */
661 int arm11_poll(struct target_s *target)
662 {
663 FNC_INFO;
664
665 arm11_common_t * arm11 = target->arch_info;
666
667 if (arm11->trst_active)
668 return ERROR_OK;
669
670 u32 dscr = arm11_read_DSCR(arm11);
671
672 LOG_DEBUG("DSCR %08x", dscr);
673
674 arm11_check_init(arm11, &dscr);
675
676 if (dscr & ARM11_DSCR_CORE_HALTED)
677 {
678 if (target->state != TARGET_HALTED)
679 {
680 enum target_state old_state = target->state;
681
682 LOG_DEBUG("enter TARGET_HALTED");
683 target->state = TARGET_HALTED;
684 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
685 arm11_on_enter_debug_state(arm11);
686
687 target_call_event_callbacks(target,
688 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
689 }
690 }
691 else
692 {
693 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
694 {
695 LOG_DEBUG("enter TARGET_RUNNING");
696 target->state = TARGET_RUNNING;
697 target->debug_reason = DBG_REASON_NOTHALTED;
698 }
699 }
700
701 return ERROR_OK;
702 }
703 /* architecture specific status reply */
704 int arm11_arch_state(struct target_s *target)
705 {
706 FNC_INFO_NOTIMPLEMENTED;
707
708 return ERROR_OK;
709 }
710
711
712 /* target request support */
713 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
714 {
715 FNC_INFO_NOTIMPLEMENTED;
716
717 return ERROR_OK;
718 }
719
720
721
722 /* target execution control */
723 int arm11_halt(struct target_s *target)
724 {
725 FNC_INFO;
726
727 arm11_common_t * arm11 = target->arch_info;
728
729 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
730
731 if (target->state == TARGET_UNKNOWN)
732 {
733 arm11->simulate_reset_on_next_halt = true;
734 }
735
736 if (target->state == TARGET_HALTED)
737 {
738 LOG_DEBUG("target was already halted");
739 return ERROR_OK;
740 }
741
742 if (arm11->trst_active)
743 {
744 arm11->halt_requested = true;
745 return ERROR_OK;
746 }
747
748 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
749
750 jtag_execute_queue();
751
752 u32 dscr;
753
754 while (1)
755 {
756 dscr = arm11_read_DSCR(arm11);
757
758 if (dscr & ARM11_DSCR_CORE_HALTED)
759 break;
760 }
761
762 arm11_on_enter_debug_state(arm11);
763
764 enum target_state old_state = target->state;
765
766 target->state = TARGET_HALTED;
767 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
768
769 target_call_event_callbacks(target,
770 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
771
772 return ERROR_OK;
773 }
774
775
776 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
777 {
778 FNC_INFO;
779
780 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
781 // current, address, handle_breakpoints, debug_execution);
782
783 arm11_common_t * arm11 = target->arch_info;
784
785 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
786
787 if (target->state != TARGET_HALTED)
788 {
789 LOG_ERROR("Target not halted");
790 return ERROR_TARGET_NOT_HALTED;
791 }
792
793 if (!current)
794 R(PC) = address;
795
796 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
797
798 /* clear breakpoints/watchpoints and VCR*/
799 arm11_sc7_clear_vbw(arm11);
800
801 /* Set up breakpoints */
802 if (!debug_execution)
803 {
804 /* check if one matches PC and step over it if necessary */
805
806 breakpoint_t * bp;
807
808 for (bp = target->breakpoints; bp; bp = bp->next)
809 {
810 if (bp->address == R(PC))
811 {
812 LOG_DEBUG("must step over %08x", bp->address);
813 arm11_step(target, 1, 0, 0);
814 break;
815 }
816 }
817
818 /* set all breakpoints */
819
820 size_t brp_num = 0;
821
822 for (bp = target->breakpoints; bp; bp = bp->next)
823 {
824 arm11_sc7_action_t brp[2];
825
826 brp[0].write = 1;
827 brp[0].address = ARM11_SC7_BVR0 + brp_num;
828 brp[0].value = bp->address;
829 brp[1].write = 1;
830 brp[1].address = ARM11_SC7_BCR0 + brp_num;
831 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
832
833 arm11_sc7_run(arm11, brp, asizeof(brp));
834
835 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
836
837 brp_num++;
838 }
839
840 arm11_sc7_set_vcr(arm11, arm11_vcr);
841 }
842
843
844 arm11_leave_debug_state(arm11);
845
846 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
847
848 jtag_execute_queue();
849
850 while (1)
851 {
852 u32 dscr = arm11_read_DSCR(arm11);
853
854 LOG_DEBUG("DSCR %08x", dscr);
855
856 if (dscr & ARM11_DSCR_CORE_RESTARTED)
857 break;
858 }
859
860 if (!debug_execution)
861 {
862 target->state = TARGET_RUNNING;
863 target->debug_reason = DBG_REASON_NOTHALTED;
864 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
865 }
866 else
867 {
868 target->state = TARGET_DEBUG_RUNNING;
869 target->debug_reason = DBG_REASON_NOTHALTED;
870 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
871 }
872
873 return ERROR_OK;
874 }
875
876 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
877 {
878 FNC_INFO;
879
880 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
881
882 if (target->state != TARGET_HALTED)
883 {
884 LOG_WARNING("target was not halted");
885 return ERROR_TARGET_NOT_HALTED;
886 }
887
888 arm11_common_t * arm11 = target->arch_info;
889
890 if (!current)
891 R(PC) = address;
892
893 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
894
895 /** \todo TODO: Thumb not supported here */
896
897 u32 next_instruction;
898
899 arm11_read_memory_word(arm11, R(PC), &next_instruction);
900
901 /* skip over BKPT */
902 if ((next_instruction & 0xFFF00070) == 0xe1200070)
903 {
904 R(PC) += 4;
905 arm11->reg_list[ARM11_RC_PC].valid = 1;
906 arm11->reg_list[ARM11_RC_PC].dirty = 0;
907 LOG_INFO("Skipping BKPT");
908 }
909 /* skip over Wait for interrupt / Standby */
910 /* mcr 15, 0, r?, cr7, cr0, {4} */
911 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
912 {
913 R(PC) += 4;
914 arm11->reg_list[ARM11_RC_PC].valid = 1;
915 arm11->reg_list[ARM11_RC_PC].dirty = 0;
916 LOG_INFO("Skipping WFI");
917 }
918 /* ignore B to self */
919 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
920 {
921 LOG_INFO("Not stepping jump to self");
922 }
923 else
924 {
925 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
926 * with this. */
927
928 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
929 * the VCR might be something worth looking into. */
930
931
932 /* Set up breakpoint for stepping */
933
934 arm11_sc7_action_t brp[2];
935
936 brp[0].write = 1;
937 brp[0].address = ARM11_SC7_BVR0;
938 brp[0].value = R(PC);
939 brp[1].write = 1;
940 brp[1].address = ARM11_SC7_BCR0;
941 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
942
943 arm11_sc7_run(arm11, brp, asizeof(brp));
944
945 /* resume */
946
947 arm11_leave_debug_state(arm11);
948
949 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
950
951 jtag_execute_queue();
952
953 /** \todo TODO: add a timeout */
954
955 /* wait for halt */
956
957 while (1)
958 {
959 u32 dscr = arm11_read_DSCR(arm11);
960
961 LOG_DEBUG("DSCR %08x", dscr);
962
963 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
964 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
965 break;
966 }
967
968 /* clear breakpoint */
969 arm11_sc7_clear_vbw(arm11);
970
971 /* save state */
972 arm11_on_enter_debug_state(arm11);
973 }
974
975 // target->state = TARGET_HALTED;
976 target->debug_reason = DBG_REASON_SINGLESTEP;
977
978 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
979
980 return ERROR_OK;
981 }
982
983
984 /* target reset control */
985 int arm11_assert_reset(struct target_s *target)
986 {
987 FNC_INFO;
988
989 #if 0
990 /* assert reset lines */
991 /* resets only the DBGTAP, not the ARM */
992
993 jtag_add_reset(1, 0);
994 jtag_add_sleep(5000);
995
996 arm11_common_t * arm11 = target->arch_info;
997 arm11->trst_active = true;
998 #endif
999
1000 if (target->reset_halt)
1001 {
1002 int retval;
1003 if ((retval = target_halt(target))!=ERROR_OK)
1004 return retval;
1005 }
1006
1007 return ERROR_OK;
1008 }
1009
1010 int arm11_deassert_reset(struct target_s *target)
1011 {
1012 FNC_INFO;
1013
1014 #if 0
1015 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1016
1017 /* deassert reset lines */
1018 jtag_add_reset(0, 0);
1019
1020 arm11_common_t * arm11 = target->arch_info;
1021 arm11->trst_active = false;
1022
1023 if (arm11->halt_requested)
1024 return arm11_halt(target);
1025 #endif
1026
1027 return ERROR_OK;
1028 }
1029
1030 int arm11_soft_reset_halt(struct target_s *target)
1031 {
1032 FNC_INFO_NOTIMPLEMENTED;
1033
1034 return ERROR_OK;
1035 }
1036
1037
1038
1039 /* target register access for gdb */
1040 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1041 {
1042 FNC_INFO;
1043
1044 arm11_common_t * arm11 = target->arch_info;
1045
1046 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1047 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1048
1049 {size_t i;
1050 for (i = 16; i < 24; i++)
1051 {
1052 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1053 }}
1054
1055 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1056
1057
1058 {size_t i;
1059 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1060 {
1061 if (arm11_reg_defs[i].gdb_num == -1)
1062 continue;
1063
1064 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1065 }}
1066
1067 return ERROR_OK;
1068 }
1069
1070
1071 /* target memory access
1072 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1073 * count: number of items of <size>
1074 */
1075 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1076 {
1077 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1078
1079 FNC_INFO;
1080
1081 if (target->state != TARGET_HALTED)
1082 {
1083 LOG_WARNING("target was not halted");
1084 return ERROR_TARGET_NOT_HALTED;
1085 }
1086
1087 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1088
1089 arm11_common_t * arm11 = target->arch_info;
1090
1091 arm11_run_instr_data_prepare(arm11);
1092
1093 /* MRC p14,0,r0,c0,c5,0 */
1094 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1095
1096 switch (size)
1097 {
1098 case 1:
1099 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1100 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1101
1102 {size_t i;
1103 for (i = 0; i < count; i++)
1104 {
1105 /* ldrb r1, [r0], #1 */
1106 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1107
1108 u32 res;
1109 /* MCR p14,0,R1,c0,c5,0 */
1110 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1111
1112 *buffer++ = res;
1113 }}
1114
1115 break;
1116
1117 case 2:
1118 {
1119 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1120
1121 u16 * buf16 = (u16*)buffer;
1122
1123 {size_t i;
1124 for (i = 0; i < count; i++)
1125 {
1126 /* ldrh r1, [r0], #2 */
1127 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1128
1129 u32 res;
1130
1131 /* MCR p14,0,R1,c0,c5,0 */
1132 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1133
1134 *buf16++ = res;
1135 }}
1136
1137 break;
1138 }
1139
1140 case 4:
1141
1142 /* LDC p14,c5,[R0],#4 */
1143 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1144 break;
1145 }
1146
1147 arm11_run_instr_data_finish(arm11);
1148
1149 return ERROR_OK;
1150 }
1151
1152 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1153 {
1154 FNC_INFO;
1155
1156 if (target->state != TARGET_HALTED)
1157 {
1158 LOG_WARNING("target was not halted");
1159 return ERROR_TARGET_NOT_HALTED;
1160 }
1161
1162 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1163
1164 arm11_common_t * arm11 = target->arch_info;
1165
1166 arm11_run_instr_data_prepare(arm11);
1167
1168 /* MRC p14,0,r0,c0,c5,0 */
1169 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1170
1171 switch (size)
1172 {
1173 case 1:
1174 {
1175 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1176
1177 {size_t i;
1178 for (i = 0; i < count; i++)
1179 {
1180 /* MRC p14,0,r1,c0,c5,0 */
1181 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1182
1183 /* strb r1, [r0], #1 */
1184 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1185 }}
1186
1187 break;
1188 }
1189
1190 case 2:
1191 {
1192 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1193
1194 u16 * buf16 = (u16*)buffer;
1195
1196 {size_t i;
1197 for (i = 0; i < count; i++)
1198 {
1199 /* MRC p14,0,r1,c0,c5,0 */
1200 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1201
1202 /* strh r1, [r0], #2 */
1203 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1204 }}
1205
1206 break;
1207 }
1208
1209 case 4:
1210 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1211
1212 if (!arm11_config_memwrite_burst)
1213 {
1214 /* STC p14,c5,[R0],#4 */
1215 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1216 }
1217 else
1218 {
1219 /* STC p14,c5,[R0],#4 */
1220 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1221 }
1222
1223 break;
1224 }
1225
1226 #if 1
1227 /* r0 verification */
1228 {
1229 u32 r0;
1230
1231 /* MCR p14,0,R0,c0,c5,0 */
1232 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1233
1234 if (address + size * count != r0)
1235 {
1236 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1237
1238 if (arm11_config_memwrite_burst)
1239 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1240
1241 if (arm11_config_memwrite_error_fatal)
1242 return ERROR_FAIL;
1243 }
1244 }
1245 #endif
1246
1247
1248 arm11_run_instr_data_finish(arm11);
1249
1250
1251
1252
1253 return ERROR_OK;
1254 }
1255
1256
1257 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1258 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1259 {
1260 FNC_INFO;
1261
1262 if (target->state != TARGET_HALTED)
1263 {
1264 LOG_WARNING("target was not halted");
1265 return ERROR_TARGET_NOT_HALTED;
1266 }
1267
1268 return arm11_write_memory(target, address, 4, count, buffer);
1269 }
1270
1271
1272 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1273 {
1274 FNC_INFO_NOTIMPLEMENTED;
1275
1276 return ERROR_OK;
1277 }
1278
1279
1280 /* target break-/watchpoint control
1281 * rw: 0 = write, 1 = read, 2 = access
1282 */
1283 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1284 {
1285 FNC_INFO;
1286
1287 arm11_common_t * arm11 = target->arch_info;
1288
1289 #if 0
1290 if (breakpoint->type == BKPT_SOFT)
1291 {
1292 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1293 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1294 }
1295 #endif
1296
1297 if (!arm11->free_brps)
1298 {
1299 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1300 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1301 }
1302
1303 if (breakpoint->length != 4)
1304 {
1305 LOG_INFO("only breakpoints of four bytes length supported");
1306 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1307 }
1308
1309 arm11->free_brps--;
1310
1311 return ERROR_OK;
1312 }
1313
1314 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1315 {
1316 FNC_INFO;
1317
1318 arm11_common_t * arm11 = target->arch_info;
1319
1320 arm11->free_brps++;
1321
1322 return ERROR_OK;
1323 }
1324
1325 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1326 {
1327 FNC_INFO_NOTIMPLEMENTED;
1328
1329 return ERROR_OK;
1330 }
1331
1332 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1333 {
1334 FNC_INFO_NOTIMPLEMENTED;
1335
1336 return ERROR_OK;
1337 }
1338
1339
1340 /* target algorithm support */
1341 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1342 {
1343 FNC_INFO_NOTIMPLEMENTED;
1344
1345 return ERROR_OK;
1346 }
1347
1348 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1349 {
1350 FNC_INFO;
1351
1352 if (argc < 4)
1353 {
1354 return ERROR_COMMAND_SYNTAX_ERROR;
1355 }
1356
1357 int chain_pos = strtoul(args[3], NULL, 0);
1358
1359 NEW(arm11_common_t, arm11, 1);
1360
1361 arm11->target = target;
1362
1363 /* prepare JTAG information for the new target */
1364 arm11->jtag_info.chain_pos = chain_pos;
1365 arm11->jtag_info.scann_size = 5;
1366
1367 arm_jtag_setup_connection(&arm11->jtag_info);
1368
1369 jtag_device_t *device = jtag_get_device(chain_pos);
1370
1371 if (device->ir_length != 5)
1372 {
1373 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1374 return ERROR_COMMAND_SYNTAX_ERROR;
1375 }
1376
1377 target->arch_info = arm11;
1378
1379 return ERROR_OK;
1380 }
1381
1382 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1383 {
1384 /* Initialize anything we can set up without talking to the target */
1385 return ERROR_OK;
1386 }
1387
1388 /* talk to the target and set things up */
1389 int arm11_examine(struct target_s *target)
1390 {
1391 FNC_INFO;
1392 int retval;
1393
1394 arm11_common_t * arm11 = target->arch_info;
1395
1396 /* check IDCODE */
1397
1398 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1399
1400 scan_field_t idcode_field;
1401
1402 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1403
1404 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1405
1406 /* check DIDR */
1407
1408 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1409
1410 arm11_add_IR(arm11, ARM11_INTEST, -1);
1411
1412 scan_field_t chain0_fields[2];
1413
1414 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1415 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1416
1417 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1418
1419 if ((retval=jtag_execute_queue())!=ERROR_OK)
1420 return retval;
1421
1422
1423 switch (arm11->device_id & 0x0FFFF000)
1424 {
1425 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1426 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1427 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1428 default:
1429 {
1430 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1431 return ERROR_FAIL;
1432 }
1433 }
1434
1435 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1436
1437 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1438 arm11->debug_version != ARM11_DEBUG_V61)
1439 {
1440 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1441 return ERROR_FAIL;
1442 }
1443
1444
1445 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1446 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1447
1448 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1449 arm11->free_brps = arm11->brp;
1450 arm11->free_wrps = arm11->wrp;
1451
1452 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1453 arm11->device_id,
1454 arm11->implementor,
1455 arm11->didr);
1456
1457 arm11_build_reg_cache(target);
1458
1459
1460 /* as a side-effect this reads DSCR and thus
1461 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1462 * as suggested by the spec.
1463 */
1464
1465 arm11_check_init(arm11, NULL);
1466
1467 return ERROR_OK;
1468 }
1469
1470 int arm11_quit(void)
1471 {
1472 FNC_INFO_NOTIMPLEMENTED;
1473
1474 return ERROR_OK;
1475 }
1476
1477 /** Load a register that is marked !valid in the register cache */
1478 int arm11_get_reg(reg_t *reg)
1479 {
1480 FNC_INFO;
1481
1482 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1483
1484 if (target->state != TARGET_HALTED)
1485 {
1486 LOG_WARNING("target was not halted");
1487 return ERROR_TARGET_NOT_HALTED;
1488 }
1489
1490 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1491
1492 #if 0
1493 arm11_common_t *arm11 = target->arch_info;
1494 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1495 #endif
1496
1497 return ERROR_OK;
1498 }
1499
1500 /** Change a value in the register cache */
1501 int arm11_set_reg(reg_t *reg, u8 *buf)
1502 {
1503 FNC_INFO;
1504
1505 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1506 arm11_common_t *arm11 = target->arch_info;
1507 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1508
1509 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1510 reg->valid = 1;
1511 reg->dirty = 1;
1512
1513 return ERROR_OK;
1514 }
1515
1516
1517 void arm11_build_reg_cache(target_t *target)
1518 {
1519 arm11_common_t *arm11 = target->arch_info;
1520
1521 NEW(reg_cache_t, cache, 1);
1522 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1523 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1524
1525 if (arm11_regs_arch_type == -1)
1526 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1527
1528 arm11->reg_list = reg_list;
1529
1530 /* Build the process context cache */
1531 cache->name = "arm11 registers";
1532 cache->next = NULL;
1533 cache->reg_list = reg_list;
1534 cache->num_regs = ARM11_REGCACHE_COUNT;
1535
1536 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1537 (*cache_p) = cache;
1538
1539 // armv7m->core_cache = cache;
1540 // armv7m->process_context = cache;
1541
1542 size_t i;
1543
1544 /* Not very elegant assertion */
1545 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1546 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1547 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1548 {
1549 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1550 exit(-1);
1551 }
1552
1553 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1554 {
1555 reg_t * r = reg_list + i;
1556 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1557 arm11_reg_state_t * rs = arm11_reg_states + i;
1558
1559 r->name = rd->name;
1560 r->size = 32;
1561 r->value = (u8 *)(arm11->reg_values + i);
1562 r->dirty = 0;
1563 r->valid = 0;
1564 r->bitfield_desc = NULL;
1565 r->num_bitfields = 0;
1566 r->arch_type = arm11_regs_arch_type;
1567 r->arch_info = rs;
1568
1569 rs->def_index = i;
1570 rs->target = target;
1571 }
1572 }
1573
1574
1575
1576 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1577 {
1578 if (argc == 0)
1579 {
1580 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1581 return ERROR_OK;
1582 }
1583
1584 if (argc != 1)
1585 return ERROR_COMMAND_SYNTAX_ERROR;
1586
1587 switch (args[0][0])
1588 {
1589 case '0': /* 0 */
1590 case 'f': /* false */
1591 case 'F':
1592 case 'd': /* disable */
1593 case 'D':
1594 *var = false;
1595 break;
1596
1597 case '1': /* 1 */
1598 case 't': /* true */
1599 case 'T':
1600 case 'e': /* enable */
1601 case 'E':
1602 *var = true;
1603 break;
1604 }
1605
1606 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1607
1608 return ERROR_OK;
1609 }
1610
1611
1612 #define BOOL_WRAPPER(name, print_name) \
1613 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1614 { \
1615 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1616 }
1617
1618 #define RC_TOP(name, descr, more) \
1619 { \
1620 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1621 command_t * top_cmd = new_cmd; \
1622 more \
1623 }
1624
1625 #define RC_FINAL(name, descr, handler) \
1626 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1627
1628 #define RC_FINAL_BOOL(name, descr, var) \
1629 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1630
1631
1632 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1633 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1634
1635
1636 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1637 {
1638 if (argc == 1)
1639 {
1640 arm11_vcr = strtoul(args[0], NULL, 0);
1641 }
1642 else if (argc != 0)
1643 {
1644 return ERROR_COMMAND_SYNTAX_ERROR;
1645 }
1646
1647 LOG_INFO("VCR 0x%08X", arm11_vcr);
1648 return ERROR_OK;
1649 }
1650
1651 const u32 arm11_coproc_instruction_limits[] =
1652 {
1653 15, /* coprocessor */
1654 7, /* opcode 1 */
1655 15, /* CRn */
1656 15, /* CRm */
1657 7, /* opcode 2 */
1658 0xFFFFFFFF, /* value */
1659 };
1660
1661 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1662 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1663
1664
1665 arm11_common_t * arm11_find_target(const char * arg)
1666 {
1667 size_t jtag_target = strtoul(arg, NULL, 0);
1668
1669 {target_t * t;
1670 for (t = targets; t; t = t->next)
1671 {
1672 if (t->type != &arm11_target)
1673 continue;
1674
1675 arm11_common_t * arm11 = t->arch_info;
1676
1677 if (arm11->jtag_info.chain_pos != jtag_target)
1678 continue;
1679
1680 return arm11;
1681 }}
1682
1683 return 0;
1684 }
1685
1686 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1687 {
1688 if (argc != (read ? 6 : 7))
1689 {
1690 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1691 return -1;
1692 }
1693
1694 arm11_common_t * arm11 = arm11_find_target(args[0]);
1695
1696 if (!arm11)
1697 {
1698 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1699 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1700
1701 return -1;
1702
1703 }
1704
1705 if (arm11->target->state != TARGET_HALTED)
1706 {
1707 LOG_WARNING("target was not halted");
1708 return ERROR_TARGET_NOT_HALTED;
1709 }
1710
1711
1712 u32 values[6];
1713
1714 {size_t i;
1715 for (i = 0; i < (read ? 5 : 6); i++)
1716 {
1717 values[i] = strtoul(args[i + 1], NULL, 0);
1718
1719 if (values[i] > arm11_coproc_instruction_limits[i])
1720 {
1721 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1722 (long)(i + 2), arm11_coproc_instruction_limits[i],
1723 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1724 return -1;
1725 }
1726 }}
1727
1728 u32 instr = 0xEE000010 |
1729 (values[0] << 8) |
1730 (values[1] << 21) |
1731 (values[2] << 16) |
1732 (values[3] << 0) |
1733 (values[4] << 5);
1734
1735 if (read)
1736 instr |= 0x00100000;
1737
1738
1739 arm11_run_instr_data_prepare(arm11);
1740
1741 if (read)
1742 {
1743 u32 result;
1744 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1745
1746 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1747 values[0], values[1], values[2], values[3], values[4], result, result);
1748 }
1749 else
1750 {
1751 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1752
1753 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1754 values[0], values[1],
1755 values[5],
1756 values[2], values[3], values[4]);
1757 }
1758
1759 arm11_run_instr_data_finish(arm11);
1760
1761
1762 return ERROR_OK;
1763 }
1764
1765 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1766 {
1767 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1768 }
1769
1770 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1771 {
1772 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1773 }
1774
1775 int arm11_register_commands(struct command_context_s *cmd_ctx)
1776 {
1777 FNC_INFO;
1778
1779 command_t * top_cmd = NULL;
1780
1781 RC_TOP( "arm11", "arm11 specific commands",
1782
1783 RC_TOP( "memwrite", "Control memory write transfer mode",
1784
1785 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1786 memwrite_burst)
1787
1788 RC_FINAL_BOOL( "error_fatal",
1789 "Terminate program if transfer error was found (default: enabled)",
1790 memwrite_error_fatal)
1791 )
1792
1793 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1794 arm11_handle_vcr)
1795
1796 RC_FINAL( "mrc", "Read Coprocessor register",
1797 arm11_handle_mrc)
1798
1799 RC_FINAL( "mcr", "Write Coprocessor register",
1800 arm11_handle_mcr)
1801 )
1802
1803 return ERROR_OK;
1804 }
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