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fix crash when connecting GDB to powered down target
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "arm11.h"
29 #include "jtag.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 u32 arm11_vcr = 0;
56
57 #define ARM11_HANDLER(x) \
58 .x = arm11_##x
59
60 target_type_t arm11_target =
61 {
62 .name = "arm11",
63
64 ARM11_HANDLER(poll),
65 ARM11_HANDLER(arch_state),
66
67 ARM11_HANDLER(target_request_data),
68
69 ARM11_HANDLER(halt),
70 ARM11_HANDLER(resume),
71 ARM11_HANDLER(step),
72
73 ARM11_HANDLER(assert_reset),
74 ARM11_HANDLER(deassert_reset),
75 ARM11_HANDLER(soft_reset_halt),
76
77 ARM11_HANDLER(get_gdb_reg_list),
78
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
81
82 ARM11_HANDLER(bulk_write_memory),
83
84 ARM11_HANDLER(checksum_memory),
85
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
90
91 ARM11_HANDLER(run_algorithm),
92
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_create),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(examine),
97 ARM11_HANDLER(quit),
98 };
99
100 int arm11_regs_arch_type = -1;
101
102
103 enum arm11_regtype
104 {
105 ARM11_REGISTER_CORE,
106 ARM11_REGISTER_CPSR,
107
108 ARM11_REGISTER_FX,
109 ARM11_REGISTER_FPS,
110
111 ARM11_REGISTER_FIQ,
112 ARM11_REGISTER_SVC,
113 ARM11_REGISTER_ABT,
114 ARM11_REGISTER_IRQ,
115 ARM11_REGISTER_UND,
116 ARM11_REGISTER_MON,
117
118 ARM11_REGISTER_SPSR_FIQ,
119 ARM11_REGISTER_SPSR_SVC,
120 ARM11_REGISTER_SPSR_ABT,
121 ARM11_REGISTER_SPSR_IRQ,
122 ARM11_REGISTER_SPSR_UND,
123 ARM11_REGISTER_SPSR_MON,
124
125 /* debug regs */
126 ARM11_REGISTER_DSCR,
127 ARM11_REGISTER_WDTR,
128 ARM11_REGISTER_RDTR,
129 };
130
131
132 typedef struct arm11_reg_defs_s
133 {
134 char * name;
135 u32 num;
136 int gdb_num;
137 enum arm11_regtype type;
138 } arm11_reg_defs_t;
139
140 /* update arm11_regcache_ids when changing this */
141 static const arm11_reg_defs_t arm11_reg_defs[] =
142 {
143 {"r0", 0, 0, ARM11_REGISTER_CORE},
144 {"r1", 1, 1, ARM11_REGISTER_CORE},
145 {"r2", 2, 2, ARM11_REGISTER_CORE},
146 {"r3", 3, 3, ARM11_REGISTER_CORE},
147 {"r4", 4, 4, ARM11_REGISTER_CORE},
148 {"r5", 5, 5, ARM11_REGISTER_CORE},
149 {"r6", 6, 6, ARM11_REGISTER_CORE},
150 {"r7", 7, 7, ARM11_REGISTER_CORE},
151 {"r8", 8, 8, ARM11_REGISTER_CORE},
152 {"r9", 9, 9, ARM11_REGISTER_CORE},
153 {"r10", 10, 10, ARM11_REGISTER_CORE},
154 {"r11", 11, 11, ARM11_REGISTER_CORE},
155 {"r12", 12, 12, ARM11_REGISTER_CORE},
156 {"sp", 13, 13, ARM11_REGISTER_CORE},
157 {"lr", 14, 14, ARM11_REGISTER_CORE},
158 {"pc", 15, 15, ARM11_REGISTER_CORE},
159
160 #if ARM11_REGCACHE_FREGS
161 {"f0", 0, 16, ARM11_REGISTER_FX},
162 {"f1", 1, 17, ARM11_REGISTER_FX},
163 {"f2", 2, 18, ARM11_REGISTER_FX},
164 {"f3", 3, 19, ARM11_REGISTER_FX},
165 {"f4", 4, 20, ARM11_REGISTER_FX},
166 {"f5", 5, 21, ARM11_REGISTER_FX},
167 {"f6", 6, 22, ARM11_REGISTER_FX},
168 {"f7", 7, 23, ARM11_REGISTER_FX},
169 {"fps", 0, 24, ARM11_REGISTER_FPS},
170 #endif
171
172 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
173
174 #if ARM11_REGCACHE_MODEREGS
175 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
176 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
177 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
178 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
179 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
180 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
181 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
182 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
183
184 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
185 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
186 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
187
188 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
189 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
190 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
191
192 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
193 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
194 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
195
196 {"r13_und", 13, -1, ARM11_REGISTER_UND},
197 {"r14_und", 14, -1, ARM11_REGISTER_UND},
198 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
199
200 /* ARM1176 only */
201 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
202 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
203 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
204 #endif
205
206 /* Debug Registers */
207 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
208 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
209 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
210 };
211
212 enum arm11_regcache_ids
213 {
214 ARM11_RC_R0,
215 ARM11_RC_RX = ARM11_RC_R0,
216
217 ARM11_RC_R1,
218 ARM11_RC_R2,
219 ARM11_RC_R3,
220 ARM11_RC_R4,
221 ARM11_RC_R5,
222 ARM11_RC_R6,
223 ARM11_RC_R7,
224 ARM11_RC_R8,
225 ARM11_RC_R9,
226 ARM11_RC_R10,
227 ARM11_RC_R11,
228 ARM11_RC_R12,
229 ARM11_RC_R13,
230 ARM11_RC_SP = ARM11_RC_R13,
231 ARM11_RC_R14,
232 ARM11_RC_LR = ARM11_RC_R14,
233 ARM11_RC_R15,
234 ARM11_RC_PC = ARM11_RC_R15,
235
236 #if ARM11_REGCACHE_FREGS
237 ARM11_RC_F0,
238 ARM11_RC_FX = ARM11_RC_F0,
239 ARM11_RC_F1,
240 ARM11_RC_F2,
241 ARM11_RC_F3,
242 ARM11_RC_F4,
243 ARM11_RC_F5,
244 ARM11_RC_F6,
245 ARM11_RC_F7,
246 ARM11_RC_FPS,
247 #endif
248
249 ARM11_RC_CPSR,
250
251 #if ARM11_REGCACHE_MODEREGS
252 ARM11_RC_R8_FIQ,
253 ARM11_RC_R9_FIQ,
254 ARM11_RC_R10_FIQ,
255 ARM11_RC_R11_FIQ,
256 ARM11_RC_R12_FIQ,
257 ARM11_RC_R13_FIQ,
258 ARM11_RC_R14_FIQ,
259 ARM11_RC_SPSR_FIQ,
260
261 ARM11_RC_R13_SVC,
262 ARM11_RC_R14_SVC,
263 ARM11_RC_SPSR_SVC,
264
265 ARM11_RC_R13_ABT,
266 ARM11_RC_R14_ABT,
267 ARM11_RC_SPSR_ABT,
268
269 ARM11_RC_R13_IRQ,
270 ARM11_RC_R14_IRQ,
271 ARM11_RC_SPSR_IRQ,
272
273 ARM11_RC_R13_UND,
274 ARM11_RC_R14_UND,
275 ARM11_RC_SPSR_UND,
276
277 ARM11_RC_R13_MON,
278 ARM11_RC_R14_MON,
279 ARM11_RC_SPSR_MON,
280 #endif
281
282 ARM11_RC_DSCR,
283 ARM11_RC_WDTR,
284 ARM11_RC_RDTR,
285
286 ARM11_RC_MAX,
287 };
288
289 #define ARM11_GDB_REGISTER_COUNT 26
290
291 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292
293 reg_t arm11_gdb_dummy_fp_reg =
294 {
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
296 };
297
298 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299
300 reg_t arm11_gdb_dummy_fps_reg =
301 {
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
303 };
304
305
306
307 /** Check and if necessary take control of the system
308 *
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
313 */
314 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
315 {
316 FNC_INFO;
317
318 u32 dscr_local_tmp_copy;
319
320 if (!dscr)
321 {
322 dscr = &dscr_local_tmp_copy;
323 *dscr = arm11_read_DSCR(arm11);
324 }
325
326 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
327 {
328 LOG_DEBUG("Bringing target into debug mode");
329
330 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
331 arm11_write_DSCR(arm11, *dscr);
332
333 /* add further reset initialization here */
334
335 arm11->simulate_reset_on_next_halt = true;
336
337 if (*dscr & ARM11_DSCR_CORE_HALTED)
338 {
339 /** \todo TODO: this needs further scrutiny because
340 * arm11_on_enter_debug_state() never gets properly called
341 */
342
343 arm11->target->state = TARGET_HALTED;
344 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
345 }
346 else
347 {
348 arm11->target->state = TARGET_RUNNING;
349 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
350 }
351
352 arm11_sc7_clear_vbw(arm11);
353 }
354 }
355
356
357
358 #define R(x) \
359 (arm11->reg_values[ARM11_RC_##x])
360
361 /** Save processor state.
362 *
363 * This is called when the HALT instruction has succeeded
364 * or on other occasions that stop the processor.
365 *
366 */
367 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
368 {
369 FNC_INFO;
370
371 {size_t i;
372 for(i = 0; i < asizeof(arm11->reg_values); i++)
373 {
374 arm11->reg_list[i].valid = 1;
375 arm11->reg_list[i].dirty = 0;
376 }}
377
378 /* Save DSCR */
379
380 R(DSCR) = arm11_read_DSCR(arm11);
381
382 /* Save wDTR */
383
384 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
385 {
386 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
387
388 arm11_add_IR(arm11, ARM11_INTEST, -1);
389
390 scan_field_t chain5_fields[3];
391
392 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
394 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
395
396 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
397 }
398 else
399 {
400 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
401 }
402
403
404 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
405 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
406 ARM1136 seems to require this to issue ITR's as well */
407
408 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
409
410 /* this executes JTAG queue: */
411
412 arm11_write_DSCR(arm11, new_dscr);
413
414
415 /* From the spec:
416 Before executing any instruction in debug state you have to drain the write buffer.
417 This ensures that no imprecise Data Aborts can return at a later point:*/
418
419 /** \todo TODO: Test drain write buffer. */
420
421 #if 0
422 while (1)
423 {
424 /* MRC p14,0,R0,c5,c10,0 */
425 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
426
427 /* mcr 15, 0, r0, cr7, cr10, {4} */
428 arm11_run_instr_no_data1(arm11, 0xee070f9a);
429
430 u32 dscr = arm11_read_DSCR(arm11);
431
432 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
433
434 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
435 {
436 arm11_run_instr_no_data1(arm11, 0xe320f000);
437
438 dscr = arm11_read_DSCR(arm11);
439
440 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
441
442 break;
443 }
444 }
445 #endif
446
447 arm11_run_instr_data_prepare(arm11);
448
449 /* save r0 - r14 */
450
451 /** \todo TODO: handle other mode registers */
452
453 {size_t i;
454 for (i = 0; i < 15; i++)
455 {
456 /* MCR p14,0,R?,c0,c5,0 */
457 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
458 }}
459
460 /* save rDTR */
461
462 /* check rDTRfull in DSCR */
463
464 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
465 {
466 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
467 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
468 }
469 else
470 {
471 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
472 }
473
474 /* save CPSR */
475
476 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
477 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
478
479 /* save PC */
480
481 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
482 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
483
484 /* adjust PC depending on ARM state */
485
486 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
487 {
488 arm11->reg_values[ARM11_RC_PC] -= 0;
489 }
490 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
491 {
492 arm11->reg_values[ARM11_RC_PC] -= 4;
493 }
494 else /* ARM state */
495 {
496 arm11->reg_values[ARM11_RC_PC] -= 8;
497 }
498
499 if (arm11->simulate_reset_on_next_halt)
500 {
501 arm11->simulate_reset_on_next_halt = false;
502
503 LOG_DEBUG("Reset c1 Control Register");
504
505 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
506
507 /* MCR p15,0,R0,c1,c0,0 */
508 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
509
510 }
511
512 arm11_run_instr_data_finish(arm11);
513
514 arm11_dump_reg_changes(arm11);
515 }
516
517 void arm11_dump_reg_changes(arm11_common_t * arm11)
518 {
519 {size_t i;
520 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
521 {
522 if (!arm11->reg_list[i].valid)
523 {
524 if (arm11->reg_history[i].valid)
525 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
526 }
527 else
528 {
529 if (arm11->reg_history[i].valid)
530 {
531 if (arm11->reg_history[i].value != arm11->reg_values[i])
532 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
533 }
534 else
535 {
536 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
537 }
538 }
539 }}
540 }
541
542 /** Restore processor state
543 *
544 * This is called in preparation for the RESTART function.
545 *
546 */
547 void arm11_leave_debug_state(arm11_common_t * arm11)
548 {
549 FNC_INFO;
550
551 arm11_run_instr_data_prepare(arm11);
552
553 /** \todo TODO: handle other mode registers */
554
555 /* restore R1 - R14 */
556 {size_t i;
557 for (i = 1; i < 15; i++)
558 {
559 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
560 continue;
561
562 /* MRC p14,0,r?,c0,c5,0 */
563 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
564
565 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
566 }}
567
568 arm11_run_instr_data_finish(arm11);
569
570 /* spec says clear wDTR and rDTR; we assume they are clear as
571 otherwise our programming would be sloppy */
572
573 {
574 u32 DSCR = arm11_read_DSCR(arm11);
575
576 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
577 {
578 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
579 }
580 }
581
582 arm11_run_instr_data_prepare(arm11);
583
584 /* restore original wDTR */
585
586 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
587 {
588 /* MCR p14,0,R0,c0,c5,0 */
589 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
590 }
591
592 /* restore CPSR */
593
594 /* MSR CPSR,R0*/
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
596
597 /* restore PC */
598
599 /* MOV PC,R0 */
600 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
601
602 /* restore R0 */
603
604 /* MRC p14,0,r0,c0,c5,0 */
605 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
606
607 arm11_run_instr_data_finish(arm11);
608
609 /* restore DSCR */
610
611 arm11_write_DSCR(arm11, R(DSCR));
612
613 /* restore rDTR */
614
615 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
616 {
617 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
618
619 arm11_add_IR(arm11, ARM11_EXTEST, -1);
620
621 scan_field_t chain5_fields[3];
622
623 u8 Ready = 0; /* ignored */
624 u8 Valid = 0; /* ignored */
625
626 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
627 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
628 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
629
630 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
631 }
632
633 arm11_record_register_history(arm11);
634 }
635
636 void arm11_record_register_history(arm11_common_t * arm11)
637 {
638 {size_t i;
639 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
640 {
641 arm11->reg_history[i].value = arm11->reg_values[i];
642 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
643
644 arm11->reg_list[i].valid = 0;
645 arm11->reg_list[i].dirty = 0;
646 }}
647 }
648
649
650 /* poll current target status */
651 int arm11_poll(struct target_s *target)
652 {
653 FNC_INFO;
654
655 arm11_common_t * arm11 = target->arch_info;
656
657 if (arm11->trst_active)
658 return ERROR_OK;
659
660 u32 dscr = arm11_read_DSCR(arm11);
661
662 LOG_DEBUG("DSCR %08x", dscr);
663
664 arm11_check_init(arm11, &dscr);
665
666 if (dscr & ARM11_DSCR_CORE_HALTED)
667 {
668 if (target->state != TARGET_HALTED)
669 {
670 enum target_state old_state = target->state;
671
672 LOG_DEBUG("enter TARGET_HALTED");
673 target->state = TARGET_HALTED;
674 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
675 arm11_on_enter_debug_state(arm11);
676
677 target_call_event_callbacks(target,
678 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
679 }
680 }
681 else
682 {
683 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
684 {
685 LOG_DEBUG("enter TARGET_RUNNING");
686 target->state = TARGET_RUNNING;
687 target->debug_reason = DBG_REASON_NOTHALTED;
688 }
689 }
690
691 return ERROR_OK;
692 }
693 /* architecture specific status reply */
694 int arm11_arch_state(struct target_s *target)
695 {
696 FNC_INFO_NOTIMPLEMENTED;
697
698 return ERROR_OK;
699 }
700
701 /* target request support */
702 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
703 {
704 FNC_INFO_NOTIMPLEMENTED;
705
706 return ERROR_OK;
707 }
708
709 /* target execution control */
710 int arm11_halt(struct target_s *target)
711 {
712 FNC_INFO;
713
714 arm11_common_t * arm11 = target->arch_info;
715
716 LOG_DEBUG("target->state: %s",
717 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
718
719 if (target->state == TARGET_UNKNOWN)
720 {
721 arm11->simulate_reset_on_next_halt = true;
722 }
723
724 if (target->state == TARGET_HALTED)
725 {
726 LOG_DEBUG("target was already halted");
727 return ERROR_OK;
728 }
729
730 if (arm11->trst_active)
731 {
732 arm11->halt_requested = true;
733 return ERROR_OK;
734 }
735
736 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
737
738 jtag_execute_queue();
739
740 u32 dscr;
741
742 while (1)
743 {
744 dscr = arm11_read_DSCR(arm11);
745
746 if (dscr & ARM11_DSCR_CORE_HALTED)
747 break;
748 }
749
750 arm11_on_enter_debug_state(arm11);
751
752 enum target_state old_state = target->state;
753
754 target->state = TARGET_HALTED;
755 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
756
757 target_call_event_callbacks(target,
758 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
759
760 return ERROR_OK;
761 }
762
763 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
764 {
765 FNC_INFO;
766
767 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
768 // current, address, handle_breakpoints, debug_execution);
769
770 arm11_common_t * arm11 = target->arch_info;
771
772 LOG_DEBUG("target->state: %s",
773 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
774
775
776 if (target->state != TARGET_HALTED)
777 {
778 LOG_ERROR("Target not halted");
779 return ERROR_TARGET_NOT_HALTED;
780 }
781
782 if (!current)
783 R(PC) = address;
784
785 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
786
787 /* clear breakpoints/watchpoints and VCR*/
788 arm11_sc7_clear_vbw(arm11);
789
790 /* Set up breakpoints */
791 if (!debug_execution)
792 {
793 /* check if one matches PC and step over it if necessary */
794
795 breakpoint_t * bp;
796
797 for (bp = target->breakpoints; bp; bp = bp->next)
798 {
799 if (bp->address == R(PC))
800 {
801 LOG_DEBUG("must step over %08x", bp->address);
802 arm11_step(target, 1, 0, 0);
803 break;
804 }
805 }
806
807 /* set all breakpoints */
808
809 size_t brp_num = 0;
810
811 for (bp = target->breakpoints; bp; bp = bp->next)
812 {
813 arm11_sc7_action_t brp[2];
814
815 brp[0].write = 1;
816 brp[0].address = ARM11_SC7_BVR0 + brp_num;
817 brp[0].value = bp->address;
818 brp[1].write = 1;
819 brp[1].address = ARM11_SC7_BCR0 + brp_num;
820 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
821
822 arm11_sc7_run(arm11, brp, asizeof(brp));
823
824 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
825
826 brp_num++;
827 }
828
829 arm11_sc7_set_vcr(arm11, arm11_vcr);
830 }
831
832 arm11_leave_debug_state(arm11);
833
834 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
835
836 jtag_execute_queue();
837
838 while (1)
839 {
840 u32 dscr = arm11_read_DSCR(arm11);
841
842 LOG_DEBUG("DSCR %08x", dscr);
843
844 if (dscr & ARM11_DSCR_CORE_RESTARTED)
845 break;
846 }
847
848 if (!debug_execution)
849 {
850 target->state = TARGET_RUNNING;
851 target->debug_reason = DBG_REASON_NOTHALTED;
852 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
853 }
854 else
855 {
856 target->state = TARGET_DEBUG_RUNNING;
857 target->debug_reason = DBG_REASON_NOTHALTED;
858 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
859 }
860
861 return ERROR_OK;
862 }
863
864 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
865 {
866 FNC_INFO;
867
868 LOG_DEBUG("target->state: %s",
869 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
870
871 if (target->state != TARGET_HALTED)
872 {
873 LOG_WARNING("target was not halted");
874 return ERROR_TARGET_NOT_HALTED;
875 }
876
877 arm11_common_t * arm11 = target->arch_info;
878
879 if (!current)
880 R(PC) = address;
881
882 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
883
884 /** \todo TODO: Thumb not supported here */
885
886 u32 next_instruction;
887
888 arm11_read_memory_word(arm11, R(PC), &next_instruction);
889
890 /* skip over BKPT */
891 if ((next_instruction & 0xFFF00070) == 0xe1200070)
892 {
893 R(PC) += 4;
894 arm11->reg_list[ARM11_RC_PC].valid = 1;
895 arm11->reg_list[ARM11_RC_PC].dirty = 0;
896 LOG_INFO("Skipping BKPT");
897 }
898 /* skip over Wait for interrupt / Standby */
899 /* mcr 15, 0, r?, cr7, cr0, {4} */
900 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
901 {
902 R(PC) += 4;
903 arm11->reg_list[ARM11_RC_PC].valid = 1;
904 arm11->reg_list[ARM11_RC_PC].dirty = 0;
905 LOG_INFO("Skipping WFI");
906 }
907 /* ignore B to self */
908 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
909 {
910 LOG_INFO("Not stepping jump to self");
911 }
912 else
913 {
914 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
915 * with this. */
916
917 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
918 * the VCR might be something worth looking into. */
919
920
921 /* Set up breakpoint for stepping */
922
923 arm11_sc7_action_t brp[2];
924
925 brp[0].write = 1;
926 brp[0].address = ARM11_SC7_BVR0;
927 brp[0].value = R(PC);
928 brp[1].write = 1;
929 brp[1].address = ARM11_SC7_BCR0;
930 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
931
932 arm11_sc7_run(arm11, brp, asizeof(brp));
933
934 /* resume */
935
936 arm11_leave_debug_state(arm11);
937
938 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
939
940 jtag_execute_queue();
941
942 /** \todo TODO: add a timeout */
943
944 /* wait for halt */
945
946 while (1)
947 {
948 u32 dscr = arm11_read_DSCR(arm11);
949
950 LOG_DEBUG("DSCR %08x", dscr);
951
952 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
953 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
954 break;
955 }
956
957 /* clear breakpoint */
958 arm11_sc7_clear_vbw(arm11);
959
960 /* save state */
961 arm11_on_enter_debug_state(arm11);
962 }
963
964 // target->state = TARGET_HALTED;
965 target->debug_reason = DBG_REASON_SINGLESTEP;
966
967 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
968
969 return ERROR_OK;
970 }
971
972 /* target reset control */
973 int arm11_assert_reset(struct target_s *target)
974 {
975 FNC_INFO;
976
977 #if 0
978 /* assert reset lines */
979 /* resets only the DBGTAP, not the ARM */
980
981 jtag_add_reset(1, 0);
982 jtag_add_sleep(5000);
983
984 arm11_common_t * arm11 = target->arch_info;
985 arm11->trst_active = true;
986 #endif
987
988 if (target->reset_halt)
989 {
990 int retval;
991 if ((retval = target_halt(target))!=ERROR_OK)
992 return retval;
993 }
994
995 return ERROR_OK;
996 }
997
998 int arm11_deassert_reset(struct target_s *target)
999 {
1000 FNC_INFO;
1001
1002 #if 0
1003 LOG_DEBUG("target->state: %s",
1004 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1005
1006
1007 /* deassert reset lines */
1008 jtag_add_reset(0, 0);
1009
1010 arm11_common_t * arm11 = target->arch_info;
1011 arm11->trst_active = false;
1012
1013 if (arm11->halt_requested)
1014 return arm11_halt(target);
1015 #endif
1016
1017 return ERROR_OK;
1018 }
1019
1020 int arm11_soft_reset_halt(struct target_s *target)
1021 {
1022 FNC_INFO_NOTIMPLEMENTED;
1023
1024 return ERROR_OK;
1025 }
1026
1027 /* target register access for gdb */
1028 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1029 {
1030 FNC_INFO;
1031
1032 arm11_common_t * arm11 = target->arch_info;
1033
1034 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1035 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1036
1037 {size_t i;
1038 for (i = 16; i < 24; i++)
1039 {
1040 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1041 }}
1042
1043 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1044
1045 {size_t i;
1046 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1047 {
1048 if (arm11_reg_defs[i].gdb_num == -1)
1049 continue;
1050
1051 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1052 }}
1053
1054 return ERROR_OK;
1055 }
1056
1057 /* target memory access
1058 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1059 * count: number of items of <size>
1060 */
1061 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1062 {
1063 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1064
1065 FNC_INFO;
1066
1067 if (target->state != TARGET_HALTED)
1068 {
1069 LOG_WARNING("target was not halted");
1070 return ERROR_TARGET_NOT_HALTED;
1071 }
1072
1073 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1074
1075 arm11_common_t * arm11 = target->arch_info;
1076
1077 arm11_run_instr_data_prepare(arm11);
1078
1079 /* MRC p14,0,r0,c0,c5,0 */
1080 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1081
1082 switch (size)
1083 {
1084 case 1:
1085 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1086 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1087
1088 {size_t i;
1089 for (i = 0; i < count; i++)
1090 {
1091 /* ldrb r1, [r0], #1 */
1092 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1093
1094 u32 res;
1095 /* MCR p14,0,R1,c0,c5,0 */
1096 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1097
1098 *buffer++ = res;
1099 }}
1100
1101 break;
1102
1103 case 2:
1104 {
1105 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1106
1107 u16 * buf16 = (u16*)buffer;
1108
1109 {size_t i;
1110 for (i = 0; i < count; i++)
1111 {
1112 /* ldrh r1, [r0], #2 */
1113 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1114
1115 u32 res;
1116
1117 /* MCR p14,0,R1,c0,c5,0 */
1118 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1119
1120 *buf16++ = res;
1121 }}
1122
1123 break;
1124 }
1125
1126 case 4:
1127
1128 /* LDC p14,c5,[R0],#4 */
1129 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1130 break;
1131 }
1132
1133 arm11_run_instr_data_finish(arm11);
1134
1135 return ERROR_OK;
1136 }
1137
1138 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1139 {
1140 FNC_INFO;
1141
1142 if (target->state != TARGET_HALTED)
1143 {
1144 LOG_WARNING("target was not halted");
1145 return ERROR_TARGET_NOT_HALTED;
1146 }
1147
1148 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1149
1150 arm11_common_t * arm11 = target->arch_info;
1151
1152 arm11_run_instr_data_prepare(arm11);
1153
1154 /* MRC p14,0,r0,c0,c5,0 */
1155 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1156
1157 switch (size)
1158 {
1159 case 1:
1160 {
1161 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1162
1163 {size_t i;
1164 for (i = 0; i < count; i++)
1165 {
1166 /* MRC p14,0,r1,c0,c5,0 */
1167 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1168
1169 /* strb r1, [r0], #1 */
1170 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1171 }}
1172
1173 break;
1174 }
1175
1176 case 2:
1177 {
1178 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1179
1180 u16 * buf16 = (u16*)buffer;
1181
1182 {size_t i;
1183 for (i = 0; i < count; i++)
1184 {
1185 /* MRC p14,0,r1,c0,c5,0 */
1186 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1187
1188 /* strh r1, [r0], #2 */
1189 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1190 }}
1191
1192 break;
1193 }
1194
1195 case 4:
1196 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1197
1198 if (!arm11_config_memwrite_burst)
1199 {
1200 /* STC p14,c5,[R0],#4 */
1201 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1202 }
1203 else
1204 {
1205 /* STC p14,c5,[R0],#4 */
1206 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1207 }
1208
1209 break;
1210 }
1211
1212 #if 1
1213 /* r0 verification */
1214 {
1215 u32 r0;
1216
1217 /* MCR p14,0,R0,c0,c5,0 */
1218 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1219
1220 if (address + size * count != r0)
1221 {
1222 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1223
1224 if (arm11_config_memwrite_burst)
1225 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1226
1227 if (arm11_config_memwrite_error_fatal)
1228 return ERROR_FAIL;
1229 }
1230 }
1231 #endif
1232
1233 arm11_run_instr_data_finish(arm11);
1234
1235 return ERROR_OK;
1236 }
1237
1238
1239 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1240 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1241 {
1242 FNC_INFO;
1243
1244 if (target->state != TARGET_HALTED)
1245 {
1246 LOG_WARNING("target was not halted");
1247 return ERROR_TARGET_NOT_HALTED;
1248 }
1249
1250 return arm11_write_memory(target, address, 4, count, buffer);
1251 }
1252
1253 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1254 {
1255 FNC_INFO_NOTIMPLEMENTED;
1256
1257 return ERROR_OK;
1258 }
1259
1260 /* target break-/watchpoint control
1261 * rw: 0 = write, 1 = read, 2 = access
1262 */
1263 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1264 {
1265 FNC_INFO;
1266
1267 arm11_common_t * arm11 = target->arch_info;
1268
1269 #if 0
1270 if (breakpoint->type == BKPT_SOFT)
1271 {
1272 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1273 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274 }
1275 #endif
1276
1277 if (!arm11->free_brps)
1278 {
1279 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1280 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1281 }
1282
1283 if (breakpoint->length != 4)
1284 {
1285 LOG_INFO("only breakpoints of four bytes length supported");
1286 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1287 }
1288
1289 arm11->free_brps--;
1290
1291 return ERROR_OK;
1292 }
1293
1294 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1295 {
1296 FNC_INFO;
1297
1298 arm11_common_t * arm11 = target->arch_info;
1299
1300 arm11->free_brps++;
1301
1302 return ERROR_OK;
1303 }
1304
1305 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1306 {
1307 FNC_INFO_NOTIMPLEMENTED;
1308
1309 return ERROR_OK;
1310 }
1311
1312 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1313 {
1314 FNC_INFO_NOTIMPLEMENTED;
1315
1316 return ERROR_OK;
1317 }
1318
1319 // HACKHACKHACK - FIXME mode/state
1320 /* target algorithm support */
1321 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1322 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1323 int timeout_ms, void *arch_info)
1324 {
1325 arm11_common_t *arm11 = target->arch_info;
1326 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1327 // enum armv4_5_state core_state = arm11->core_state;
1328 // enum armv4_5_mode core_mode = arm11->core_mode;
1329 u32 context[16];
1330 u32 cpsr;
1331 int exit_breakpoint_size = 0;
1332 int i;
1333 int retval = ERROR_OK;
1334 LOG_DEBUG("Running algorithm");
1335
1336 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1337 {
1338 LOG_ERROR("current target isn't an ARMV4/5 target");
1339 return ERROR_TARGET_INVALID;
1340 }
1341
1342 if (target->state != TARGET_HALTED)
1343 {
1344 LOG_WARNING("target not halted");
1345 return ERROR_TARGET_NOT_HALTED;
1346 }
1347
1348 // FIXME
1349 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1350 // return ERROR_FAIL;
1351
1352 // Save regs
1353 for (i = 0; i < 16; i++)
1354 {
1355 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1356 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1357 }
1358
1359 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1360 LOG_DEBUG("Save CPSR: 0x%x", cpsr);
1361
1362 for (i = 0; i < num_mem_params; i++)
1363 {
1364 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1365 }
1366
1367 // Set register parameters
1368 for (i = 0; i < num_reg_params; i++)
1369 {
1370 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1371 if (!reg)
1372 {
1373 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1374 exit(-1);
1375 }
1376
1377 if (reg->size != reg_params[i].size)
1378 {
1379 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1380 exit(-1);
1381 }
1382 arm11_set_reg(reg,reg_params[i].value);
1383 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1384 }
1385
1386 exit_breakpoint_size = 4;
1387
1388 /* arm11->core_state = arm11_algorithm_info->core_state;
1389 if (arm11->core_state == ARMV4_5_STATE_ARM)
1390 exit_breakpoint_size = 4;
1391 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1392 exit_breakpoint_size = 2;
1393 else
1394 {
1395 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1396 exit(-1);
1397 }
1398 */
1399 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1400 {
1401 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1402 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1403 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1404 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1405 }
1406
1407 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1408 {
1409 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1410 retval = ERROR_TARGET_FAILURE;
1411 goto restore;
1412 }
1413
1414 target_resume(target, 0, entry_point, 1, 0); // no debug, otherwise breakpoint is not set
1415
1416 target_wait_state(target, TARGET_HALTED, timeout_ms);
1417 if (target->state != TARGET_HALTED)
1418 {
1419 if ((retval=target_halt(target))!=ERROR_OK)
1420 return retval;
1421 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
1422 {
1423 return retval;
1424 }
1425 retval = ERROR_TARGET_TIMEOUT;
1426 goto del_breakpoint;
1427 }
1428
1429 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1430 {
1431 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1432 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1433 retval = ERROR_TARGET_TIMEOUT;
1434 goto del_breakpoint;
1435 }
1436
1437 for (i = 0; i < num_mem_params; i++)
1438 {
1439 if (mem_params[i].direction != PARAM_OUT)
1440 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1441 }
1442
1443 for (i = 0; i < num_reg_params; i++)
1444 {
1445 if (reg_params[i].direction != PARAM_OUT)
1446 {
1447 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1448 if (!reg)
1449 {
1450 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1451 exit(-1);
1452 }
1453
1454 if (reg->size != reg_params[i].size)
1455 {
1456 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1457 exit(-1);
1458 }
1459
1460 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1461 }
1462 }
1463
1464 del_breakpoint:
1465 breakpoint_remove(target, exit_point);
1466
1467 restore:
1468 // Restore context
1469 for (i = 0; i < 16; i++)
1470 {
1471 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1472 arm11->reg_list[i].name, context[i]);
1473 arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
1474 }
1475 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1476 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
1477
1478 // arm11->core_state = core_state;
1479 // arm11->core_mode = core_mode;
1480
1481 return retval;
1482 }
1483
1484 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1485 {
1486 FNC_INFO;
1487
1488 NEW(arm11_common_t, arm11, 1);
1489
1490 arm11->target = target;
1491
1492 /* prepare JTAG information for the new target */
1493 arm11->jtag_info.chain_pos = target->chain_position;
1494 arm11->jtag_info.scann_size = 5;
1495
1496 arm_jtag_setup_connection(&arm11->jtag_info);
1497
1498 jtag_device_t *device = jtag_get_device(target->chain_position);
1499
1500 if (device->ir_length != 5)
1501 {
1502 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1503 return ERROR_COMMAND_SYNTAX_ERROR;
1504 }
1505
1506 target->arch_info = arm11;
1507
1508 return ERROR_OK;
1509 }
1510
1511 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1512 {
1513 /* Initialize anything we can set up without talking to the target */
1514 return arm11_build_reg_cache(target);
1515
1516 }
1517
1518 /* talk to the target and set things up */
1519 int arm11_examine(struct target_s *target)
1520 {
1521 FNC_INFO;
1522 int retval;
1523
1524 arm11_common_t * arm11 = target->arch_info;
1525
1526 /* check IDCODE */
1527
1528 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1529
1530 scan_field_t idcode_field;
1531
1532 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1533
1534 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1535
1536 /* check DIDR */
1537
1538 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1539
1540 arm11_add_IR(arm11, ARM11_INTEST, -1);
1541
1542 scan_field_t chain0_fields[2];
1543
1544 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1545 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1546
1547 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1548
1549 if ((retval=jtag_execute_queue())!=ERROR_OK)
1550 return retval;
1551
1552
1553 switch (arm11->device_id & 0x0FFFF000)
1554 {
1555 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1556 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1557 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1558 default:
1559 {
1560 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1561 return ERROR_FAIL;
1562 }
1563 }
1564
1565 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1566
1567 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1568 arm11->debug_version != ARM11_DEBUG_V61)
1569 {
1570 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1571 return ERROR_FAIL;
1572 }
1573
1574
1575 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1576 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1577
1578 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1579 arm11->free_brps = arm11->brp;
1580 arm11->free_wrps = arm11->wrp;
1581
1582 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1583 arm11->device_id,
1584 arm11->implementor,
1585 arm11->didr);
1586
1587 /* as a side-effect this reads DSCR and thus
1588 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1589 * as suggested by the spec.
1590 */
1591
1592 arm11_check_init(arm11, NULL);
1593
1594 target->type->examined = 1;
1595
1596 return ERROR_OK;
1597 }
1598
1599 int arm11_quit(void)
1600 {
1601 FNC_INFO_NOTIMPLEMENTED;
1602
1603 return ERROR_OK;
1604 }
1605
1606 /** Load a register that is marked !valid in the register cache */
1607 int arm11_get_reg(reg_t *reg)
1608 {
1609 FNC_INFO;
1610
1611 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1612
1613 if (target->state != TARGET_HALTED)
1614 {
1615 LOG_WARNING("target was not halted");
1616 return ERROR_TARGET_NOT_HALTED;
1617 }
1618
1619 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1620
1621 #if 0
1622 arm11_common_t *arm11 = target->arch_info;
1623 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1624 #endif
1625
1626 return ERROR_OK;
1627 }
1628
1629 /** Change a value in the register cache */
1630 int arm11_set_reg(reg_t *reg, u8 *buf)
1631 {
1632 FNC_INFO;
1633
1634 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1635 arm11_common_t *arm11 = target->arch_info;
1636 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1637
1638 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1639 reg->valid = 1;
1640 reg->dirty = 1;
1641
1642 return ERROR_OK;
1643 }
1644
1645 int arm11_build_reg_cache(target_t *target)
1646 {
1647 arm11_common_t *arm11 = target->arch_info;
1648
1649 NEW(reg_cache_t, cache, 1);
1650 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1651 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1652
1653 if (arm11_regs_arch_type == -1)
1654 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1655
1656 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1657 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1658
1659 arm11->reg_list = reg_list;
1660
1661 /* Build the process context cache */
1662 cache->name = "arm11 registers";
1663 cache->next = NULL;
1664 cache->reg_list = reg_list;
1665 cache->num_regs = ARM11_REGCACHE_COUNT;
1666
1667 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1668 (*cache_p) = cache;
1669
1670 arm11->core_cache = cache;
1671 // armv7m->process_context = cache;
1672
1673 size_t i;
1674
1675 /* Not very elegant assertion */
1676 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1677 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1678 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1679 {
1680 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1681 exit(-1);
1682 }
1683
1684 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1685 {
1686 reg_t * r = reg_list + i;
1687 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1688 arm11_reg_state_t * rs = arm11_reg_states + i;
1689
1690 r->name = rd->name;
1691 r->size = 32;
1692 r->value = (u8 *)(arm11->reg_values + i);
1693 r->dirty = 0;
1694 r->valid = 0;
1695 r->bitfield_desc = NULL;
1696 r->num_bitfields = 0;
1697 r->arch_type = arm11_regs_arch_type;
1698 r->arch_info = rs;
1699
1700 rs->def_index = i;
1701 rs->target = target;
1702 }
1703 return ERROR_OK;
1704 }
1705
1706 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1707 {
1708 if (argc == 0)
1709 {
1710 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1711 return ERROR_OK;
1712 }
1713
1714 if (argc != 1)
1715 return ERROR_COMMAND_SYNTAX_ERROR;
1716
1717 switch (args[0][0])
1718 {
1719 case '0': /* 0 */
1720 case 'f': /* false */
1721 case 'F':
1722 case 'd': /* disable */
1723 case 'D':
1724 *var = false;
1725 break;
1726
1727 case '1': /* 1 */
1728 case 't': /* true */
1729 case 'T':
1730 case 'e': /* enable */
1731 case 'E':
1732 *var = true;
1733 break;
1734 }
1735
1736 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1737
1738 return ERROR_OK;
1739 }
1740
1741 #define BOOL_WRAPPER(name, print_name) \
1742 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1743 { \
1744 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1745 }
1746
1747 #define RC_TOP(name, descr, more) \
1748 { \
1749 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1750 command_t * top_cmd = new_cmd; \
1751 more \
1752 }
1753
1754 #define RC_FINAL(name, descr, handler) \
1755 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1756
1757 #define RC_FINAL_BOOL(name, descr, var) \
1758 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1759
1760 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1761 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1762
1763 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1764 {
1765 if (argc == 1)
1766 {
1767 arm11_vcr = strtoul(args[0], NULL, 0);
1768 }
1769 else if (argc != 0)
1770 {
1771 return ERROR_COMMAND_SYNTAX_ERROR;
1772 }
1773
1774 LOG_INFO("VCR 0x%08X", arm11_vcr);
1775 return ERROR_OK;
1776 }
1777
1778 const u32 arm11_coproc_instruction_limits[] =
1779 {
1780 15, /* coprocessor */
1781 7, /* opcode 1 */
1782 15, /* CRn */
1783 15, /* CRm */
1784 7, /* opcode 2 */
1785 0xFFFFFFFF, /* value */
1786 };
1787
1788 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1789 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1790
1791 arm11_common_t * arm11_find_target(const char * arg)
1792 {
1793 size_t jtag_target = strtoul(arg, NULL, 0);
1794
1795 {target_t * t;
1796 for (t = all_targets; t; t = t->next)
1797 {
1798 if (strcmp(t->type->name,"arm11"))
1799 continue;
1800
1801 arm11_common_t * arm11 = t->arch_info;
1802
1803 if (arm11->jtag_info.chain_pos != jtag_target)
1804 continue;
1805
1806 return arm11;
1807 }}
1808
1809 return 0;
1810 }
1811
1812 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1813 {
1814 if (argc != (read ? 6 : 7))
1815 {
1816 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1817 return -1;
1818 }
1819
1820 arm11_common_t * arm11 = arm11_find_target(args[0]);
1821
1822 if (!arm11)
1823 {
1824 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1825 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1826
1827 return -1;
1828
1829 }
1830
1831 if (arm11->target->state != TARGET_HALTED)
1832 {
1833 LOG_WARNING("target was not halted");
1834 return ERROR_TARGET_NOT_HALTED;
1835 }
1836
1837 u32 values[6];
1838
1839 {size_t i;
1840 for (i = 0; i < (read ? 5 : 6); i++)
1841 {
1842 values[i] = strtoul(args[i + 1], NULL, 0);
1843
1844 if (values[i] > arm11_coproc_instruction_limits[i])
1845 {
1846 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1847 (long)(i + 2), arm11_coproc_instruction_limits[i],
1848 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1849 return -1;
1850 }
1851 }}
1852
1853 u32 instr = 0xEE000010 |
1854 (values[0] << 8) |
1855 (values[1] << 21) |
1856 (values[2] << 16) |
1857 (values[3] << 0) |
1858 (values[4] << 5);
1859
1860 if (read)
1861 instr |= 0x00100000;
1862
1863 arm11_run_instr_data_prepare(arm11);
1864
1865 if (read)
1866 {
1867 u32 result;
1868 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1869
1870 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1871 values[0], values[1], values[2], values[3], values[4], result, result);
1872 }
1873 else
1874 {
1875 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1876
1877 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1878 values[0], values[1],
1879 values[5],
1880 values[2], values[3], values[4]);
1881 }
1882
1883 arm11_run_instr_data_finish(arm11);
1884
1885
1886 return ERROR_OK;
1887 }
1888
1889 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1890 {
1891 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1892 }
1893
1894 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1895 {
1896 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1897 }
1898
1899 int arm11_register_commands(struct command_context_s *cmd_ctx)
1900 {
1901 FNC_INFO;
1902
1903 command_t * top_cmd = NULL;
1904
1905 RC_TOP( "arm11", "arm11 specific commands",
1906
1907 RC_TOP( "memwrite", "Control memory write transfer mode",
1908
1909 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1910 memwrite_burst)
1911
1912 RC_FINAL_BOOL( "error_fatal",
1913 "Terminate program if transfer error was found (default: enabled)",
1914 memwrite_error_fatal)
1915 )
1916
1917 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1918 arm11_handle_vcr)
1919
1920 RC_FINAL( "mrc", "Read Coprocessor register",
1921 arm11_handle_mrc)
1922
1923 RC_FINAL( "mcr", "Write Coprocessor register",
1924 arm11_handle_mcr)
1925 )
1926
1927 return ERROR_OK;
1928 }
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