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ARM11: remove unused state and exports
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "etm.h"
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35 #include "algorithm.h"
36 #include "register.h"
37
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 static bool arm11_config_memwrite_burst = true;
44 static bool arm11_config_memwrite_error_fatal = true;
45 static uint32_t arm11_vcr = 0;
46 static bool arm11_config_step_irq_enable = false;
47 static bool arm11_config_hardware_step = false;
48
49 enum arm11_regtype
50 {
51 ARM11_REGISTER_CORE,
52 ARM11_REGISTER_CPSR,
53
54 ARM11_REGISTER_FX,
55 ARM11_REGISTER_FPS,
56
57 ARM11_REGISTER_FIQ,
58 ARM11_REGISTER_SVC,
59 ARM11_REGISTER_ABT,
60 ARM11_REGISTER_IRQ,
61 ARM11_REGISTER_UND,
62 ARM11_REGISTER_MON,
63
64 ARM11_REGISTER_SPSR_FIQ,
65 ARM11_REGISTER_SPSR_SVC,
66 ARM11_REGISTER_SPSR_ABT,
67 ARM11_REGISTER_SPSR_IRQ,
68 ARM11_REGISTER_SPSR_UND,
69 ARM11_REGISTER_SPSR_MON,
70
71 /* debug regs */
72 ARM11_REGISTER_DSCR,
73 ARM11_REGISTER_WDTR,
74 ARM11_REGISTER_RDTR,
75 };
76
77
78 struct arm11_reg_defs
79 {
80 char * name;
81 uint32_t num;
82 int gdb_num;
83 enum arm11_regtype type;
84 };
85
86 /* update arm11_regcache_ids when changing this */
87 static const struct arm11_reg_defs arm11_reg_defs[] =
88 {
89 {"r0", 0, 0, ARM11_REGISTER_CORE},
90 {"r1", 1, 1, ARM11_REGISTER_CORE},
91 {"r2", 2, 2, ARM11_REGISTER_CORE},
92 {"r3", 3, 3, ARM11_REGISTER_CORE},
93 {"r4", 4, 4, ARM11_REGISTER_CORE},
94 {"r5", 5, 5, ARM11_REGISTER_CORE},
95 {"r6", 6, 6, ARM11_REGISTER_CORE},
96 {"r7", 7, 7, ARM11_REGISTER_CORE},
97 {"r8", 8, 8, ARM11_REGISTER_CORE},
98 {"r9", 9, 9, ARM11_REGISTER_CORE},
99 {"r10", 10, 10, ARM11_REGISTER_CORE},
100 {"r11", 11, 11, ARM11_REGISTER_CORE},
101 {"r12", 12, 12, ARM11_REGISTER_CORE},
102 {"sp", 13, 13, ARM11_REGISTER_CORE},
103 {"lr", 14, 14, ARM11_REGISTER_CORE},
104 {"pc", 15, 15, ARM11_REGISTER_CORE},
105
106 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
107
108 /* Debug Registers */
109 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
110 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
111 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
112 };
113
114 enum arm11_regcache_ids
115 {
116 ARM11_RC_R0,
117 ARM11_RC_RX = ARM11_RC_R0,
118
119 ARM11_RC_R1,
120 ARM11_RC_R2,
121 ARM11_RC_R3,
122 ARM11_RC_R4,
123 ARM11_RC_R5,
124 ARM11_RC_R6,
125 ARM11_RC_R7,
126 ARM11_RC_R8,
127 ARM11_RC_R9,
128 ARM11_RC_R10,
129 ARM11_RC_R11,
130 ARM11_RC_R12,
131 ARM11_RC_R13,
132 ARM11_RC_SP = ARM11_RC_R13,
133 ARM11_RC_R14,
134 ARM11_RC_LR = ARM11_RC_R14,
135 ARM11_RC_R15,
136 ARM11_RC_PC = ARM11_RC_R15,
137
138 ARM11_RC_CPSR,
139
140 ARM11_RC_DSCR,
141 ARM11_RC_WDTR,
142 ARM11_RC_RDTR,
143
144 ARM11_RC_MAX,
145 };
146
147 /* GDB expects ARMs to give R0..R15, CPSR, and 7 FPA dummies */
148 #define ARM11_GDB_REGISTER_COUNT 26
149
150 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
151 static int arm11_step(struct target *target, int current,
152 uint32_t address, int handle_breakpoints);
153 /* helpers */
154 static int arm11_build_reg_cache(struct target *target);
155 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
156 static int arm11_get_reg(struct reg *reg);
157
158 static void arm11_record_register_history(struct arm11_common * arm11);
159 static void arm11_dump_reg_changes(struct arm11_common * arm11);
160
161
162 /** Check and if necessary take control of the system
163 *
164 * \param arm11 Target state variable.
165 * \param dscr If the current DSCR content is
166 * available a pointer to a word holding the
167 * DSCR can be passed. Otherwise use NULL.
168 */
169 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
170 {
171 uint32_t dscr_local_tmp_copy;
172
173 if (!dscr)
174 {
175 dscr = &dscr_local_tmp_copy;
176
177 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
178 }
179
180 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
181 {
182 LOG_DEBUG("Bringing target into debug mode");
183
184 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
185 arm11_write_DSCR(arm11, *dscr);
186
187 /* add further reset initialization here */
188
189 arm11->simulate_reset_on_next_halt = true;
190
191 if (*dscr & ARM11_DSCR_CORE_HALTED)
192 {
193 /** \todo TODO: this needs further scrutiny because
194 * arm11_on_enter_debug_state() never gets properly called.
195 * As a result we don't read the actual register states from
196 * the target.
197 */
198
199 arm11->target->state = TARGET_HALTED;
200 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
201 }
202 else
203 {
204 arm11->target->state = TARGET_RUNNING;
205 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
206 }
207
208 arm11_sc7_clear_vbw(arm11);
209 }
210
211 return ERROR_OK;
212 }
213
214
215
216 #define R(x) \
217 (arm11->reg_values[ARM11_RC_##x])
218
219 /** Save processor state.
220 *
221 * This is called when the HALT instruction has succeeded
222 * or on other occasions that stop the processor.
223 *
224 */
225 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
226 {
227 int retval;
228
229 for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
230 {
231 arm11->reg_list[i].valid = 1;
232 arm11->reg_list[i].dirty = 0;
233 }
234
235 /* Save DSCR */
236 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
237
238 /* Save wDTR */
239
240 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
241 {
242 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
243
244 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
245
246 struct scan_field chain5_fields[3];
247
248 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
249 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
250 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
251
252 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
253 }
254 else
255 {
256 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
257 }
258
259
260 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
261 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
262 ARM1136 seems to require this to issue ITR's as well */
263
264 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
265
266 /* this executes JTAG queue: */
267
268 arm11_write_DSCR(arm11, new_dscr);
269
270
271 /* From the spec:
272 Before executing any instruction in debug state you have to drain the write buffer.
273 This ensures that no imprecise Data Aborts can return at a later point:*/
274
275 /** \todo TODO: Test drain write buffer. */
276
277 #if 0
278 while (1)
279 {
280 /* MRC p14,0,R0,c5,c10,0 */
281 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
282
283 /* mcr 15, 0, r0, cr7, cr10, {4} */
284 arm11_run_instr_no_data1(arm11, 0xee070f9a);
285
286 uint32_t dscr = arm11_read_DSCR(arm11);
287
288 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
289
290 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
291 {
292 arm11_run_instr_no_data1(arm11, 0xe320f000);
293
294 dscr = arm11_read_DSCR(arm11);
295
296 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
297
298 break;
299 }
300 }
301 #endif
302
303 retval = arm11_run_instr_data_prepare(arm11);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* save r0 - r14 */
308
309 /** \todo TODO: handle other mode registers */
310
311 for (size_t i = 0; i < 15; i++)
312 {
313 /* MCR p14,0,R?,c0,c5,0 */
314 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
315 if (retval != ERROR_OK)
316 return retval;
317 }
318
319 /* save rDTR */
320
321 /* check rDTRfull in DSCR */
322
323 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
324 {
325 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
326 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
327 if (retval != ERROR_OK)
328 return retval;
329 }
330 else
331 {
332 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
333 }
334
335 /* save CPSR */
336
337 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
338 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
339 if (retval != ERROR_OK)
340 return retval;
341
342 /* save PC */
343
344 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
345 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
346 if (retval != ERROR_OK)
347 return retval;
348
349 /* adjust PC depending on ARM state */
350
351 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
352 {
353 arm11->reg_values[ARM11_RC_PC] -= 0;
354 }
355 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
356 {
357 arm11->reg_values[ARM11_RC_PC] -= 4;
358 }
359 else /* ARM state */
360 {
361 arm11->reg_values[ARM11_RC_PC] -= 8;
362 }
363
364 if (arm11->simulate_reset_on_next_halt)
365 {
366 arm11->simulate_reset_on_next_halt = false;
367
368 LOG_DEBUG("Reset c1 Control Register");
369
370 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
371
372 /* MCR p15,0,R0,c1,c0,0 */
373 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
374 if (retval != ERROR_OK)
375 return retval;
376
377 }
378
379 retval = arm11_run_instr_data_finish(arm11);
380 if (retval != ERROR_OK)
381 return retval;
382
383 arm11_dump_reg_changes(arm11);
384
385 return ERROR_OK;
386 }
387
388 static void arm11_dump_reg_changes(struct arm11_common * arm11)
389 {
390
391 if (!(debug_level >= LOG_LVL_DEBUG))
392 {
393 return;
394 }
395
396 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
397 {
398 if (!arm11->reg_list[i].valid)
399 {
400 if (arm11->reg_history[i].valid)
401 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
402 }
403 else
404 {
405 if (arm11->reg_history[i].valid)
406 {
407 if (arm11->reg_history[i].value != arm11->reg_values[i])
408 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
409 }
410 else
411 {
412 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
413 }
414 }
415 }
416 }
417
418 /** Restore processor state
419 *
420 * This is called in preparation for the RESTART function.
421 *
422 */
423 static int arm11_leave_debug_state(struct arm11_common *arm11)
424 {
425 int retval;
426
427 retval = arm11_run_instr_data_prepare(arm11);
428 if (retval != ERROR_OK)
429 return retval;
430
431 /** \todo TODO: handle other mode registers */
432
433 /* restore R1 - R14 */
434
435 for (unsigned i = 1; i < 15; i++)
436 {
437 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
438 continue;
439
440 /* MRC p14,0,r?,c0,c5,0 */
441 arm11_run_instr_data_to_core1(arm11,
442 0xee100e15 | (i << 12), R(RX + i));
443
444 // LOG_DEBUG("RESTORE R%u %08x", i, R(RX + i));
445 }
446
447 retval = arm11_run_instr_data_finish(arm11);
448 if (retval != ERROR_OK)
449 return retval;
450
451 /* spec says clear wDTR and rDTR; we assume they are clear as
452 otherwise our programming would be sloppy */
453 {
454 uint32_t DSCR;
455
456 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
457
458 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
459 {
460 /*
461 The wDTR/rDTR two registers that are used to send/receive data to/from
462 the core in tandem with corresponding instruction codes that are
463 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
464 registers hold data that was written by one side (CPU or JTAG) and not
465 read out by the other side.
466 */
467 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
468 return ERROR_FAIL;
469 }
470 }
471
472 retval = arm11_run_instr_data_prepare(arm11);
473 if (retval != ERROR_OK)
474 return retval;
475
476 /* restore original wDTR */
477
478 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
479 {
480 /* MCR p14,0,R0,c0,c5,0 */
481 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
482 if (retval != ERROR_OK)
483 return retval;
484 }
485
486 /* restore CPSR */
487
488 /* MSR CPSR,R0*/
489 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
490 if (retval != ERROR_OK)
491 return retval;
492
493
494 /* restore PC */
495
496 /* MOV PC,R0 */
497 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
498 if (retval != ERROR_OK)
499 return retval;
500
501
502 /* restore R0 */
503
504 /* MRC p14,0,r0,c0,c5,0 */
505 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
506
507 retval = arm11_run_instr_data_finish(arm11);
508 if (retval != ERROR_OK)
509 return retval;
510
511 /* restore DSCR */
512
513 arm11_write_DSCR(arm11, R(DSCR));
514
515 /* restore rDTR */
516
517 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
518 {
519 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
520
521 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
522
523 struct scan_field chain5_fields[3];
524
525 uint8_t Ready = 0; /* ignored */
526 uint8_t Valid = 0; /* ignored */
527
528 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
529 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
530 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
531
532 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
533 }
534
535 arm11_record_register_history(arm11);
536
537 return ERROR_OK;
538 }
539
540 static void arm11_record_register_history(struct arm11_common *arm11)
541 {
542 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
543 {
544 arm11->reg_history[i].value = arm11->reg_values[i];
545 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
546
547 arm11->reg_list[i].valid = 0;
548 arm11->reg_list[i].dirty = 0;
549 }
550 }
551
552
553 /* poll current target status */
554 static int arm11_poll(struct target *target)
555 {
556 int retval;
557 struct arm11_common *arm11 = target_to_arm11(target);
558 uint32_t dscr;
559
560 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
561
562 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
563
564 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
565
566 if (dscr & ARM11_DSCR_CORE_HALTED)
567 {
568 if (target->state != TARGET_HALTED)
569 {
570 enum target_state old_state = target->state;
571
572 LOG_DEBUG("enter TARGET_HALTED");
573 target->state = TARGET_HALTED;
574 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
575 retval = arm11_on_enter_debug_state(arm11);
576 if (retval != ERROR_OK)
577 return retval;
578
579 target_call_event_callbacks(target,
580 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
581 }
582 }
583 else
584 {
585 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
586 {
587 LOG_DEBUG("enter TARGET_RUNNING");
588 target->state = TARGET_RUNNING;
589 target->debug_reason = DBG_REASON_NOTHALTED;
590 }
591 }
592
593 return ERROR_OK;
594 }
595 /* architecture specific status reply */
596 static int arm11_arch_state(struct target *target)
597 {
598 struct arm11_common *arm11 = target_to_arm11(target);
599
600 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
601 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
602 R(CPSR),
603 R(PC));
604
605 return ERROR_OK;
606 }
607
608 /* target request support */
609 static int arm11_target_request_data(struct target *target,
610 uint32_t size, uint8_t *buffer)
611 {
612 LOG_WARNING("Not implemented: %s", __func__);
613
614 return ERROR_FAIL;
615 }
616
617 /* target execution control */
618 static int arm11_halt(struct target *target)
619 {
620 struct arm11_common *arm11 = target_to_arm11(target);
621
622 LOG_DEBUG("target->state: %s",
623 target_state_name(target));
624
625 if (target->state == TARGET_UNKNOWN)
626 {
627 arm11->simulate_reset_on_next_halt = true;
628 }
629
630 if (target->state == TARGET_HALTED)
631 {
632 LOG_DEBUG("target was already halted");
633 return ERROR_OK;
634 }
635
636 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
637
638 CHECK_RETVAL(jtag_execute_queue());
639
640 uint32_t dscr;
641
642 int i = 0;
643 while (1)
644 {
645 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
646
647 if (dscr & ARM11_DSCR_CORE_HALTED)
648 break;
649
650
651 long long then = 0;
652 if (i == 1000)
653 {
654 then = timeval_ms();
655 }
656 if (i >= 1000)
657 {
658 if ((timeval_ms()-then) > 1000)
659 {
660 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
661 return ERROR_FAIL;
662 }
663 }
664 i++;
665 }
666
667 arm11_on_enter_debug_state(arm11);
668
669 enum target_state old_state = target->state;
670
671 target->state = TARGET_HALTED;
672 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
673
674 CHECK_RETVAL(
675 target_call_event_callbacks(target,
676 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
677
678 return ERROR_OK;
679 }
680
681 static int arm11_resume(struct target *target, int current,
682 uint32_t address, int handle_breakpoints, int debug_execution)
683 {
684 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
685 // current, address, handle_breakpoints, debug_execution);
686
687 struct arm11_common *arm11 = target_to_arm11(target);
688
689 LOG_DEBUG("target->state: %s",
690 target_state_name(target));
691
692
693 if (target->state != TARGET_HALTED)
694 {
695 LOG_ERROR("Target not halted");
696 return ERROR_TARGET_NOT_HALTED;
697 }
698
699 if (!current)
700 R(PC) = address;
701
702 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
703
704 /* clear breakpoints/watchpoints and VCR*/
705 arm11_sc7_clear_vbw(arm11);
706
707 /* Set up breakpoints */
708 if (!debug_execution)
709 {
710 /* check if one matches PC and step over it if necessary */
711
712 struct breakpoint * bp;
713
714 for (bp = target->breakpoints; bp; bp = bp->next)
715 {
716 if (bp->address == R(PC))
717 {
718 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
719 arm11_step(target, 1, 0, 0);
720 break;
721 }
722 }
723
724 /* set all breakpoints */
725
726 unsigned brp_num = 0;
727
728 for (bp = target->breakpoints; bp; bp = bp->next)
729 {
730 struct arm11_sc7_action brp[2];
731
732 brp[0].write = 1;
733 brp[0].address = ARM11_SC7_BVR0 + brp_num;
734 brp[0].value = bp->address;
735 brp[1].write = 1;
736 brp[1].address = ARM11_SC7_BCR0 + brp_num;
737 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
738
739 arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
740
741 LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
742 bp->address);
743
744 brp_num++;
745 }
746
747 arm11_sc7_set_vcr(arm11, arm11_vcr);
748 }
749
750 arm11_leave_debug_state(arm11);
751
752 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
753
754 CHECK_RETVAL(jtag_execute_queue());
755
756 int i = 0;
757 while (1)
758 {
759 uint32_t dscr;
760
761 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
762
763 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
764
765 if (dscr & ARM11_DSCR_CORE_RESTARTED)
766 break;
767
768
769 long long then = 0;
770 if (i == 1000)
771 {
772 then = timeval_ms();
773 }
774 if (i >= 1000)
775 {
776 if ((timeval_ms()-then) > 1000)
777 {
778 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
779 return ERROR_FAIL;
780 }
781 }
782 i++;
783 }
784
785 if (!debug_execution)
786 {
787 target->state = TARGET_RUNNING;
788 target->debug_reason = DBG_REASON_NOTHALTED;
789
790 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
791 }
792 else
793 {
794 target->state = TARGET_DEBUG_RUNNING;
795 target->debug_reason = DBG_REASON_NOTHALTED;
796
797 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
798 }
799
800 return ERROR_OK;
801 }
802
803
804 static int armv4_5_to_arm11(int reg)
805 {
806 if (reg < 16)
807 return reg;
808 switch (reg)
809 {
810 case ARMV4_5_CPSR:
811 return ARM11_RC_CPSR;
812 case 16:
813 /* FIX!!! handle thumb better! */
814 return ARM11_RC_CPSR;
815 default:
816 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
817 exit(-1);
818 }
819 }
820
821
822 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
823 {
824 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
825
826 reg=armv4_5_to_arm11(reg);
827
828 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
829 }
830
831 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
832 int reg, uint32_t value)
833 {
834 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
835
836 reg=armv4_5_to_arm11(reg);
837
838 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
839 }
840
841 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
842 int pos, int bits)
843 {
844 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
845
846 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
847 }
848
849 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
850 {
851 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
852
853 /* FIX!!!! we should implement thumb for arm11 */
854 return ARMV4_5_STATE_ARM;
855 }
856
857 static void arm11_sim_set_state(struct arm_sim_interface *sim,
858 enum armv4_5_state mode)
859 {
860 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
861
862 /* FIX!!!! we should implement thumb for arm11 */
863 LOG_ERROR("Not implemented: %s", __func__);
864 }
865
866
867 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
868 {
869 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
870
871 /* FIX!!!! we should implement something that returns the current mode here!!! */
872 return ARMV4_5_MODE_USR;
873 }
874
875 static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
876 {
877 struct arm_sim_interface sim;
878
879 sim.user_data=target->arch_info;
880 sim.get_reg=&arm11_sim_get_reg;
881 sim.set_reg=&arm11_sim_set_reg;
882 sim.get_reg_mode=&arm11_sim_get_reg;
883 sim.set_reg_mode=&arm11_sim_set_reg;
884 sim.get_cpsr=&arm11_sim_get_cpsr;
885 sim.get_mode=&arm11_sim_get_mode;
886 sim.get_state=&arm11_sim_get_state;
887 sim.set_state=&arm11_sim_set_state;
888
889 return arm_simulate_step_core(target, dry_run_pc, &sim);
890
891 }
892
893 static int arm11_step(struct target *target, int current,
894 uint32_t address, int handle_breakpoints)
895 {
896 LOG_DEBUG("target->state: %s",
897 target_state_name(target));
898
899 if (target->state != TARGET_HALTED)
900 {
901 LOG_WARNING("target was not halted");
902 return ERROR_TARGET_NOT_HALTED;
903 }
904
905 struct arm11_common *arm11 = target_to_arm11(target);
906
907 if (!current)
908 R(PC) = address;
909
910 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
911
912
913 /** \todo TODO: Thumb not supported here */
914
915 uint32_t next_instruction;
916
917 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
918
919 /* skip over BKPT */
920 if ((next_instruction & 0xFFF00070) == 0xe1200070)
921 {
922 R(PC) += 4;
923 arm11->reg_list[ARM11_RC_PC].valid = 1;
924 arm11->reg_list[ARM11_RC_PC].dirty = 0;
925 LOG_DEBUG("Skipping BKPT");
926 }
927 /* skip over Wait for interrupt / Standby */
928 /* mcr 15, 0, r?, cr7, cr0, {4} */
929 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
930 {
931 R(PC) += 4;
932 arm11->reg_list[ARM11_RC_PC].valid = 1;
933 arm11->reg_list[ARM11_RC_PC].dirty = 0;
934 LOG_DEBUG("Skipping WFI");
935 }
936 /* ignore B to self */
937 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
938 {
939 LOG_DEBUG("Not stepping jump to self");
940 }
941 else
942 {
943 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
944 * with this. */
945
946 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
947 * the VCR might be something worth looking into. */
948
949
950 /* Set up breakpoint for stepping */
951
952 struct arm11_sc7_action brp[2];
953
954 brp[0].write = 1;
955 brp[0].address = ARM11_SC7_BVR0;
956 brp[1].write = 1;
957 brp[1].address = ARM11_SC7_BCR0;
958
959 if (arm11_config_hardware_step)
960 {
961 /* hardware single stepping be used if possible or is it better to
962 * always use the same code path? Hardware single stepping is not supported
963 * on all hardware
964 */
965 brp[0].value = R(PC);
966 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
967 } else
968 {
969 /* sets a breakpoint on the next PC(calculated by simulation),
970 */
971 uint32_t next_pc;
972 int retval;
973 retval = arm11_simulate_step(target, &next_pc);
974 if (retval != ERROR_OK)
975 return retval;
976
977 brp[0].value = next_pc;
978 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
979 }
980
981 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
982
983 /* resume */
984
985
986 if (arm11_config_step_irq_enable)
987 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
988 else
989 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
990
991
992 CHECK_RETVAL(arm11_leave_debug_state(arm11));
993
994 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
995
996 CHECK_RETVAL(jtag_execute_queue());
997
998 /* wait for halt */
999 int i = 0;
1000 while (1)
1001 {
1002 uint32_t dscr;
1003
1004 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1005
1006 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1007
1008 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1009 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1010 break;
1011
1012 long long then = 0;
1013 if (i == 1000)
1014 {
1015 then = timeval_ms();
1016 }
1017 if (i >= 1000)
1018 {
1019 if ((timeval_ms()-then) > 1000)
1020 {
1021 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1022 return ERROR_FAIL;
1023 }
1024 }
1025 i++;
1026 }
1027
1028 /* clear breakpoint */
1029 arm11_sc7_clear_vbw(arm11);
1030
1031 /* save state */
1032 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1033
1034 /* restore default state */
1035 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1036
1037 }
1038
1039 // target->state = TARGET_HALTED;
1040 target->debug_reason = DBG_REASON_SINGLESTEP;
1041
1042 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1043
1044 return ERROR_OK;
1045 }
1046
1047 static int arm11_assert_reset(struct target *target)
1048 {
1049 int retval;
1050 struct arm11_common *arm11 = target_to_arm11(target);
1051
1052 retval = arm11_check_init(arm11, NULL);
1053 if (retval != ERROR_OK)
1054 return retval;
1055
1056 target->state = TARGET_UNKNOWN;
1057
1058 /* we would very much like to reset into the halted, state,
1059 * but resetting and halting is second best... */
1060 if (target->reset_halt)
1061 {
1062 CHECK_RETVAL(target_halt(target));
1063 }
1064
1065
1066 /* srst is funny. We can not do *anything* else while it's asserted
1067 * and it has unkonwn side effects. Make sure no other code runs
1068 * meanwhile.
1069 *
1070 * Code below assumes srst:
1071 *
1072 * - Causes power-on-reset (but of what parts of the system?). Bug
1073 * in arm11?
1074 *
1075 * - Messes us TAP state without asserting trst.
1076 *
1077 * - There is another bug in the arm11 core. When you generate an access to
1078 * external logic (for example ddr controller via AHB bus) and that block
1079 * is not configured (perhaps it is still held in reset), that transaction
1080 * will never complete. This will hang arm11 core but it will also hang
1081 * JTAG controller. Nothing, short of srst assertion will bring it out of
1082 * this.
1083 *
1084 * Mysteries:
1085 *
1086 * - What should the PC be after an srst reset when starting in the halted
1087 * state?
1088 */
1089
1090 jtag_add_reset(0, 1);
1091 jtag_add_reset(0, 0);
1092
1093 /* How long do we have to wait? */
1094 jtag_add_sleep(5000);
1095
1096 /* un-mess up TAP state */
1097 jtag_add_tlr();
1098
1099 retval = jtag_execute_queue();
1100 if (retval != ERROR_OK)
1101 {
1102 return retval;
1103 }
1104
1105 return ERROR_OK;
1106 }
1107
1108 static int arm11_deassert_reset(struct target *target)
1109 {
1110 return ERROR_OK;
1111 }
1112
1113 static int arm11_soft_reset_halt(struct target *target)
1114 {
1115 LOG_WARNING("Not implemented: %s", __func__);
1116
1117 return ERROR_FAIL;
1118 }
1119
1120 /* target register access for gdb */
1121 static int arm11_get_gdb_reg_list(struct target *target,
1122 struct reg **reg_list[], int *reg_list_size)
1123 {
1124 struct arm11_common *arm11 = target_to_arm11(target);
1125
1126 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1127 *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
1128
1129 /* nine unused legacy FPA registers are expected by GDB */
1130 for (size_t i = 16; i < 24; i++)
1131 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1132 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1133
1134 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1135 {
1136 if (arm11_reg_defs[i].gdb_num == -1)
1137 continue;
1138
1139 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1140 }
1141
1142 return ERROR_OK;
1143 }
1144
1145 /* target memory access
1146 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1147 * count: number of items of <size>
1148 *
1149 * arm11_config_memrw_no_increment - in the future we may want to be able
1150 * to read/write a range of data to a "port". a "port" is an action on
1151 * read memory address for some peripheral.
1152 */
1153 static int arm11_read_memory_inner(struct target *target,
1154 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1155 bool arm11_config_memrw_no_increment)
1156 {
1157 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1158 int retval;
1159
1160 if (target->state != TARGET_HALTED)
1161 {
1162 LOG_WARNING("target was not halted");
1163 return ERROR_TARGET_NOT_HALTED;
1164 }
1165
1166 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1167
1168 struct arm11_common *arm11 = target_to_arm11(target);
1169
1170 retval = arm11_run_instr_data_prepare(arm11);
1171 if (retval != ERROR_OK)
1172 return retval;
1173
1174 /* MRC p14,0,r0,c0,c5,0 */
1175 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1176 if (retval != ERROR_OK)
1177 return retval;
1178
1179 switch (size)
1180 {
1181 case 1:
1182 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1183 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1184
1185 for (size_t i = 0; i < count; i++)
1186 {
1187 /* ldrb r1, [r0], #1 */
1188 /* ldrb r1, [r0] */
1189 arm11_run_instr_no_data1(arm11,
1190 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1191
1192 uint32_t res;
1193 /* MCR p14,0,R1,c0,c5,0 */
1194 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1195
1196 *buffer++ = res;
1197 }
1198
1199 break;
1200
1201 case 2:
1202 {
1203 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1204
1205 for (size_t i = 0; i < count; i++)
1206 {
1207 /* ldrh r1, [r0], #2 */
1208 arm11_run_instr_no_data1(arm11,
1209 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1210
1211 uint32_t res;
1212
1213 /* MCR p14,0,R1,c0,c5,0 */
1214 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1215
1216 uint16_t svalue = res;
1217 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1218 }
1219
1220 break;
1221 }
1222
1223 case 4:
1224 {
1225 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1226 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1227 uint32_t *words = (uint32_t *)buffer;
1228
1229 /* LDC p14,c5,[R0],#4 */
1230 /* LDC p14,c5,[R0] */
1231 arm11_run_instr_data_from_core(arm11, instr, words, count);
1232 break;
1233 }
1234 }
1235
1236 return arm11_run_instr_data_finish(arm11);
1237 }
1238
1239 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1240 {
1241 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1242 }
1243
1244 /*
1245 * arm11_config_memrw_no_increment - in the future we may want to be able
1246 * to read/write a range of data to a "port". a "port" is an action on
1247 * read memory address for some peripheral.
1248 */
1249 static int arm11_write_memory_inner(struct target *target,
1250 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1251 bool arm11_config_memrw_no_increment)
1252 {
1253 int retval;
1254
1255 if (target->state != TARGET_HALTED)
1256 {
1257 LOG_WARNING("target was not halted");
1258 return ERROR_TARGET_NOT_HALTED;
1259 }
1260
1261 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1262
1263 struct arm11_common *arm11 = target_to_arm11(target);
1264
1265 retval = arm11_run_instr_data_prepare(arm11);
1266 if (retval != ERROR_OK)
1267 return retval;
1268
1269 /* MRC p14,0,r0,c0,c5,0 */
1270 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1271 if (retval != ERROR_OK)
1272 return retval;
1273
1274 /* burst writes are not used for single words as those may well be
1275 * reset init script writes.
1276 *
1277 * The other advantage is that as burst writes are default, we'll
1278 * now exercise both burst and non-burst code paths with the
1279 * default settings, increasing code coverage.
1280 */
1281 bool burst = arm11_config_memwrite_burst && (count > 1);
1282
1283 switch (size)
1284 {
1285 case 1:
1286 {
1287 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1288
1289 for (size_t i = 0; i < count; i++)
1290 {
1291 /* MRC p14,0,r1,c0,c5,0 */
1292 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1293 if (retval != ERROR_OK)
1294 return retval;
1295
1296 /* strb r1, [r0], #1 */
1297 /* strb r1, [r0] */
1298 retval = arm11_run_instr_no_data1(arm11,
1299 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1300 if (retval != ERROR_OK)
1301 return retval;
1302 }
1303
1304 break;
1305 }
1306
1307 case 2:
1308 {
1309 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1310
1311 for (size_t i = 0; i < count; i++)
1312 {
1313 uint16_t value;
1314 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1315
1316 /* MRC p14,0,r1,c0,c5,0 */
1317 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1318 if (retval != ERROR_OK)
1319 return retval;
1320
1321 /* strh r1, [r0], #2 */
1322 /* strh r1, [r0] */
1323 retval = arm11_run_instr_no_data1(arm11,
1324 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1325 if (retval != ERROR_OK)
1326 return retval;
1327 }
1328
1329 break;
1330 }
1331
1332 case 4: {
1333 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1334
1335 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1336 uint32_t *words = (uint32_t*)buffer;
1337
1338 if (!burst)
1339 {
1340 /* STC p14,c5,[R0],#4 */
1341 /* STC p14,c5,[R0]*/
1342 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1343 if (retval != ERROR_OK)
1344 return retval;
1345 }
1346 else
1347 {
1348 /* STC p14,c5,[R0],#4 */
1349 /* STC p14,c5,[R0]*/
1350 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1351 if (retval != ERROR_OK)
1352 return retval;
1353 }
1354
1355 break;
1356 }
1357 }
1358
1359 /* r0 verification */
1360 if (!arm11_config_memrw_no_increment)
1361 {
1362 uint32_t r0;
1363
1364 /* MCR p14,0,R0,c0,c5,0 */
1365 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1366 if (retval != ERROR_OK)
1367 return retval;
1368
1369 if (address + size * count != r0)
1370 {
1371 LOG_ERROR("Data transfer failed. Expected end "
1372 "address 0x%08x, got 0x%08x",
1373 (unsigned) (address + size * count),
1374 (unsigned) r0);
1375
1376 if (burst)
1377 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1378
1379 if (arm11_config_memwrite_error_fatal)
1380 return ERROR_FAIL;
1381 }
1382 }
1383
1384 return arm11_run_instr_data_finish(arm11);
1385 }
1386
1387 static int arm11_write_memory(struct target *target,
1388 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1389 {
1390 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1391 }
1392
1393 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1394 static int arm11_bulk_write_memory(struct target *target,
1395 uint32_t address, uint32_t count, uint8_t *buffer)
1396 {
1397 if (target->state != TARGET_HALTED)
1398 {
1399 LOG_WARNING("target was not halted");
1400 return ERROR_TARGET_NOT_HALTED;
1401 }
1402
1403 return arm11_write_memory(target, address, 4, count, buffer);
1404 }
1405
1406 /* target break-/watchpoint control
1407 * rw: 0 = write, 1 = read, 2 = access
1408 */
1409 static int arm11_add_breakpoint(struct target *target,
1410 struct breakpoint *breakpoint)
1411 {
1412 struct arm11_common *arm11 = target_to_arm11(target);
1413
1414 #if 0
1415 if (breakpoint->type == BKPT_SOFT)
1416 {
1417 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1418 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1419 }
1420 #endif
1421
1422 if (!arm11->free_brps)
1423 {
1424 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1426 }
1427
1428 if (breakpoint->length != 4)
1429 {
1430 LOG_DEBUG("only breakpoints of four bytes length supported");
1431 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1432 }
1433
1434 arm11->free_brps--;
1435
1436 return ERROR_OK;
1437 }
1438
1439 static int arm11_remove_breakpoint(struct target *target,
1440 struct breakpoint *breakpoint)
1441 {
1442 struct arm11_common *arm11 = target_to_arm11(target);
1443
1444 arm11->free_brps++;
1445
1446 return ERROR_OK;
1447 }
1448
1449 static int arm11_add_watchpoint(struct target *target,
1450 struct watchpoint *watchpoint)
1451 {
1452 LOG_WARNING("Not implemented: %s", __func__);
1453
1454 return ERROR_FAIL;
1455 }
1456
1457 static int arm11_remove_watchpoint(struct target *target,
1458 struct watchpoint *watchpoint)
1459 {
1460 LOG_WARNING("Not implemented: %s", __func__);
1461
1462 return ERROR_FAIL;
1463 }
1464
1465 // HACKHACKHACK - FIXME mode/state
1466 /* target algorithm support */
1467 static int arm11_run_algorithm(struct target *target,
1468 int num_mem_params, struct mem_param *mem_params,
1469 int num_reg_params, struct reg_param *reg_params,
1470 uint32_t entry_point, uint32_t exit_point,
1471 int timeout_ms, void *arch_info)
1472 {
1473 struct arm11_common *arm11 = target_to_arm11(target);
1474 // enum armv4_5_state core_state = arm11->core_state;
1475 // enum armv4_5_mode core_mode = arm11->core_mode;
1476 uint32_t context[16];
1477 uint32_t cpsr;
1478 int exit_breakpoint_size = 0;
1479 int retval = ERROR_OK;
1480 LOG_DEBUG("Running algorithm");
1481
1482
1483 if (target->state != TARGET_HALTED)
1484 {
1485 LOG_WARNING("target not halted");
1486 return ERROR_TARGET_NOT_HALTED;
1487 }
1488
1489 // FIXME
1490 // if (!is_arm_mode(arm11->core_mode))
1491 // return ERROR_FAIL;
1492
1493 // Save regs
1494 for (unsigned i = 0; i < 16; i++)
1495 {
1496 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1497 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1498 }
1499
1500 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1501 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1502
1503 for (int i = 0; i < num_mem_params; i++)
1504 {
1505 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1506 }
1507
1508 // Set register parameters
1509 for (int i = 0; i < num_reg_params; i++)
1510 {
1511 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1512 if (!reg)
1513 {
1514 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1515 return ERROR_INVALID_ARGUMENTS;
1516 }
1517
1518 if (reg->size != reg_params[i].size)
1519 {
1520 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1521 return ERROR_INVALID_ARGUMENTS;
1522 }
1523 arm11_set_reg(reg,reg_params[i].value);
1524 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1525 }
1526
1527 exit_breakpoint_size = 4;
1528
1529 /* arm11->core_state = arm11_algorithm_info->core_state;
1530 if (arm11->core_state == ARMV4_5_STATE_ARM)
1531 exit_breakpoint_size = 4;
1532 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1533 exit_breakpoint_size = 2;
1534 else
1535 {
1536 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1537 exit(-1);
1538 }
1539 */
1540
1541
1542 /* arm11 at this point only supports ARM not THUMB mode
1543 however if this test needs to be reactivated the current state can be read back
1544 from CPSR */
1545 #if 0
1546 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1547 {
1548 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1549 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1550 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1551 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1552 }
1553 #endif
1554
1555 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1556 {
1557 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1558 retval = ERROR_TARGET_FAILURE;
1559 goto restore;
1560 }
1561
1562 // no debug, otherwise breakpoint is not set
1563 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1564
1565 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1566
1567 if (target->state != TARGET_HALTED)
1568 {
1569 CHECK_RETVAL(target_halt(target));
1570
1571 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1572
1573 retval = ERROR_TARGET_TIMEOUT;
1574
1575 goto del_breakpoint;
1576 }
1577
1578 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1579 {
1580 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1581 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1582 retval = ERROR_TARGET_TIMEOUT;
1583 goto del_breakpoint;
1584 }
1585
1586 for (int i = 0; i < num_mem_params; i++)
1587 {
1588 if (mem_params[i].direction != PARAM_OUT)
1589 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1590 }
1591
1592 for (int i = 0; i < num_reg_params; i++)
1593 {
1594 if (reg_params[i].direction != PARAM_OUT)
1595 {
1596 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1597 if (!reg)
1598 {
1599 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1600 retval = ERROR_INVALID_ARGUMENTS;
1601 goto del_breakpoint;
1602 }
1603
1604 if (reg->size != reg_params[i].size)
1605 {
1606 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1607 retval = ERROR_INVALID_ARGUMENTS;
1608 goto del_breakpoint;
1609 }
1610
1611 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1612 }
1613 }
1614
1615 del_breakpoint:
1616 breakpoint_remove(target, exit_point);
1617
1618 restore:
1619 // Restore context
1620 for (size_t i = 0; i < 16; i++)
1621 {
1622 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1623 arm11->reg_list[i].name, context[i]);
1624 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1625 }
1626 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1627 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1628
1629 // arm11->core_state = core_state;
1630 // arm11->core_mode = core_mode;
1631
1632 return retval;
1633 }
1634
1635 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1636 {
1637 struct arm11_common *arm11;
1638
1639 if (target->tap == NULL)
1640 return ERROR_FAIL;
1641
1642 if (target->tap->ir_length != 5)
1643 {
1644 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1645 return ERROR_COMMAND_SYNTAX_ERROR;
1646 }
1647
1648 arm11 = calloc(1, sizeof *arm11);
1649 if (!arm11)
1650 return ERROR_FAIL;
1651
1652 armv4_5_init_arch_info(target, &arm11->arm);
1653
1654 arm11->target = target;
1655
1656 arm11->jtag_info.tap = target->tap;
1657 arm11->jtag_info.scann_size = 5;
1658 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1659 /* cur_scan_chain == 0 */
1660 arm11->jtag_info.intest_instr = ARM11_INTEST;
1661
1662 return ERROR_OK;
1663 }
1664
1665 static int arm11_init_target(struct command_context *cmd_ctx,
1666 struct target *target)
1667 {
1668 /* Initialize anything we can set up without talking to the target */
1669
1670 /* FIXME Switch to use the standard build_reg_cache() not custom
1671 * code. Do it from examine(), after we check whether we're
1672 * an arm1176 and thus support the Secure Monitor mode.
1673 */
1674 return arm11_build_reg_cache(target);
1675 }
1676
1677 /* talk to the target and set things up */
1678 static int arm11_examine(struct target *target)
1679 {
1680 int retval;
1681 char *type;
1682 struct arm11_common *arm11 = target_to_arm11(target);
1683 uint32_t didr, device_id;
1684 uint8_t implementor;
1685
1686 /* check IDCODE */
1687
1688 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1689
1690 struct scan_field idcode_field;
1691
1692 arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1693
1694 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1695
1696 /* check DIDR */
1697
1698 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1699
1700 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1701
1702 struct scan_field chain0_fields[2];
1703
1704 arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1705 arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
1706
1707 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1708
1709 CHECK_RETVAL(jtag_execute_queue());
1710
1711 switch (device_id & 0x0FFFF000)
1712 {
1713 case 0x07B36000:
1714 type = "ARM1136";
1715 break;
1716 case 0x07B56000:
1717 type = "ARM1156";
1718 break;
1719 case 0x07B76000:
1720 arm11->arm.core_type = ARM_MODE_MON;
1721 type = "ARM1176";
1722 break;
1723 default:
1724 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1725 return ERROR_FAIL;
1726 }
1727 LOG_INFO("found %s", type);
1728
1729 /* unlikely this could ever fail, but ... */
1730 switch ((didr >> 16) & 0x0F) {
1731 case ARM11_DEBUG_V6:
1732 case ARM11_DEBUG_V61: /* supports security extensions */
1733 break;
1734 default:
1735 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1736 return ERROR_FAIL;
1737 }
1738
1739 arm11->brp = ((didr >> 24) & 0x0F) + 1;
1740 arm11->wrp = ((didr >> 28) & 0x0F) + 1;
1741
1742 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1743 arm11->free_brps = arm11->brp;
1744 arm11->free_wrps = arm11->wrp;
1745
1746 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1747 device_id, implementor, didr);
1748
1749 /* as a side-effect this reads DSCR and thus
1750 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1751 * as suggested by the spec.
1752 */
1753
1754 retval = arm11_check_init(arm11, NULL);
1755 if (retval != ERROR_OK)
1756 return retval;
1757
1758 /* ETM on ARM11 still uses original scanchain 6 access mode */
1759 if (arm11->arm.etm && !target_was_examined(target)) {
1760 *register_get_last_cache_p(&target->reg_cache) =
1761 etm_build_reg_cache(target, &arm11->jtag_info,
1762 arm11->arm.etm);
1763 retval = etm_setup(target);
1764 }
1765
1766 target_set_examined(target);
1767
1768 return ERROR_OK;
1769 }
1770
1771
1772 /** Load a register that is marked !valid in the register cache */
1773 static int arm11_get_reg(struct reg *reg)
1774 {
1775 struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1776
1777 if (target->state != TARGET_HALTED)
1778 {
1779 LOG_WARNING("target was not halted");
1780 return ERROR_TARGET_NOT_HALTED;
1781 }
1782
1783 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1784
1785 #if 0
1786 struct arm11_common *arm11 = target_to_arm11(target);
1787 const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1788 #endif
1789
1790 return ERROR_OK;
1791 }
1792
1793 /** Change a value in the register cache */
1794 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1795 {
1796 struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
1797 struct arm11_common *arm11 = target_to_arm11(target);
1798 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1799
1800 arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1801 reg->valid = 1;
1802 reg->dirty = 1;
1803
1804 return ERROR_OK;
1805 }
1806
1807 static const struct reg_arch_type arm11_reg_type = {
1808 .get = arm11_get_reg,
1809 .set = arm11_set_reg,
1810 };
1811
1812 static int arm11_build_reg_cache(struct target *target)
1813 {
1814 struct arm11_common *arm11 = target_to_arm11(target);
1815 struct reg_cache *cache;
1816 struct reg *reg_list;
1817 struct arm11_reg_state *arm11_reg_states;
1818
1819 cache = calloc(1, sizeof *cache);
1820 reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
1821 arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
1822 sizeof *arm11_reg_states);
1823 if (!cache || !reg_list || !arm11_reg_states) {
1824 free(cache);
1825 free(reg_list);
1826 free(arm11_reg_states);
1827 return ERROR_FAIL;
1828 }
1829
1830 arm11->reg_list = reg_list;
1831
1832 /* Build the process context cache */
1833 cache->name = "arm11 registers";
1834 cache->next = NULL;
1835 cache->reg_list = reg_list;
1836 cache->num_regs = ARM11_REGCACHE_COUNT;
1837
1838 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1839 (*cache_p) = cache;
1840
1841 arm11->core_cache = cache;
1842 // armv7m->process_context = cache;
1843
1844 size_t i;
1845
1846 /* Not very elegant assertion */
1847 if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1848 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1849 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1850 {
1851 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
1852 ARM11_REGCACHE_COUNT,
1853 (unsigned) ARRAY_SIZE(arm11->reg_values),
1854 (unsigned) ARRAY_SIZE(arm11_reg_defs),
1855 ARM11_RC_MAX);
1856 /* FIXME minimally, use a build_bug_on(X) mechanism;
1857 * runtime exit() here is bad!
1858 */
1859 exit(-1);
1860 }
1861
1862 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1863 {
1864 struct reg * r = reg_list + i;
1865 const struct arm11_reg_defs * rd = arm11_reg_defs + i;
1866 struct arm11_reg_state * rs = arm11_reg_states + i;
1867
1868 r->name = rd->name;
1869 r->size = 32;
1870 r->value = (uint8_t *)(arm11->reg_values + i);
1871 r->dirty = 0;
1872 r->valid = 0;
1873 r->type = &arm11_reg_type;
1874 r->arch_info = rs;
1875
1876 rs->def_index = i;
1877 rs->target = target;
1878 }
1879
1880 return ERROR_OK;
1881 }
1882
1883 #define ARM11_BOOL_WRAPPER(name, print_name) \
1884 COMMAND_HANDLER(arm11_handle_bool_##name) \
1885 { \
1886 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1887 &arm11_config_##name, print_name); \
1888 }
1889
1890 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1891 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1892 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1893 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1894
1895 COMMAND_HANDLER(arm11_handle_vcr)
1896 {
1897 switch (CMD_ARGC) {
1898 case 0:
1899 break;
1900 case 1:
1901 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1902 break;
1903 default:
1904 return ERROR_COMMAND_SYNTAX_ERROR;
1905 }
1906
1907 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1908 return ERROR_OK;
1909 }
1910
1911 static const uint32_t arm11_coproc_instruction_limits[] =
1912 {
1913 15, /* coprocessor */
1914 7, /* opcode 1 */
1915 15, /* CRn */
1916 15, /* CRm */
1917 7, /* opcode 2 */
1918 0xFFFFFFFF, /* value */
1919 };
1920
1921 static int arm11_mrc_inner(struct target *target, int cpnum,
1922 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
1923 uint32_t *value, bool read)
1924 {
1925 int retval;
1926 struct arm11_common *arm11 = target_to_arm11(target);
1927
1928 if (target->state != TARGET_HALTED)
1929 {
1930 LOG_ERROR("Target not halted");
1931 return ERROR_FAIL;
1932 }
1933
1934 uint32_t instr = 0xEE000010 |
1935 (cpnum << 8) |
1936 (op1 << 21) |
1937 (CRn << 16) |
1938 (CRm << 0) |
1939 (op2 << 5);
1940
1941 if (read)
1942 instr |= 0x00100000;
1943
1944 retval = arm11_run_instr_data_prepare(arm11);
1945 if (retval != ERROR_OK)
1946 return retval;
1947
1948 if (read)
1949 {
1950 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
1951 if (retval != ERROR_OK)
1952 return retval;
1953 }
1954 else
1955 {
1956 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
1957 if (retval != ERROR_OK)
1958 return retval;
1959 }
1960
1961 return arm11_run_instr_data_finish(arm11);
1962 }
1963
1964 static int arm11_mrc(struct target *target, int cpnum,
1965 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
1966 {
1967 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
1968 }
1969
1970 static int arm11_mcr(struct target *target, int cpnum,
1971 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
1972 {
1973 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
1974 }
1975
1976 static int arm11_register_commands(struct command_context *cmd_ctx)
1977 {
1978 struct command *top_cmd, *mw_cmd;
1979
1980 armv4_5_register_commands(cmd_ctx);
1981
1982 top_cmd = register_command(cmd_ctx, NULL, "arm11",
1983 NULL, COMMAND_ANY, NULL);
1984
1985 /* "hardware_step" is only here to check if the default
1986 * simulate + breakpoint implementation is broken.
1987 * TEMPORARY! NOT DOCUMENTED!
1988 */
1989 register_command(cmd_ctx, top_cmd, "hardware_step",
1990 arm11_handle_bool_hardware_step, COMMAND_ANY,
1991 "DEBUG ONLY - Hardware single stepping"
1992 " (default: disabled)");
1993
1994 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
1995 NULL, COMMAND_ANY, NULL);
1996 register_command(cmd_ctx, mw_cmd, "burst",
1997 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
1998 "Enable/Disable non-standard but fast burst mode"
1999 " (default: enabled)");
2000 register_command(cmd_ctx, mw_cmd, "error_fatal",
2001 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2002 "Terminate program if transfer error was found"
2003 " (default: enabled)");
2004
2005 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2006 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2007 "Enable interrupts while stepping"
2008 " (default: disabled)");
2009 register_command(cmd_ctx, top_cmd, "vcr",
2010 arm11_handle_vcr, COMMAND_ANY,
2011 "Control (Interrupt) Vector Catch Register");
2012
2013 return etm_register_commands(cmd_ctx);
2014 }
2015
2016 /** Holds methods for ARM11xx targets. */
2017 struct target_type arm11_target = {
2018 .name = "arm11",
2019
2020 .poll = arm11_poll,
2021 .arch_state = arm11_arch_state,
2022
2023 .target_request_data = arm11_target_request_data,
2024
2025 .halt = arm11_halt,
2026 .resume = arm11_resume,
2027 .step = arm11_step,
2028
2029 .assert_reset = arm11_assert_reset,
2030 .deassert_reset = arm11_deassert_reset,
2031 .soft_reset_halt = arm11_soft_reset_halt,
2032
2033 .get_gdb_reg_list = arm11_get_gdb_reg_list,
2034
2035 .read_memory = arm11_read_memory,
2036 .write_memory = arm11_write_memory,
2037
2038 .bulk_write_memory = arm11_bulk_write_memory,
2039
2040 .checksum_memory = arm_checksum_memory,
2041 .blank_check_memory = arm_blank_check_memory,
2042
2043 .add_breakpoint = arm11_add_breakpoint,
2044 .remove_breakpoint = arm11_remove_breakpoint,
2045 .add_watchpoint = arm11_add_watchpoint,
2046 .remove_watchpoint = arm11_remove_watchpoint,
2047
2048 .run_algorithm = arm11_run_algorithm,
2049
2050 .register_commands = arm11_register_commands,
2051 .target_create = arm11_target_create,
2052 .init_target = arm11_init_target,
2053 .examine = arm11_examine,
2054
2055 .mrc = arm11_mrc,
2056 .mcr = arm11_mcr,
2057 };
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