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arm11 single stepping wip
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "target_type.h"
33
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 uint32_t arm11_vcr = 0;
56 bool arm11_config_memrw_no_increment = false;
57 bool arm11_config_step_irq_enable = false;
58
59 #define ARM11_HANDLER(x) \
60 .x = arm11_##x
61
62 target_type_t arm11_target =
63 {
64 .name = "arm11",
65
66 ARM11_HANDLER(poll),
67 ARM11_HANDLER(arch_state),
68
69 ARM11_HANDLER(target_request_data),
70
71 ARM11_HANDLER(halt),
72 ARM11_HANDLER(resume),
73 ARM11_HANDLER(step),
74
75 ARM11_HANDLER(assert_reset),
76 ARM11_HANDLER(deassert_reset),
77 ARM11_HANDLER(soft_reset_halt),
78
79 ARM11_HANDLER(get_gdb_reg_list),
80
81 ARM11_HANDLER(read_memory),
82 ARM11_HANDLER(write_memory),
83
84 ARM11_HANDLER(bulk_write_memory),
85
86 ARM11_HANDLER(checksum_memory),
87
88 ARM11_HANDLER(add_breakpoint),
89 ARM11_HANDLER(remove_breakpoint),
90 ARM11_HANDLER(add_watchpoint),
91 ARM11_HANDLER(remove_watchpoint),
92
93 ARM11_HANDLER(run_algorithm),
94
95 ARM11_HANDLER(register_commands),
96 ARM11_HANDLER(target_create),
97 ARM11_HANDLER(init_target),
98 ARM11_HANDLER(examine),
99 ARM11_HANDLER(quit),
100 };
101
102 int arm11_regs_arch_type = -1;
103
104
105 enum arm11_regtype
106 {
107 ARM11_REGISTER_CORE,
108 ARM11_REGISTER_CPSR,
109
110 ARM11_REGISTER_FX,
111 ARM11_REGISTER_FPS,
112
113 ARM11_REGISTER_FIQ,
114 ARM11_REGISTER_SVC,
115 ARM11_REGISTER_ABT,
116 ARM11_REGISTER_IRQ,
117 ARM11_REGISTER_UND,
118 ARM11_REGISTER_MON,
119
120 ARM11_REGISTER_SPSR_FIQ,
121 ARM11_REGISTER_SPSR_SVC,
122 ARM11_REGISTER_SPSR_ABT,
123 ARM11_REGISTER_SPSR_IRQ,
124 ARM11_REGISTER_SPSR_UND,
125 ARM11_REGISTER_SPSR_MON,
126
127 /* debug regs */
128 ARM11_REGISTER_DSCR,
129 ARM11_REGISTER_WDTR,
130 ARM11_REGISTER_RDTR,
131 };
132
133
134 typedef struct arm11_reg_defs_s
135 {
136 char * name;
137 uint32_t num;
138 int gdb_num;
139 enum arm11_regtype type;
140 } arm11_reg_defs_t;
141
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs[] =
144 {
145 {"r0", 0, 0, ARM11_REGISTER_CORE},
146 {"r1", 1, 1, ARM11_REGISTER_CORE},
147 {"r2", 2, 2, ARM11_REGISTER_CORE},
148 {"r3", 3, 3, ARM11_REGISTER_CORE},
149 {"r4", 4, 4, ARM11_REGISTER_CORE},
150 {"r5", 5, 5, ARM11_REGISTER_CORE},
151 {"r6", 6, 6, ARM11_REGISTER_CORE},
152 {"r7", 7, 7, ARM11_REGISTER_CORE},
153 {"r8", 8, 8, ARM11_REGISTER_CORE},
154 {"r9", 9, 9, ARM11_REGISTER_CORE},
155 {"r10", 10, 10, ARM11_REGISTER_CORE},
156 {"r11", 11, 11, ARM11_REGISTER_CORE},
157 {"r12", 12, 12, ARM11_REGISTER_CORE},
158 {"sp", 13, 13, ARM11_REGISTER_CORE},
159 {"lr", 14, 14, ARM11_REGISTER_CORE},
160 {"pc", 15, 15, ARM11_REGISTER_CORE},
161
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX},
164 {"f1", 1, 17, ARM11_REGISTER_FX},
165 {"f2", 2, 18, ARM11_REGISTER_FX},
166 {"f3", 3, 19, ARM11_REGISTER_FX},
167 {"f4", 4, 20, ARM11_REGISTER_FX},
168 {"f5", 5, 21, ARM11_REGISTER_FX},
169 {"f6", 6, 22, ARM11_REGISTER_FX},
170 {"f7", 7, 23, ARM11_REGISTER_FX},
171 {"fps", 0, 24, ARM11_REGISTER_FPS},
172 #endif
173
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
175
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
185
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
189
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
193
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
197
198 {"r13_und", 13, -1, ARM11_REGISTER_UND},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
201
202 /* ARM1176 only */
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
206 #endif
207
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
212 };
213
214 enum arm11_regcache_ids
215 {
216 ARM11_RC_R0,
217 ARM11_RC_RX = ARM11_RC_R0,
218
219 ARM11_RC_R1,
220 ARM11_RC_R2,
221 ARM11_RC_R3,
222 ARM11_RC_R4,
223 ARM11_RC_R5,
224 ARM11_RC_R6,
225 ARM11_RC_R7,
226 ARM11_RC_R8,
227 ARM11_RC_R9,
228 ARM11_RC_R10,
229 ARM11_RC_R11,
230 ARM11_RC_R12,
231 ARM11_RC_R13,
232 ARM11_RC_SP = ARM11_RC_R13,
233 ARM11_RC_R14,
234 ARM11_RC_LR = ARM11_RC_R14,
235 ARM11_RC_R15,
236 ARM11_RC_PC = ARM11_RC_R15,
237
238 #if ARM11_REGCACHE_FREGS
239 ARM11_RC_F0,
240 ARM11_RC_FX = ARM11_RC_F0,
241 ARM11_RC_F1,
242 ARM11_RC_F2,
243 ARM11_RC_F3,
244 ARM11_RC_F4,
245 ARM11_RC_F5,
246 ARM11_RC_F6,
247 ARM11_RC_F7,
248 ARM11_RC_FPS,
249 #endif
250
251 ARM11_RC_CPSR,
252
253 #if ARM11_REGCACHE_MODEREGS
254 ARM11_RC_R8_FIQ,
255 ARM11_RC_R9_FIQ,
256 ARM11_RC_R10_FIQ,
257 ARM11_RC_R11_FIQ,
258 ARM11_RC_R12_FIQ,
259 ARM11_RC_R13_FIQ,
260 ARM11_RC_R14_FIQ,
261 ARM11_RC_SPSR_FIQ,
262
263 ARM11_RC_R13_SVC,
264 ARM11_RC_R14_SVC,
265 ARM11_RC_SPSR_SVC,
266
267 ARM11_RC_R13_ABT,
268 ARM11_RC_R14_ABT,
269 ARM11_RC_SPSR_ABT,
270
271 ARM11_RC_R13_IRQ,
272 ARM11_RC_R14_IRQ,
273 ARM11_RC_SPSR_IRQ,
274
275 ARM11_RC_R13_UND,
276 ARM11_RC_R14_UND,
277 ARM11_RC_SPSR_UND,
278
279 ARM11_RC_R13_MON,
280 ARM11_RC_R14_MON,
281 ARM11_RC_SPSR_MON,
282 #endif
283
284 ARM11_RC_DSCR,
285 ARM11_RC_WDTR,
286 ARM11_RC_RDTR,
287
288 ARM11_RC_MAX,
289 };
290
291 #define ARM11_GDB_REGISTER_COUNT 26
292
293 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
294
295 reg_t arm11_gdb_dummy_fp_reg =
296 {
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 };
299
300 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
301
302 reg_t arm11_gdb_dummy_fps_reg =
303 {
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
305 };
306
307
308
309 /** Check and if necessary take control of the system
310 *
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
315 */
316 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
317 {
318 FNC_INFO;
319
320 uint32_t dscr_local_tmp_copy;
321
322 if (!dscr)
323 {
324 dscr = &dscr_local_tmp_copy;
325
326 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
327 }
328
329 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
330 {
331 LOG_DEBUG("Bringing target into debug mode");
332
333 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
334 arm11_write_DSCR(arm11, *dscr);
335
336 /* add further reset initialization here */
337
338 arm11->simulate_reset_on_next_halt = true;
339
340 if (*dscr & ARM11_DSCR_CORE_HALTED)
341 {
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called.
344 * As a result we don't read the actual register states from
345 * the target.
346 */
347
348 arm11->target->state = TARGET_HALTED;
349 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
350 }
351 else
352 {
353 arm11->target->state = TARGET_RUNNING;
354 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
355 }
356
357 arm11_sc7_clear_vbw(arm11);
358 }
359
360 return ERROR_OK;
361 }
362
363
364
365 #define R(x) \
366 (arm11->reg_values[ARM11_RC_##x])
367
368 /** Save processor state.
369 *
370 * This is called when the HALT instruction has succeeded
371 * or on other occasions that stop the processor.
372 *
373 */
374 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
375 {
376 FNC_INFO;
377
378 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
379 {
380 arm11->reg_list[i].valid = 1;
381 arm11->reg_list[i].dirty = 0;
382 }
383
384 /* Save DSCR */
385 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
386
387 /* Save wDTR */
388
389 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
390 {
391 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
392
393 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
394
395 scan_field_t chain5_fields[3];
396
397 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
398 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
399 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
400
401 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
402 }
403 else
404 {
405 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
406 }
407
408
409 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
410 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
411 ARM1136 seems to require this to issue ITR's as well */
412
413 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
414
415 /* this executes JTAG queue: */
416
417 arm11_write_DSCR(arm11, new_dscr);
418
419
420 /* From the spec:
421 Before executing any instruction in debug state you have to drain the write buffer.
422 This ensures that no imprecise Data Aborts can return at a later point:*/
423
424 /** \todo TODO: Test drain write buffer. */
425
426 #if 0
427 while (1)
428 {
429 /* MRC p14,0,R0,c5,c10,0 */
430 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
431
432 /* mcr 15, 0, r0, cr7, cr10, {4} */
433 arm11_run_instr_no_data1(arm11, 0xee070f9a);
434
435 uint32_t dscr = arm11_read_DSCR(arm11);
436
437 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
438
439 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
440 {
441 arm11_run_instr_no_data1(arm11, 0xe320f000);
442
443 dscr = arm11_read_DSCR(arm11);
444
445 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
446
447 break;
448 }
449 }
450 #endif
451
452 arm11_run_instr_data_prepare(arm11);
453
454 /* save r0 - r14 */
455
456 /** \todo TODO: handle other mode registers */
457
458 for (size_t i = 0; i < 15; i++)
459 {
460 /* MCR p14,0,R?,c0,c5,0 */
461 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
462 }
463
464 /* save rDTR */
465
466 /* check rDTRfull in DSCR */
467
468 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
469 {
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
472 }
473 else
474 {
475 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
476 }
477
478 /* save CPSR */
479
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
482
483 /* save PC */
484
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
487
488 /* adjust PC depending on ARM state */
489
490 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
491 {
492 arm11->reg_values[ARM11_RC_PC] -= 0;
493 }
494 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
495 {
496 arm11->reg_values[ARM11_RC_PC] -= 4;
497 }
498 else /* ARM state */
499 {
500 arm11->reg_values[ARM11_RC_PC] -= 8;
501 }
502
503 if (arm11->simulate_reset_on_next_halt)
504 {
505 arm11->simulate_reset_on_next_halt = false;
506
507 LOG_DEBUG("Reset c1 Control Register");
508
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
510
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
513
514 }
515
516 arm11_run_instr_data_finish(arm11);
517
518 arm11_dump_reg_changes(arm11);
519
520 return ERROR_OK;
521 }
522
523 void arm11_dump_reg_changes(arm11_common_t * arm11)
524 {
525
526 if (!(debug_level >= LOG_LVL_DEBUG))
527 {
528 return;
529 }
530
531 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
532 {
533 if (!arm11->reg_list[i].valid)
534 {
535 if (arm11->reg_history[i].valid)
536 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
537 }
538 else
539 {
540 if (arm11->reg_history[i].valid)
541 {
542 if (arm11->reg_history[i].value != arm11->reg_values[i])
543 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
544 }
545 else
546 {
547 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
548 }
549 }
550 }
551 }
552
553 /** Restore processor state
554 *
555 * This is called in preparation for the RESTART function.
556 *
557 */
558 int arm11_leave_debug_state(arm11_common_t * arm11)
559 {
560 FNC_INFO;
561
562 arm11_run_instr_data_prepare(arm11);
563
564 /** \todo TODO: handle other mode registers */
565
566 /* restore R1 - R14 */
567
568 for (size_t i = 1; i < 15; i++)
569 {
570 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
571 continue;
572
573 /* MRC p14,0,r?,c0,c5,0 */
574 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
575
576 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
577 }
578
579 arm11_run_instr_data_finish(arm11);
580
581 /* spec says clear wDTR and rDTR; we assume they are clear as
582 otherwise our programming would be sloppy */
583 {
584 uint32_t DSCR;
585
586 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
587
588 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
589 {
590 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
591 }
592 }
593
594 arm11_run_instr_data_prepare(arm11);
595
596 /* restore original wDTR */
597
598 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
599 {
600 /* MCR p14,0,R0,c0,c5,0 */
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
602 }
603
604 /* restore CPSR */
605
606 /* MSR CPSR,R0*/
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
608
609 /* restore PC */
610
611 /* MOV PC,R0 */
612 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
613
614 /* restore R0 */
615
616 /* MRC p14,0,r0,c0,c5,0 */
617 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
618
619 arm11_run_instr_data_finish(arm11);
620
621 /* restore DSCR */
622
623 arm11_write_DSCR(arm11, R(DSCR));
624
625 /* restore rDTR */
626
627 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
628 {
629 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
630
631 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
632
633 scan_field_t chain5_fields[3];
634
635 uint8_t Ready = 0; /* ignored */
636 uint8_t Valid = 0; /* ignored */
637
638 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
639 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
640 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
641
642 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
643 }
644
645 arm11_record_register_history(arm11);
646
647 return ERROR_OK;
648 }
649
650 void arm11_record_register_history(arm11_common_t * arm11)
651 {
652 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
653 {
654 arm11->reg_history[i].value = arm11->reg_values[i];
655 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
656
657 arm11->reg_list[i].valid = 0;
658 arm11->reg_list[i].dirty = 0;
659 }
660 }
661
662
663 /* poll current target status */
664 int arm11_poll(struct target_s *target)
665 {
666 FNC_INFO;
667
668 arm11_common_t * arm11 = target->arch_info;
669
670 if (arm11->trst_active)
671 return ERROR_OK;
672
673 uint32_t dscr;
674
675 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
676
677 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
678
679 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
680
681 if (dscr & ARM11_DSCR_CORE_HALTED)
682 {
683 if (target->state != TARGET_HALTED)
684 {
685 enum target_state old_state = target->state;
686
687 LOG_DEBUG("enter TARGET_HALTED");
688 target->state = TARGET_HALTED;
689 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
690 arm11_on_enter_debug_state(arm11);
691
692 target_call_event_callbacks(target,
693 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
694 }
695 }
696 else
697 {
698 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
699 {
700 LOG_DEBUG("enter TARGET_RUNNING");
701 target->state = TARGET_RUNNING;
702 target->debug_reason = DBG_REASON_NOTHALTED;
703 }
704 }
705
706 return ERROR_OK;
707 }
708 /* architecture specific status reply */
709 int arm11_arch_state(struct target_s *target)
710 {
711 arm11_common_t * arm11 = target->arch_info;
712
713 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
714 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
715 R(CPSR),
716 R(PC));
717
718 return ERROR_OK;
719 }
720
721 /* target request support */
722 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
723 {
724 FNC_INFO_NOTIMPLEMENTED;
725
726 return ERROR_OK;
727 }
728
729 /* target execution control */
730 int arm11_halt(struct target_s *target)
731 {
732 FNC_INFO;
733
734 arm11_common_t * arm11 = target->arch_info;
735
736 LOG_DEBUG("target->state: %s",
737 target_state_name(target));
738
739 if (target->state == TARGET_UNKNOWN)
740 {
741 arm11->simulate_reset_on_next_halt = true;
742 }
743
744 if (target->state == TARGET_HALTED)
745 {
746 LOG_DEBUG("target was already halted");
747 return ERROR_OK;
748 }
749
750 if (arm11->trst_active)
751 {
752 arm11->halt_requested = true;
753 return ERROR_OK;
754 }
755
756 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
757
758 CHECK_RETVAL(jtag_execute_queue());
759
760 uint32_t dscr;
761
762 while (1)
763 {
764 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
765
766 if (dscr & ARM11_DSCR_CORE_HALTED)
767 break;
768 }
769
770 arm11_on_enter_debug_state(arm11);
771
772 enum target_state old_state = target->state;
773
774 target->state = TARGET_HALTED;
775 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
776
777 CHECK_RETVAL(
778 target_call_event_callbacks(target,
779 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
780
781 return ERROR_OK;
782 }
783
784 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
785 {
786 FNC_INFO;
787
788 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
789 // current, address, handle_breakpoints, debug_execution);
790
791 arm11_common_t * arm11 = target->arch_info;
792
793 LOG_DEBUG("target->state: %s",
794 target_state_name(target));
795
796
797 if (target->state != TARGET_HALTED)
798 {
799 LOG_ERROR("Target not halted");
800 return ERROR_TARGET_NOT_HALTED;
801 }
802
803 if (!current)
804 R(PC) = address;
805
806 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
807
808 /* clear breakpoints/watchpoints and VCR*/
809 arm11_sc7_clear_vbw(arm11);
810
811 /* Set up breakpoints */
812 if (!debug_execution)
813 {
814 /* check if one matches PC and step over it if necessary */
815
816 breakpoint_t * bp;
817
818 for (bp = target->breakpoints; bp; bp = bp->next)
819 {
820 if (bp->address == R(PC))
821 {
822 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
823 arm11_step(target, 1, 0, 0);
824 break;
825 }
826 }
827
828 /* set all breakpoints */
829
830 size_t brp_num = 0;
831
832 for (bp = target->breakpoints; bp; bp = bp->next)
833 {
834 arm11_sc7_action_t brp[2];
835
836 brp[0].write = 1;
837 brp[0].address = ARM11_SC7_BVR0 + brp_num;
838 brp[0].value = bp->address;
839 brp[1].write = 1;
840 brp[1].address = ARM11_SC7_BCR0 + brp_num;
841 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
842
843 arm11_sc7_run(arm11, brp, asizeof(brp));
844
845 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
846
847 brp_num++;
848 }
849
850 arm11_sc7_set_vcr(arm11, arm11_vcr);
851 }
852
853 arm11_leave_debug_state(arm11);
854
855 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
856
857 CHECK_RETVAL(jtag_execute_queue());
858
859 while (1)
860 {
861 uint32_t dscr;
862
863 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
864
865 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
866
867 if (dscr & ARM11_DSCR_CORE_RESTARTED)
868 break;
869 }
870
871 if (!debug_execution)
872 {
873 target->state = TARGET_RUNNING;
874 target->debug_reason = DBG_REASON_NOTHALTED;
875
876 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
877 }
878 else
879 {
880 target->state = TARGET_DEBUG_RUNNING;
881 target->debug_reason = DBG_REASON_NOTHALTED;
882
883 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
884 }
885
886 return ERROR_OK;
887 }
888
889
890 static int armv4_5_to_arm11(int reg)
891 {
892 if (reg < 16)
893 return reg;
894 switch (reg)
895 {
896 case ARMV4_5_CPSR:
897 return ARM11_RC_CPSR;
898 case 16:
899 /* FIX!!! handle thumb better! */
900 return ARM11_RC_CPSR;
901 default:
902 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
903 exit(-1);
904 }
905 }
906
907
908 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
909 {
910 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
911
912 reg=armv4_5_to_arm11(reg);
913
914 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
915 }
916
917 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
918 {
919 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
920
921 reg=armv4_5_to_arm11(reg);
922
923 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
924 }
925
926 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
927 {
928 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
929
930 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
931 }
932
933 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
934 {
935 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
936
937 /* FIX!!!! we should implement thumb for arm11 */
938 return ARMV4_5_STATE_ARM;
939 }
940
941 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
942 {
943 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
944
945 /* FIX!!!! we should implement thumb for arm11 */
946 LOG_ERROR("Not implemetned!");
947 }
948
949
950 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
951 {
952 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
953
954 /* FIX!!!! we should implement something that returns the current mode here!!! */
955 return ARMV4_5_MODE_USR;
956 }
957
958 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
959 {
960 struct arm_sim_interface sim;
961
962 sim.user_data=target->arch_info;
963 sim.get_reg=&arm11_sim_get_reg;
964 sim.set_reg=&arm11_sim_set_reg;
965 sim.get_reg_mode=&arm11_sim_get_reg;
966 sim.set_reg_mode=&arm11_sim_set_reg;
967 sim.get_cpsr=&arm11_sim_get_cpsr;
968 sim.get_mode=&arm11_sim_get_mode;
969 sim.get_state=&arm11_sim_get_state;
970 sim.set_state=&arm11_sim_set_state;
971
972 return arm_simulate_step_core(target, dry_run_pc, &sim);
973
974 }
975
976 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
977 {
978 FNC_INFO;
979 int retval;
980
981 LOG_DEBUG("target->state: %s",
982 target_state_name(target));
983
984 if (target->state != TARGET_HALTED)
985 {
986 LOG_WARNING("target was not halted");
987 return ERROR_TARGET_NOT_HALTED;
988 }
989
990 arm11_common_t * arm11 = target->arch_info;
991
992 if (!current)
993 R(PC) = address;
994
995 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
996
997 uint32_t next_pc;
998 retval = arm11_simulate_step(target, &next_pc);
999 if (retval != ERROR_OK)
1000 return retval;
1001
1002
1003 /** \todo TODO: Thumb not supported here */
1004
1005 uint32_t next_instruction;
1006
1007 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1008
1009 /* skip over BKPT */
1010 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1011 {
1012 R(PC) += 4;
1013 arm11->reg_list[ARM11_RC_PC].valid = 1;
1014 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1015 LOG_DEBUG("Skipping BKPT");
1016 }
1017 /* skip over Wait for interrupt / Standby */
1018 /* mcr 15, 0, r?, cr7, cr0, {4} */
1019 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1020 {
1021 R(PC) += 4;
1022 arm11->reg_list[ARM11_RC_PC].valid = 1;
1023 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1024 LOG_DEBUG("Skipping WFI");
1025 }
1026 /* ignore B to self */
1027 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1028 {
1029 LOG_DEBUG("Not stepping jump to self");
1030 }
1031 else
1032 {
1033 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1034 * with this. */
1035
1036 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1037 * the VCR might be something worth looking into. */
1038
1039
1040 /* Set up breakpoint for stepping */
1041
1042 arm11_sc7_action_t brp[2];
1043
1044 brp[0].write = 1;
1045 brp[0].address = ARM11_SC7_BVR0;
1046 brp[0].value = R(PC);
1047 brp[1].write = 1;
1048 brp[1].address = ARM11_SC7_BCR0;
1049 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1050
1051 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1052
1053 /* resume */
1054
1055
1056 if (arm11_config_step_irq_enable)
1057 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1058 else
1059 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1060
1061
1062 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1063
1064 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1065
1066 CHECK_RETVAL(jtag_execute_queue());
1067
1068 /** \todo TODO: add a timeout */
1069
1070 /* wait for halt */
1071
1072 while (1)
1073 {
1074 uint32_t dscr;
1075
1076 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1077
1078 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1079
1080 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1081 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1082 break;
1083 }
1084
1085 /* clear breakpoint */
1086 arm11_sc7_clear_vbw(arm11);
1087
1088 /* save state */
1089 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1090
1091 /* restore default state */
1092 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1093
1094 }
1095
1096 // target->state = TARGET_HALTED;
1097 target->debug_reason = DBG_REASON_SINGLESTEP;
1098
1099 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1100
1101 if (R(PC) != next_pc)
1102 {
1103 LOG_WARNING("next pc != simulated address %08" PRIx32 "!=%08" PRIx32, R(PC), next_pc);
1104 }
1105
1106 return ERROR_OK;
1107 }
1108
1109 /* target reset control */
1110 int arm11_assert_reset(struct target_s *target)
1111 {
1112 FNC_INFO;
1113
1114 #if 0
1115 /* assert reset lines */
1116 /* resets only the DBGTAP, not the ARM */
1117
1118 jtag_add_reset(1, 0);
1119 jtag_add_sleep(5000);
1120
1121 arm11_common_t * arm11 = target->arch_info;
1122 arm11->trst_active = true;
1123 #endif
1124
1125 if (target->reset_halt)
1126 {
1127 CHECK_RETVAL(target_halt(target));
1128 }
1129
1130 return ERROR_OK;
1131 }
1132
1133 int arm11_deassert_reset(struct target_s *target)
1134 {
1135 FNC_INFO;
1136
1137 #if 0
1138 LOG_DEBUG("target->state: %s",
1139 target_state_name(target));
1140
1141
1142 /* deassert reset lines */
1143 jtag_add_reset(0, 0);
1144
1145 arm11_common_t * arm11 = target->arch_info;
1146 arm11->trst_active = false;
1147
1148 if (arm11->halt_requested)
1149 return arm11_halt(target);
1150 #endif
1151
1152 return ERROR_OK;
1153 }
1154
1155 int arm11_soft_reset_halt(struct target_s *target)
1156 {
1157 FNC_INFO_NOTIMPLEMENTED;
1158
1159 return ERROR_OK;
1160 }
1161
1162 /* target register access for gdb */
1163 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1164 {
1165 FNC_INFO;
1166
1167 arm11_common_t * arm11 = target->arch_info;
1168
1169 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1170 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1171
1172 for (size_t i = 16; i < 24; i++)
1173 {
1174 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1175 }
1176
1177 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1178
1179 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1180 {
1181 if (arm11_reg_defs[i].gdb_num == -1)
1182 continue;
1183
1184 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1185 }
1186
1187 return ERROR_OK;
1188 }
1189
1190 /* target memory access
1191 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1192 * count: number of items of <size>
1193 */
1194 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1195 {
1196 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1197
1198 FNC_INFO;
1199
1200 if (target->state != TARGET_HALTED)
1201 {
1202 LOG_WARNING("target was not halted");
1203 return ERROR_TARGET_NOT_HALTED;
1204 }
1205
1206 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1207
1208 arm11_common_t * arm11 = target->arch_info;
1209
1210 arm11_run_instr_data_prepare(arm11);
1211
1212 /* MRC p14,0,r0,c0,c5,0 */
1213 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1214
1215 switch (size)
1216 {
1217 case 1:
1218 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1219 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1220
1221 for (size_t i = 0; i < count; i++)
1222 {
1223 /* ldrb r1, [r0], #1 */
1224 /* ldrb r1, [r0] */
1225 arm11_run_instr_no_data1(arm11,
1226 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1227
1228 uint32_t res;
1229 /* MCR p14,0,R1,c0,c5,0 */
1230 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1231
1232 *buffer++ = res;
1233 }
1234
1235 break;
1236
1237 case 2:
1238 {
1239 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1240
1241 for (size_t i = 0; i < count; i++)
1242 {
1243 /* ldrh r1, [r0], #2 */
1244 arm11_run_instr_no_data1(arm11,
1245 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1246
1247 uint32_t res;
1248
1249 /* MCR p14,0,R1,c0,c5,0 */
1250 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1251
1252 uint16_t svalue = res;
1253 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1254 }
1255
1256 break;
1257 }
1258
1259 case 4:
1260 {
1261 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1262 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1263 uint32_t *words = (uint32_t *)buffer;
1264
1265 /* LDC p14,c5,[R0],#4 */
1266 /* LDC p14,c5,[R0] */
1267 arm11_run_instr_data_from_core(arm11, instr, words, count);
1268 break;
1269 }
1270 }
1271
1272 arm11_run_instr_data_finish(arm11);
1273
1274 return ERROR_OK;
1275 }
1276
1277 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1278 {
1279 FNC_INFO;
1280
1281 if (target->state != TARGET_HALTED)
1282 {
1283 LOG_WARNING("target was not halted");
1284 return ERROR_TARGET_NOT_HALTED;
1285 }
1286
1287 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1288
1289 arm11_common_t * arm11 = target->arch_info;
1290
1291 arm11_run_instr_data_prepare(arm11);
1292
1293 /* MRC p14,0,r0,c0,c5,0 */
1294 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1295
1296 switch (size)
1297 {
1298 case 1:
1299 {
1300 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1301
1302 for (size_t i = 0; i < count; i++)
1303 {
1304 /* MRC p14,0,r1,c0,c5,0 */
1305 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1306
1307 /* strb r1, [r0], #1 */
1308 /* strb r1, [r0] */
1309 arm11_run_instr_no_data1(arm11,
1310 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1311 }
1312
1313 break;
1314 }
1315
1316 case 2:
1317 {
1318 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1319
1320 for (size_t i = 0; i < count; i++)
1321 {
1322 uint16_t value;
1323 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1324
1325 /* MRC p14,0,r1,c0,c5,0 */
1326 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1327
1328 /* strh r1, [r0], #2 */
1329 /* strh r1, [r0] */
1330 arm11_run_instr_no_data1(arm11,
1331 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1332 }
1333
1334 break;
1335 }
1336
1337 case 4: {
1338 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1339
1340 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1341 uint32_t *words = (uint32_t*)buffer;
1342
1343 if (!arm11_config_memwrite_burst)
1344 {
1345 /* STC p14,c5,[R0],#4 */
1346 /* STC p14,c5,[R0]*/
1347 arm11_run_instr_data_to_core(arm11, instr, words, count);
1348 }
1349 else
1350 {
1351 /* STC p14,c5,[R0],#4 */
1352 /* STC p14,c5,[R0]*/
1353 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1354 }
1355
1356 break;
1357 }
1358 }
1359
1360 #if 1
1361 /* r0 verification */
1362 if (!arm11_config_memrw_no_increment)
1363 {
1364 uint32_t r0;
1365
1366 /* MCR p14,0,R0,c0,c5,0 */
1367 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1368
1369 if (address + size * count != r0)
1370 {
1371 LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
1372
1373 if (arm11_config_memwrite_burst)
1374 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1375
1376 if (arm11_config_memwrite_error_fatal)
1377 return ERROR_FAIL;
1378 }
1379 }
1380 #endif
1381
1382 arm11_run_instr_data_finish(arm11);
1383
1384 return ERROR_OK;
1385 }
1386
1387
1388 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1389 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1390 {
1391 FNC_INFO;
1392
1393 if (target->state != TARGET_HALTED)
1394 {
1395 LOG_WARNING("target was not halted");
1396 return ERROR_TARGET_NOT_HALTED;
1397 }
1398
1399 return arm11_write_memory(target, address, 4, count, buffer);
1400 }
1401
1402 /* here we have nothing target specific to contribute, so we fail and then the
1403 * fallback code will read data from the target and calculate the CRC on the
1404 * host.
1405 */
1406 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1407 {
1408 return ERROR_FAIL;
1409 }
1410
1411 /* target break-/watchpoint control
1412 * rw: 0 = write, 1 = read, 2 = access
1413 */
1414 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1415 {
1416 FNC_INFO;
1417
1418 arm11_common_t * arm11 = target->arch_info;
1419
1420 #if 0
1421 if (breakpoint->type == BKPT_SOFT)
1422 {
1423 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1425 }
1426 #endif
1427
1428 if (!arm11->free_brps)
1429 {
1430 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1431 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1432 }
1433
1434 if (breakpoint->length != 4)
1435 {
1436 LOG_DEBUG("only breakpoints of four bytes length supported");
1437 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1438 }
1439
1440 arm11->free_brps--;
1441
1442 return ERROR_OK;
1443 }
1444
1445 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1446 {
1447 FNC_INFO;
1448
1449 arm11_common_t * arm11 = target->arch_info;
1450
1451 arm11->free_brps++;
1452
1453 return ERROR_OK;
1454 }
1455
1456 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1457 {
1458 FNC_INFO_NOTIMPLEMENTED;
1459
1460 return ERROR_OK;
1461 }
1462
1463 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1464 {
1465 FNC_INFO_NOTIMPLEMENTED;
1466
1467 return ERROR_OK;
1468 }
1469
1470 // HACKHACKHACK - FIXME mode/state
1471 /* target algorithm support */
1472 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1473 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1474 int timeout_ms, void *arch_info)
1475 {
1476 arm11_common_t *arm11 = target->arch_info;
1477 // enum armv4_5_state core_state = arm11->core_state;
1478 // enum armv4_5_mode core_mode = arm11->core_mode;
1479 uint32_t context[16];
1480 uint32_t cpsr;
1481 int exit_breakpoint_size = 0;
1482 int retval = ERROR_OK;
1483 LOG_DEBUG("Running algorithm");
1484
1485
1486 if (target->state != TARGET_HALTED)
1487 {
1488 LOG_WARNING("target not halted");
1489 return ERROR_TARGET_NOT_HALTED;
1490 }
1491
1492 // FIXME
1493 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1494 // return ERROR_FAIL;
1495
1496 // Save regs
1497 for (size_t i = 0; i < 16; i++)
1498 {
1499 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1500 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1501 }
1502
1503 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1504 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1505
1506 for (int i = 0; i < num_mem_params; i++)
1507 {
1508 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1509 }
1510
1511 // Set register parameters
1512 for (int i = 0; i < num_reg_params; i++)
1513 {
1514 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1515 if (!reg)
1516 {
1517 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1518 exit(-1);
1519 }
1520
1521 if (reg->size != reg_params[i].size)
1522 {
1523 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1524 exit(-1);
1525 }
1526 arm11_set_reg(reg,reg_params[i].value);
1527 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1528 }
1529
1530 exit_breakpoint_size = 4;
1531
1532 /* arm11->core_state = arm11_algorithm_info->core_state;
1533 if (arm11->core_state == ARMV4_5_STATE_ARM)
1534 exit_breakpoint_size = 4;
1535 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1536 exit_breakpoint_size = 2;
1537 else
1538 {
1539 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1540 exit(-1);
1541 }
1542 */
1543
1544
1545 /* arm11 at this point only supports ARM not THUMB mode
1546 however if this test needs to be reactivated the current state can be read back
1547 from CPSR */
1548 #if 0
1549 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1550 {
1551 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1552 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1553 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1554 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1555 }
1556 #endif
1557
1558 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1559 {
1560 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1561 retval = ERROR_TARGET_FAILURE;
1562 goto restore;
1563 }
1564
1565 // no debug, otherwise breakpoint is not set
1566 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1567
1568 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1569
1570 if (target->state != TARGET_HALTED)
1571 {
1572 CHECK_RETVAL(target_halt(target));
1573
1574 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1575
1576 retval = ERROR_TARGET_TIMEOUT;
1577
1578 goto del_breakpoint;
1579 }
1580
1581 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1582 {
1583 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1584 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1585 retval = ERROR_TARGET_TIMEOUT;
1586 goto del_breakpoint;
1587 }
1588
1589 for (int i = 0; i < num_mem_params; i++)
1590 {
1591 if (mem_params[i].direction != PARAM_OUT)
1592 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1593 }
1594
1595 for (int i = 0; i < num_reg_params; i++)
1596 {
1597 if (reg_params[i].direction != PARAM_OUT)
1598 {
1599 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1600 if (!reg)
1601 {
1602 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1603 exit(-1);
1604 }
1605
1606 if (reg->size != reg_params[i].size)
1607 {
1608 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1609 exit(-1);
1610 }
1611
1612 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1613 }
1614 }
1615
1616 del_breakpoint:
1617 breakpoint_remove(target, exit_point);
1618
1619 restore:
1620 // Restore context
1621 for (size_t i = 0; i < 16; i++)
1622 {
1623 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1624 arm11->reg_list[i].name, context[i]);
1625 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1626 }
1627 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1628 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1629
1630 // arm11->core_state = core_state;
1631 // arm11->core_mode = core_mode;
1632
1633 return retval;
1634 }
1635
1636 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1637 {
1638 FNC_INFO;
1639
1640 NEW(arm11_common_t, arm11, 1);
1641
1642 arm11->target = target;
1643
1644 if (target->tap == NULL)
1645 return ERROR_FAIL;
1646
1647 if (target->tap->ir_length != 5)
1648 {
1649 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1650 return ERROR_COMMAND_SYNTAX_ERROR;
1651 }
1652
1653 target->arch_info = arm11;
1654
1655 return ERROR_OK;
1656 }
1657
1658 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1659 {
1660 /* Initialize anything we can set up without talking to the target */
1661 return arm11_build_reg_cache(target);
1662 }
1663
1664 /* talk to the target and set things up */
1665 int arm11_examine(struct target_s *target)
1666 {
1667 FNC_INFO;
1668
1669 arm11_common_t * arm11 = target->arch_info;
1670
1671 /* check IDCODE */
1672
1673 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1674
1675 scan_field_t idcode_field;
1676
1677 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1678
1679 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1680
1681 /* check DIDR */
1682
1683 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1684
1685 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1686
1687 scan_field_t chain0_fields[2];
1688
1689 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1690 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1691
1692 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1693
1694 CHECK_RETVAL(jtag_execute_queue());
1695
1696 switch (arm11->device_id & 0x0FFFF000)
1697 {
1698 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1699 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1700 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1701 default:
1702 {
1703 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1704 return ERROR_FAIL;
1705 }
1706 }
1707
1708 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1709
1710 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1711 arm11->debug_version != ARM11_DEBUG_V61)
1712 {
1713 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1714 return ERROR_FAIL;
1715 }
1716
1717 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1718 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1719
1720 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1721 arm11->free_brps = arm11->brp;
1722 arm11->free_wrps = arm11->wrp;
1723
1724 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1725 arm11->device_id,
1726 (int)(arm11->implementor),
1727 arm11->didr);
1728
1729 /* as a side-effect this reads DSCR and thus
1730 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1731 * as suggested by the spec.
1732 */
1733
1734 arm11_check_init(arm11, NULL);
1735
1736 target_set_examined(target);
1737
1738 return ERROR_OK;
1739 }
1740
1741 int arm11_quit(void)
1742 {
1743 FNC_INFO_NOTIMPLEMENTED;
1744
1745 return ERROR_OK;
1746 }
1747
1748 /** Load a register that is marked !valid in the register cache */
1749 int arm11_get_reg(reg_t *reg)
1750 {
1751 FNC_INFO;
1752
1753 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1754
1755 if (target->state != TARGET_HALTED)
1756 {
1757 LOG_WARNING("target was not halted");
1758 return ERROR_TARGET_NOT_HALTED;
1759 }
1760
1761 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1762
1763 #if 0
1764 arm11_common_t *arm11 = target->arch_info;
1765 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1766 #endif
1767
1768 return ERROR_OK;
1769 }
1770
1771 /** Change a value in the register cache */
1772 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1773 {
1774 FNC_INFO;
1775
1776 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1777 arm11_common_t *arm11 = target->arch_info;
1778 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1779
1780 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1781 reg->valid = 1;
1782 reg->dirty = 1;
1783
1784 return ERROR_OK;
1785 }
1786
1787 int arm11_build_reg_cache(target_t *target)
1788 {
1789 arm11_common_t *arm11 = target->arch_info;
1790
1791 NEW(reg_cache_t, cache, 1);
1792 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1793 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1794
1795 if (arm11_regs_arch_type == -1)
1796 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1797
1798 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1799 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1800
1801 arm11->reg_list = reg_list;
1802
1803 /* Build the process context cache */
1804 cache->name = "arm11 registers";
1805 cache->next = NULL;
1806 cache->reg_list = reg_list;
1807 cache->num_regs = ARM11_REGCACHE_COUNT;
1808
1809 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1810 (*cache_p) = cache;
1811
1812 arm11->core_cache = cache;
1813 // armv7m->process_context = cache;
1814
1815 size_t i;
1816
1817 /* Not very elegant assertion */
1818 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1819 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1820 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1821 {
1822 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1823 exit(-1);
1824 }
1825
1826 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1827 {
1828 reg_t * r = reg_list + i;
1829 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1830 arm11_reg_state_t * rs = arm11_reg_states + i;
1831
1832 r->name = rd->name;
1833 r->size = 32;
1834 r->value = (uint8_t *)(arm11->reg_values + i);
1835 r->dirty = 0;
1836 r->valid = 0;
1837 r->bitfield_desc = NULL;
1838 r->num_bitfields = 0;
1839 r->arch_type = arm11_regs_arch_type;
1840 r->arch_info = rs;
1841
1842 rs->def_index = i;
1843 rs->target = target;
1844 }
1845
1846 return ERROR_OK;
1847 }
1848
1849 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1850 {
1851 if (argc == 0)
1852 {
1853 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1854 return ERROR_OK;
1855 }
1856
1857 if (argc != 1)
1858 return ERROR_COMMAND_SYNTAX_ERROR;
1859
1860 switch (args[0][0])
1861 {
1862 case '0': /* 0 */
1863 case 'f': /* false */
1864 case 'F':
1865 case 'd': /* disable */
1866 case 'D':
1867 *var = false;
1868 break;
1869
1870 case '1': /* 1 */
1871 case 't': /* true */
1872 case 'T':
1873 case 'e': /* enable */
1874 case 'E':
1875 *var = true;
1876 break;
1877 }
1878
1879 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1880
1881 return ERROR_OK;
1882 }
1883
1884 #define BOOL_WRAPPER(name, print_name) \
1885 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1886 { \
1887 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1888 }
1889
1890 #define RC_TOP(name, descr, more) \
1891 { \
1892 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1893 command_t * top_cmd = new_cmd; \
1894 more \
1895 }
1896
1897 #define RC_FINAL(name, descr, handler) \
1898 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1899
1900 #define RC_FINAL_BOOL(name, descr, var) \
1901 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1902
1903 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1904 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1905 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1906 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1907
1908 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1909 {
1910 if (argc == 1)
1911 {
1912 arm11_vcr = strtoul(args[0], NULL, 0);
1913 }
1914 else if (argc != 0)
1915 {
1916 return ERROR_COMMAND_SYNTAX_ERROR;
1917 }
1918
1919 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1920 return ERROR_OK;
1921 }
1922
1923 const uint32_t arm11_coproc_instruction_limits[] =
1924 {
1925 15, /* coprocessor */
1926 7, /* opcode 1 */
1927 15, /* CRn */
1928 15, /* CRm */
1929 7, /* opcode 2 */
1930 0xFFFFFFFF, /* value */
1931 };
1932
1933 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1934 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1935
1936 arm11_common_t * arm11_find_target(const char * arg)
1937 {
1938 jtag_tap_t * tap;
1939 target_t * t;
1940
1941 tap = jtag_tap_by_string(arg);
1942
1943 if (!tap)
1944 return 0;
1945
1946 for (t = all_targets; t; t = t->next)
1947 {
1948 if (t->tap != tap)
1949 continue;
1950
1951 /* if (t->type == arm11_target) */
1952 if (0 == strcmp(target_get_name(t), "arm11"))
1953 return t->arch_info;
1954 }
1955
1956 return 0;
1957 }
1958
1959 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1960 {
1961 if (argc != (read ? 6 : 7))
1962 {
1963 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1964 return -1;
1965 }
1966
1967 arm11_common_t * arm11 = arm11_find_target(args[0]);
1968
1969 if (!arm11)
1970 {
1971 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1972 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1973
1974 return -1;
1975 }
1976
1977 if (arm11->target->state != TARGET_HALTED)
1978 {
1979 LOG_WARNING("target was not halted");
1980 return ERROR_TARGET_NOT_HALTED;
1981 }
1982
1983 uint32_t values[6];
1984
1985 for (size_t i = 0; i < (read ? 5 : 6); i++)
1986 {
1987 values[i] = strtoul(args[i + 1], NULL, 0);
1988
1989 if (values[i] > arm11_coproc_instruction_limits[i])
1990 {
1991 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
1992 (long)(i + 2),
1993 arm11_coproc_instruction_limits[i],
1994 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1995 return -1;
1996 }
1997 }
1998
1999 uint32_t instr = 0xEE000010 |
2000 (values[0] << 8) |
2001 (values[1] << 21) |
2002 (values[2] << 16) |
2003 (values[3] << 0) |
2004 (values[4] << 5);
2005
2006 if (read)
2007 instr |= 0x00100000;
2008
2009 arm11_run_instr_data_prepare(arm11);
2010
2011 if (read)
2012 {
2013 uint32_t result;
2014 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2015
2016 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2017 (int)(values[0]),
2018 (int)(values[1]),
2019 (int)(values[2]),
2020 (int)(values[3]),
2021 (int)(values[4]), result, result);
2022 }
2023 else
2024 {
2025 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2026
2027 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2028 (int)(values[0]), (int)(values[1]),
2029 values[5],
2030 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2031 }
2032
2033 arm11_run_instr_data_finish(arm11);
2034
2035
2036 return ERROR_OK;
2037 }
2038
2039 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2040 {
2041 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2042 }
2043
2044 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2045 {
2046 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2047 }
2048
2049 int arm11_register_commands(struct command_context_s *cmd_ctx)
2050 {
2051 FNC_INFO;
2052
2053 command_t * top_cmd = NULL;
2054
2055 RC_TOP("arm11", "arm11 specific commands",
2056
2057 RC_TOP("memwrite", "Control memory write transfer mode",
2058
2059 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
2060 memwrite_burst)
2061
2062 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
2063 memwrite_error_fatal)
2064 ) /* memwrite */
2065
2066 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
2067 memrw_no_increment)
2068
2069 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
2070 step_irq_enable)
2071
2072 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
2073 arm11_handle_vcr)
2074
2075 RC_FINAL("mrc", "Read Coprocessor register",
2076 arm11_handle_mrc)
2077
2078 RC_FINAL("mcr", "Write Coprocessor register",
2079 arm11_handle_mcr)
2080 ) /* arm11 */
2081
2082 return ERROR_OK;
2083 }
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