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- added more TARGET_HALTED checks for the read/write_memory handlers
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm11.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35
36 #if 0
37 #define FNC_INFO DEBUG("-")
38 #else
39 #define FNC_INFO
40 #endif
41
42 #if 1
43 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
44 #else
45 #define FNC_INFO_NOTIMPLEMENTED
46 #endif
47
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
49
50
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 u32 arm11_vcr = 0;
54
55
56 #define ARM11_HANDLER(x) \
57 .x = arm11_##x
58
59 target_type_t arm11_target =
60 {
61 .name = "arm11",
62
63 ARM11_HANDLER(poll),
64 ARM11_HANDLER(arch_state),
65
66 ARM11_HANDLER(target_request_data),
67
68 ARM11_HANDLER(halt),
69 ARM11_HANDLER(resume),
70 ARM11_HANDLER(step),
71
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75 ARM11_HANDLER(prepare_reset_halt),
76
77 ARM11_HANDLER(get_gdb_reg_list),
78
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
81
82 ARM11_HANDLER(bulk_write_memory),
83
84 ARM11_HANDLER(checksum_memory),
85
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
90
91 ARM11_HANDLER(run_algorithm),
92
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_command),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(quit),
97 };
98
99 int arm11_regs_arch_type = -1;
100
101
102 enum arm11_regtype
103 {
104 ARM11_REGISTER_CORE,
105 ARM11_REGISTER_CPSR,
106
107 ARM11_REGISTER_FX,
108 ARM11_REGISTER_FPS,
109
110 ARM11_REGISTER_FIQ,
111 ARM11_REGISTER_SVC,
112 ARM11_REGISTER_ABT,
113 ARM11_REGISTER_IRQ,
114 ARM11_REGISTER_UND,
115 ARM11_REGISTER_MON,
116
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
123
124 /* debug regs */
125 ARM11_REGISTER_DSCR,
126 ARM11_REGISTER_WDTR,
127 ARM11_REGISTER_RDTR,
128 };
129
130
131 typedef struct arm11_reg_defs_s
132 {
133 char * name;
134 u32 num;
135 int gdb_num;
136 enum arm11_regtype type;
137 } arm11_reg_defs_t;
138
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
141 {
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
158
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
169 #endif
170
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
172
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
182
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
186
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
190
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
194
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
198
199 /* ARM1176 only */
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
203 #endif
204
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
209 };
210
211 enum arm11_regcache_ids
212 {
213 ARM11_RC_R0,
214 ARM11_RC_RX = ARM11_RC_R0,
215
216 ARM11_RC_R1,
217 ARM11_RC_R2,
218 ARM11_RC_R3,
219 ARM11_RC_R4,
220 ARM11_RC_R5,
221 ARM11_RC_R6,
222 ARM11_RC_R7,
223 ARM11_RC_R8,
224 ARM11_RC_R9,
225 ARM11_RC_R10,
226 ARM11_RC_R11,
227 ARM11_RC_R12,
228 ARM11_RC_R13,
229 ARM11_RC_SP = ARM11_RC_R13,
230 ARM11_RC_R14,
231 ARM11_RC_LR = ARM11_RC_R14,
232 ARM11_RC_R15,
233 ARM11_RC_PC = ARM11_RC_R15,
234
235 #if ARM11_REGCACHE_FREGS
236 ARM11_RC_F0,
237 ARM11_RC_FX = ARM11_RC_F0,
238 ARM11_RC_F1,
239 ARM11_RC_F2,
240 ARM11_RC_F3,
241 ARM11_RC_F4,
242 ARM11_RC_F5,
243 ARM11_RC_F6,
244 ARM11_RC_F7,
245 ARM11_RC_FPS,
246 #endif
247
248 ARM11_RC_CPSR,
249
250 #if ARM11_REGCACHE_MODEREGS
251 ARM11_RC_R8_FIQ,
252 ARM11_RC_R9_FIQ,
253 ARM11_RC_R10_FIQ,
254 ARM11_RC_R11_FIQ,
255 ARM11_RC_R12_FIQ,
256 ARM11_RC_R13_FIQ,
257 ARM11_RC_R14_FIQ,
258 ARM11_RC_SPSR_FIQ,
259
260 ARM11_RC_R13_SVC,
261 ARM11_RC_R14_SVC,
262 ARM11_RC_SPSR_SVC,
263
264 ARM11_RC_R13_ABT,
265 ARM11_RC_R14_ABT,
266 ARM11_RC_SPSR_ABT,
267
268 ARM11_RC_R13_IRQ,
269 ARM11_RC_R14_IRQ,
270 ARM11_RC_SPSR_IRQ,
271
272 ARM11_RC_R13_UND,
273 ARM11_RC_R14_UND,
274 ARM11_RC_SPSR_UND,
275
276 ARM11_RC_R13_MON,
277 ARM11_RC_R14_MON,
278 ARM11_RC_SPSR_MON,
279 #endif
280
281 ARM11_RC_DSCR,
282 ARM11_RC_WDTR,
283 ARM11_RC_RDTR,
284
285 ARM11_RC_MAX,
286 };
287
288 #define ARM11_GDB_REGISTER_COUNT 26
289
290 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
291
292 reg_t arm11_gdb_dummy_fp_reg =
293 {
294 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
295 };
296
297 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
298
299 reg_t arm11_gdb_dummy_fps_reg =
300 {
301 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
302 };
303
304
305
306 /** Check and if necessary take control of the system
307 *
308 * \param arm11 Target state variable.
309 * \param dscr If the current DSCR content is
310 * available a pointer to a word holding the
311 * DSCR can be passed. Otherwise use NULL.
312 */
313 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
314 {
315 FNC_INFO;
316
317 u32 dscr_local_tmp_copy;
318
319 if (!dscr)
320 {
321 dscr = &dscr_local_tmp_copy;
322 *dscr = arm11_read_DSCR(arm11);
323 }
324
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
326 {
327 DEBUG("Bringing target into debug mode");
328
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
331
332 /* add further reset initialization here */
333
334 arm11->simulate_reset_on_next_halt = true;
335
336 if (*dscr & ARM11_DSCR_CORE_HALTED)
337 {
338 /** \todo TODO: this needs further scrutiny because
339 * arm11_on_enter_debug_state() never gets properly called
340 */
341
342 arm11->target->state = TARGET_HALTED;
343 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
344 }
345 else
346 {
347 arm11->target->state = TARGET_RUNNING;
348 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
349 }
350
351 arm11_sc7_clear_vbw(arm11);
352 }
353 }
354
355
356
357 #define R(x) \
358 (arm11->reg_values[ARM11_RC_##x])
359
360 /** Save processor state.
361 *
362 * This is called when the HALT instruction has succeeded
363 * or on other occasions that stop the processor.
364 *
365 */
366 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
367 {
368 FNC_INFO;
369
370 {size_t i;
371 for(i = 0; i < asizeof(arm11->reg_values); i++)
372 {
373 arm11->reg_list[i].valid = 1;
374 arm11->reg_list[i].dirty = 0;
375 }}
376
377 /* Save DSCR */
378
379 R(DSCR) = arm11_read_DSCR(arm11);
380
381 /* Save wDTR */
382
383 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
384 {
385 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
386
387 arm11_add_IR(arm11, ARM11_INTEST, -1);
388
389 scan_field_t chain5_fields[3];
390
391 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
394
395 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
396 }
397 else
398 {
399 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
400 }
401
402
403 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
404 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
405 ARM1136 seems to require this to issue ITR's as well */
406
407 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
408
409 /* this executes JTAG queue: */
410
411 arm11_write_DSCR(arm11, new_dscr);
412
413
414 /* From the spec:
415 Before executing any instruction in debug state you have to drain the write buffer.
416 This ensures that no imprecise Data Aborts can return at a later point:*/
417
418 /** \todo TODO: Test drain write buffer. */
419
420 #if 0
421 while (1)
422 {
423 /* MRC p14,0,R0,c5,c10,0 */
424 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
425
426 /* mcr 15, 0, r0, cr7, cr10, {4} */
427 arm11_run_instr_no_data1(arm11, 0xee070f9a);
428
429 u32 dscr = arm11_read_DSCR(arm11);
430
431 DEBUG("DRAIN, DSCR %08x", dscr);
432
433 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
434 {
435 arm11_run_instr_no_data1(arm11, 0xe320f000);
436
437 dscr = arm11_read_DSCR(arm11);
438
439 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
440
441 break;
442 }
443 }
444 #endif
445
446
447 arm11_run_instr_data_prepare(arm11);
448
449 /* save r0 - r14 */
450
451
452 /** \todo TODO: handle other mode registers */
453
454 {size_t i;
455 for (i = 0; i < 15; i++)
456 {
457 /* MCR p14,0,R?,c0,c5,0 */
458 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
459 }}
460
461
462 /* save rDTR */
463
464 /* check rDTRfull in DSCR */
465
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
467 {
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
470 }
471 else
472 {
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
474 }
475
476 /* save CPSR */
477
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
480
481 /* save PC */
482
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
485
486 /* adjust PC depending on ARM state */
487
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
489 {
490 arm11->reg_values[ARM11_RC_PC] -= 0;
491 }
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 4;
495 }
496 else /* ARM state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 8;
499 }
500
501 if (arm11->simulate_reset_on_next_halt)
502 {
503 arm11->simulate_reset_on_next_halt = false;
504
505 DEBUG("Reset c1 Control Register");
506
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
508
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
511
512 }
513
514 arm11_run_instr_data_finish(arm11);
515
516 arm11_dump_reg_changes(arm11);
517 }
518
519 void arm11_dump_reg_changes(arm11_common_t * arm11)
520 {
521 {size_t i;
522 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
523 {
524 if (!arm11->reg_list[i].valid)
525 {
526 if (arm11->reg_history[i].valid)
527 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
528 }
529 else
530 {
531 if (arm11->reg_history[i].valid)
532 {
533 if (arm11->reg_history[i].value != arm11->reg_values[i])
534 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
535 }
536 else
537 {
538 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
539 }
540 }
541 }}
542 }
543
544
545 /** Restore processor state
546 *
547 * This is called in preparation for the RESTART function.
548 *
549 */
550 void arm11_leave_debug_state(arm11_common_t * arm11)
551 {
552 FNC_INFO;
553
554 arm11_run_instr_data_prepare(arm11);
555
556 /** \todo TODO: handle other mode registers */
557
558 /* restore R1 - R14 */
559 {size_t i;
560 for (i = 1; i < 15; i++)
561 {
562 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
563 continue;
564
565 /* MRC p14,0,r?,c0,c5,0 */
566 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
567
568 // DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
569 }}
570
571 arm11_run_instr_data_finish(arm11);
572
573
574 /* spec says clear wDTR and rDTR; we assume they are clear as
575 otherwise our programming would be sloppy */
576
577 {
578 u32 DSCR = arm11_read_DSCR(arm11);
579
580 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
581 {
582 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
583 }
584 }
585
586 arm11_run_instr_data_prepare(arm11);
587
588 /* restore original wDTR */
589
590 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
591 {
592 /* MCR p14,0,R0,c0,c5,0 */
593 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
594 }
595
596 /* restore CPSR */
597
598 /* MSR CPSR,R0*/
599 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
600
601
602 /* restore PC */
603
604 /* MOV PC,R0 */
605 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
606
607
608 /* restore R0 */
609
610 /* MRC p14,0,r0,c0,c5,0 */
611 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
612
613 arm11_run_instr_data_finish(arm11);
614
615
616 /* restore DSCR */
617
618 arm11_write_DSCR(arm11, R(DSCR));
619
620
621 /* restore rDTR */
622
623 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
624 {
625 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
626
627 arm11_add_IR(arm11, ARM11_EXTEST, -1);
628
629 scan_field_t chain5_fields[3];
630
631 u8 Ready = 0; /* ignored */
632 u8 Valid = 0; /* ignored */
633
634 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
635 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
636 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
637
638 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
639 }
640
641 arm11_record_register_history(arm11);
642 }
643
644 void arm11_record_register_history(arm11_common_t * arm11)
645 {
646 {size_t i;
647 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
648 {
649 arm11->reg_history[i].value = arm11->reg_values[i];
650 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
651
652 arm11->reg_list[i].valid = 0;
653 arm11->reg_list[i].dirty = 0;
654 }}
655 }
656
657
658 /* poll current target status */
659 int arm11_poll(struct target_s *target)
660 {
661 FNC_INFO;
662
663 arm11_common_t * arm11 = target->arch_info;
664
665 if (arm11->trst_active)
666 return ERROR_OK;
667
668 u32 dscr = arm11_read_DSCR(arm11);
669
670 DEBUG("DSCR %08x", dscr);
671
672 arm11_check_init(arm11, &dscr);
673
674 if (dscr & ARM11_DSCR_CORE_HALTED)
675 {
676 if (target->state != TARGET_HALTED)
677 {
678 enum target_state old_state = target->state;
679
680 DEBUG("enter TARGET_HALTED");
681 target->state = TARGET_HALTED;
682 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
683 arm11_on_enter_debug_state(arm11);
684
685 target_call_event_callbacks(target,
686 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
687 }
688 }
689 else
690 {
691 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
692 {
693 DEBUG("enter TARGET_RUNNING");
694 target->state = TARGET_RUNNING;
695 target->debug_reason = DBG_REASON_NOTHALTED;
696 }
697 }
698
699 return ERROR_OK;
700 }
701 /* architecture specific status reply */
702 int arm11_arch_state(struct target_s *target)
703 {
704 FNC_INFO_NOTIMPLEMENTED;
705
706 return ERROR_OK;
707 }
708
709
710 /* target request support */
711 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
712 {
713 FNC_INFO_NOTIMPLEMENTED;
714
715 return ERROR_OK;
716 }
717
718
719
720 /* target execution control */
721 int arm11_halt(struct target_s *target)
722 {
723 FNC_INFO;
724
725 arm11_common_t * arm11 = target->arch_info;
726
727 DEBUG("target->state: %s", target_state_strings[target->state]);
728
729 if (target->state == TARGET_UNKNOWN)
730 {
731 arm11->simulate_reset_on_next_halt = true;
732 }
733
734 if (target->state == TARGET_HALTED)
735 {
736 WARNING("target was already halted");
737 return ERROR_OK;
738 }
739
740 if (arm11->trst_active)
741 {
742 arm11->halt_requested = true;
743 return ERROR_OK;
744 }
745
746 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
747
748 jtag_execute_queue();
749
750 u32 dscr;
751
752 while (1)
753 {
754 dscr = arm11_read_DSCR(arm11);
755
756 if (dscr & ARM11_DSCR_CORE_HALTED)
757 break;
758 }
759
760 arm11_on_enter_debug_state(arm11);
761
762 enum target_state old_state = target->state;
763
764 target->state = TARGET_HALTED;
765 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
766
767 target_call_event_callbacks(target,
768 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
769
770 return ERROR_OK;
771 }
772
773
774 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
775 {
776 FNC_INFO;
777
778 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
779 // current, address, handle_breakpoints, debug_execution);
780
781 arm11_common_t * arm11 = target->arch_info;
782
783 DEBUG("target->state: %s", target_state_strings[target->state]);
784
785 if (target->state != TARGET_HALTED)
786 {
787 WARNING("target was not halted");
788 return ERROR_TARGET_NOT_HALTED;
789 }
790
791 if (!current)
792 R(PC) = address;
793
794 INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
795
796 /* clear breakpoints/watchpoints and VCR*/
797 arm11_sc7_clear_vbw(arm11);
798
799 /* Set up breakpoints */
800 if (!debug_execution)
801 {
802 /* check if one matches PC and step over it if necessary */
803
804 breakpoint_t * bp;
805
806 for (bp = target->breakpoints; bp; bp = bp->next)
807 {
808 if (bp->address == R(PC))
809 {
810 DEBUG("must step over %08x", bp->address);
811 arm11_step(target, 1, 0, 0);
812 break;
813 }
814 }
815
816 /* set all breakpoints */
817
818 size_t brp_num = 0;
819
820 for (bp = target->breakpoints; bp; bp = bp->next)
821 {
822 arm11_sc7_action_t brp[2];
823
824 brp[0].write = 1;
825 brp[0].address = ARM11_SC7_BVR0 + brp_num;
826 brp[0].value = bp->address;
827 brp[1].write = 1;
828 brp[1].address = ARM11_SC7_BCR0 + brp_num;
829 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
830
831 arm11_sc7_run(arm11, brp, asizeof(brp));
832
833 DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
834
835 brp_num++;
836 }
837
838 arm11_sc7_set_vcr(arm11, arm11_vcr);
839 }
840
841
842 arm11_leave_debug_state(arm11);
843
844 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
845
846 jtag_execute_queue();
847
848 while (1)
849 {
850 u32 dscr = arm11_read_DSCR(arm11);
851
852 DEBUG("DSCR %08x", dscr);
853
854 if (dscr & ARM11_DSCR_CORE_RESTARTED)
855 break;
856 }
857
858 if (!debug_execution)
859 {
860 target->state = TARGET_RUNNING;
861 target->debug_reason = DBG_REASON_NOTHALTED;
862 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
863 }
864 else
865 {
866 target->state = TARGET_DEBUG_RUNNING;
867 target->debug_reason = DBG_REASON_NOTHALTED;
868 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
869 }
870
871 return ERROR_OK;
872 }
873
874 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
875 {
876 FNC_INFO;
877
878 DEBUG("target->state: %s", target_state_strings[target->state]);
879
880 if (target->state != TARGET_HALTED)
881 {
882 WARNING("target was not halted");
883 return ERROR_TARGET_NOT_HALTED;
884 }
885
886 arm11_common_t * arm11 = target->arch_info;
887
888 if (!current)
889 R(PC) = address;
890
891 INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
892
893 /** \todo TODO: Thumb not supported here */
894
895 u32 next_instruction;
896
897 arm11_read_memory_word(arm11, R(PC), &next_instruction);
898
899 /* skip over BKPT */
900 if ((next_instruction & 0xFFF00070) == 0xe1200070)
901 {
902 R(PC) += 4;
903 arm11->reg_list[ARM11_RC_PC].valid = 1;
904 arm11->reg_list[ARM11_RC_PC].dirty = 0;
905 INFO("Skipping BKPT");
906 }
907 /* skip over Wait for interrupt / Standby */
908 /* mcr 15, 0, r?, cr7, cr0, {4} */
909 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
910 {
911 R(PC) += 4;
912 arm11->reg_list[ARM11_RC_PC].valid = 1;
913 arm11->reg_list[ARM11_RC_PC].dirty = 0;
914 INFO("Skipping WFI");
915 }
916 /* ignore B to self */
917 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
918 {
919 INFO("Not stepping jump to self");
920 }
921 else
922 {
923 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
924 * with this. */
925
926 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
927 * the VCR might be something worth looking into. */
928
929
930 /* Set up breakpoint for stepping */
931
932 arm11_sc7_action_t brp[2];
933
934 brp[0].write = 1;
935 brp[0].address = ARM11_SC7_BVR0;
936 brp[0].value = R(PC);
937 brp[1].write = 1;
938 brp[1].address = ARM11_SC7_BCR0;
939 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
940
941 arm11_sc7_run(arm11, brp, asizeof(brp));
942
943 /* resume */
944
945 arm11_leave_debug_state(arm11);
946
947 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
948
949 jtag_execute_queue();
950
951 /** \todo TODO: add a timeout */
952
953 /* wait for halt */
954
955 while (1)
956 {
957 u32 dscr = arm11_read_DSCR(arm11);
958
959 DEBUG("DSCR %08x", dscr);
960
961 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
962 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
963 break;
964 }
965
966 /* clear breakpoint */
967 arm11_sc7_clear_vbw(arm11);
968
969 /* save state */
970 arm11_on_enter_debug_state(arm11);
971 }
972
973 // target->state = TARGET_HALTED;
974 target->debug_reason = DBG_REASON_SINGLESTEP;
975
976 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
977
978 return ERROR_OK;
979 }
980
981
982 /* target reset control */
983 int arm11_assert_reset(struct target_s *target)
984 {
985 FNC_INFO;
986
987 #if 0
988 /* assert reset lines */
989 /* resets only the DBGTAP, not the ARM */
990
991 jtag_add_reset(1, 0);
992 jtag_add_sleep(5000);
993
994 arm11_common_t * arm11 = target->arch_info;
995 arm11->trst_active = true;
996 #endif
997
998 return ERROR_OK;
999 }
1000
1001 int arm11_deassert_reset(struct target_s *target)
1002 {
1003 FNC_INFO;
1004
1005 #if 0
1006 DEBUG("target->state: %s", target_state_strings[target->state]);
1007
1008 /* deassert reset lines */
1009 jtag_add_reset(0, 0);
1010
1011 arm11_common_t * arm11 = target->arch_info;
1012 arm11->trst_active = false;
1013
1014 if (arm11->halt_requested)
1015 return arm11_halt(target);
1016 #endif
1017
1018 return ERROR_OK;
1019 }
1020
1021 int arm11_soft_reset_halt(struct target_s *target)
1022 {
1023 FNC_INFO_NOTIMPLEMENTED;
1024
1025 return ERROR_OK;
1026 }
1027
1028 int arm11_prepare_reset_halt(struct target_s *target)
1029 {
1030 FNC_INFO_NOTIMPLEMENTED;
1031
1032 return ERROR_OK;
1033 }
1034
1035
1036 /* target register access for gdb */
1037 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1038 {
1039 FNC_INFO;
1040
1041 arm11_common_t * arm11 = target->arch_info;
1042
1043 if (target->state != TARGET_HALTED)
1044 {
1045 WARNING("target was not halted");
1046 return ERROR_TARGET_NOT_HALTED;
1047 }
1048
1049 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1050 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1051
1052 {size_t i;
1053 for (i = 16; i < 24; i++)
1054 {
1055 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1056 }}
1057
1058 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1059
1060
1061 {size_t i;
1062 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1063 {
1064 if (arm11_reg_defs[i].gdb_num == -1)
1065 continue;
1066
1067 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1068 }}
1069
1070 return ERROR_OK;
1071 }
1072
1073
1074 /* target memory access
1075 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1076 * count: number of items of <size>
1077 */
1078 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1079 {
1080 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1081
1082 FNC_INFO;
1083
1084 if (target->state != TARGET_HALTED)
1085 {
1086 WARNING("target was not halted");
1087 return ERROR_TARGET_NOT_HALTED;
1088 }
1089
1090 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1091
1092 arm11_common_t * arm11 = target->arch_info;
1093
1094 arm11_run_instr_data_prepare(arm11);
1095
1096 /* MRC p14,0,r0,c0,c5,0 */
1097 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1098
1099 switch (size)
1100 {
1101 case 1:
1102 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1103 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1104
1105 {size_t i;
1106 for (i = 0; i < count; i++)
1107 {
1108 /* ldrb r1, [r0], #1 */
1109 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1110
1111 u32 res;
1112 /* MCR p14,0,R1,c0,c5,0 */
1113 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1114
1115 *buffer++ = res;
1116 }}
1117
1118 break;
1119
1120 case 2:
1121 {
1122 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1123
1124 u16 * buf16 = (u16*)buffer;
1125
1126 {size_t i;
1127 for (i = 0; i < count; i++)
1128 {
1129 /* ldrh r1, [r0], #2 */
1130 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1131
1132 u32 res;
1133
1134 /* MCR p14,0,R1,c0,c5,0 */
1135 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1136
1137 *buf16++ = res;
1138 }}
1139
1140 break;
1141 }
1142
1143 case 4:
1144
1145 /* LDC p14,c5,[R0],#4 */
1146 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1147 break;
1148 }
1149
1150 arm11_run_instr_data_finish(arm11);
1151
1152 return ERROR_OK;
1153 }
1154
1155 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1156 {
1157 FNC_INFO;
1158
1159 if (target->state != TARGET_HALTED)
1160 {
1161 WARNING("target was not halted");
1162 return ERROR_TARGET_NOT_HALTED;
1163 }
1164
1165 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1166
1167 arm11_common_t * arm11 = target->arch_info;
1168
1169 arm11_run_instr_data_prepare(arm11);
1170
1171 /* MRC p14,0,r0,c0,c5,0 */
1172 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1173
1174 switch (size)
1175 {
1176 case 1:
1177 {
1178 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1179
1180 {size_t i;
1181 for (i = 0; i < count; i++)
1182 {
1183 /* MRC p14,0,r1,c0,c5,0 */
1184 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1185
1186 /* strb r1, [r0], #1 */
1187 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1188 }}
1189
1190 break;
1191 }
1192
1193 case 2:
1194 {
1195 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1196
1197 u16 * buf16 = (u16*)buffer;
1198
1199 {size_t i;
1200 for (i = 0; i < count; i++)
1201 {
1202 /* MRC p14,0,r1,c0,c5,0 */
1203 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1204
1205 /* strh r1, [r0], #2 */
1206 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1207 }}
1208
1209 break;
1210 }
1211
1212 case 4:
1213 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1214
1215 if (!arm11_config_memwrite_burst)
1216 {
1217 /* STC p14,c5,[R0],#4 */
1218 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1219 }
1220 else
1221 {
1222 /* STC p14,c5,[R0],#4 */
1223 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1224 }
1225
1226 break;
1227 }
1228
1229 #if 1
1230 /* r0 verification */
1231 {
1232 u32 r0;
1233
1234 /* MCR p14,0,R0,c0,c5,0 */
1235 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1236
1237 if (address + size * count != r0)
1238 {
1239 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1240
1241 if (arm11_config_memwrite_burst)
1242 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1243
1244 if (arm11_config_memwrite_error_fatal)
1245 exit(-1);
1246 }
1247 }
1248 #endif
1249
1250
1251 arm11_run_instr_data_finish(arm11);
1252
1253
1254
1255
1256 return ERROR_OK;
1257 }
1258
1259
1260 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1261 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1262 {
1263 FNC_INFO;
1264
1265 if (target->state != TARGET_HALTED)
1266 {
1267 WARNING("target was not halted");
1268 return ERROR_TARGET_NOT_HALTED;
1269 }
1270
1271 return arm11_write_memory(target, address, 4, count, buffer);
1272 }
1273
1274
1275 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1276 {
1277 FNC_INFO_NOTIMPLEMENTED;
1278
1279 return ERROR_OK;
1280 }
1281
1282
1283 /* target break-/watchpoint control
1284 * rw: 0 = write, 1 = read, 2 = access
1285 */
1286 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1287 {
1288 FNC_INFO;
1289
1290 arm11_common_t * arm11 = target->arch_info;
1291
1292 #if 0
1293 if (breakpoint->type == BKPT_SOFT)
1294 {
1295 INFO("sw breakpoint requested, but software breakpoints not enabled");
1296 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1297 }
1298 #endif
1299
1300 if (!arm11->free_brps)
1301 {
1302 INFO("no breakpoint unit available for hardware breakpoint");
1303 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1304 }
1305
1306 if (breakpoint->length != 4)
1307 {
1308 INFO("only breakpoints of four bytes length supported");
1309 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1310 }
1311
1312 arm11->free_brps--;
1313
1314 return ERROR_OK;
1315 }
1316
1317 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1318 {
1319 FNC_INFO;
1320
1321 arm11_common_t * arm11 = target->arch_info;
1322
1323 arm11->free_brps++;
1324
1325 return ERROR_OK;
1326 }
1327
1328 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1329 {
1330 FNC_INFO_NOTIMPLEMENTED;
1331
1332 return ERROR_OK;
1333 }
1334
1335 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1336 {
1337 FNC_INFO_NOTIMPLEMENTED;
1338
1339 return ERROR_OK;
1340 }
1341
1342
1343 /* target algorithm support */
1344 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1345 {
1346 FNC_INFO_NOTIMPLEMENTED;
1347
1348 return ERROR_OK;
1349 }
1350
1351 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1352 {
1353 FNC_INFO;
1354
1355 if (argc < 4)
1356 {
1357 ERROR("'target arm11' 4th argument <jtag chain pos>");
1358 exit(-1);
1359 }
1360
1361 int chain_pos = strtoul(args[3], NULL, 0);
1362
1363 NEW(arm11_common_t, arm11, 1);
1364
1365 arm11->target = target;
1366
1367 /* prepare JTAG information for the new target */
1368 arm11->jtag_info.chain_pos = chain_pos;
1369 arm11->jtag_info.scann_size = 5;
1370
1371 arm_jtag_setup_connection(&arm11->jtag_info);
1372
1373 jtag_device_t *device = jtag_get_device(chain_pos);
1374
1375 if (device->ir_length != 5)
1376 {
1377 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1378 exit(-1);
1379 }
1380
1381 target->arch_info = arm11;
1382
1383 return ERROR_OK;
1384 }
1385
1386 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1387 {
1388 FNC_INFO;
1389
1390 arm11_common_t * arm11 = target->arch_info;
1391
1392 /* check IDCODE */
1393
1394 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1395
1396 scan_field_t idcode_field;
1397
1398 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1399
1400 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1401
1402 /* check DIDR */
1403
1404 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1405
1406 arm11_add_IR(arm11, ARM11_INTEST, -1);
1407
1408 scan_field_t chain0_fields[2];
1409
1410 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1411 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1412
1413 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1414
1415 jtag_execute_queue();
1416
1417
1418 switch (arm11->device_id & 0x0FFFF000)
1419 {
1420 case 0x07B36000: INFO("found ARM1136"); break;
1421 case 0x07B56000: INFO("found ARM1156"); break;
1422 case 0x07B76000: INFO("found ARM1176"); break;
1423 default:
1424 {
1425 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1426 exit(-1);
1427 }
1428 }
1429
1430 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1431
1432 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1433 arm11->debug_version != ARM11_DEBUG_V61)
1434 {
1435 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1436 exit(-1);
1437 }
1438
1439
1440 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1441 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1442
1443 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1444 arm11->free_brps = arm11->brp;
1445 arm11->free_wrps = arm11->wrp;
1446
1447 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1448 arm11->device_id,
1449 arm11->implementor,
1450 arm11->didr);
1451
1452 arm11_build_reg_cache(target);
1453
1454
1455 /* as a side-effect this reads DSCR and thus
1456 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1457 * as suggested by the spec.
1458 */
1459
1460 arm11_check_init(arm11, NULL);
1461
1462 return ERROR_OK;
1463 }
1464
1465 int arm11_quit(void)
1466 {
1467 FNC_INFO_NOTIMPLEMENTED;
1468
1469 return ERROR_OK;
1470 }
1471
1472 /** Load a register that is marked !valid in the register cache */
1473 int arm11_get_reg(reg_t *reg)
1474 {
1475 FNC_INFO;
1476
1477 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1478
1479 if (target->state != TARGET_HALTED)
1480 {
1481 WARNING("target was not halted");
1482 return ERROR_TARGET_NOT_HALTED;
1483 }
1484
1485 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1486
1487 #if 0
1488 arm11_common_t *arm11 = target->arch_info;
1489 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1490 #endif
1491
1492 return ERROR_OK;
1493 }
1494
1495 /** Change a value in the register cache */
1496 int arm11_set_reg(reg_t *reg, u8 *buf)
1497 {
1498 FNC_INFO;
1499
1500 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1501 arm11_common_t *arm11 = target->arch_info;
1502 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1503
1504 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1505 reg->valid = 1;
1506 reg->dirty = 1;
1507
1508 return ERROR_OK;
1509 }
1510
1511
1512 void arm11_build_reg_cache(target_t *target)
1513 {
1514 arm11_common_t *arm11 = target->arch_info;
1515
1516 NEW(reg_cache_t, cache, 1);
1517 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1518 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1519
1520 if (arm11_regs_arch_type == -1)
1521 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1522
1523 arm11->reg_list = reg_list;
1524
1525 /* Build the process context cache */
1526 cache->name = "arm11 registers";
1527 cache->next = NULL;
1528 cache->reg_list = reg_list;
1529 cache->num_regs = ARM11_REGCACHE_COUNT;
1530
1531 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1532 (*cache_p) = cache;
1533
1534 // armv7m->core_cache = cache;
1535 // armv7m->process_context = cache;
1536
1537 size_t i;
1538
1539 /* Not very elegant assertion */
1540 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1541 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1542 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1543 {
1544 ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1545 exit(-1);
1546 }
1547
1548 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1549 {
1550 reg_t * r = reg_list + i;
1551 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1552 arm11_reg_state_t * rs = arm11_reg_states + i;
1553
1554 r->name = rd->name;
1555 r->size = 32;
1556 r->value = (u8 *)(arm11->reg_values + i);
1557 r->dirty = 0;
1558 r->valid = 0;
1559 r->bitfield_desc = NULL;
1560 r->num_bitfields = 0;
1561 r->arch_type = arm11_regs_arch_type;
1562 r->arch_info = rs;
1563
1564 rs->def_index = i;
1565 rs->target = target;
1566 }
1567 }
1568
1569
1570
1571 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1572 {
1573 if (argc == 0)
1574 {
1575 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1576 return ERROR_OK;
1577 }
1578
1579 if (argc != 1)
1580 return ERROR_COMMAND_SYNTAX_ERROR;
1581
1582 switch (args[0][0])
1583 {
1584 case '0': /* 0 */
1585 case 'f': /* false */
1586 case 'F':
1587 case 'd': /* disable */
1588 case 'D':
1589 *var = false;
1590 break;
1591
1592 case '1': /* 1 */
1593 case 't': /* true */
1594 case 'T':
1595 case 'e': /* enable */
1596 case 'E':
1597 *var = true;
1598 break;
1599 }
1600
1601 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1602
1603 return ERROR_OK;
1604 }
1605
1606
1607 #define BOOL_WRAPPER(name, print_name) \
1608 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1609 { \
1610 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1611 }
1612
1613 #define RC_TOP(name, descr, more) \
1614 { \
1615 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1616 command_t * top_cmd = new_cmd; \
1617 more \
1618 }
1619
1620 #define RC_FINAL(name, descr, handler) \
1621 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1622
1623 #define RC_FINAL_BOOL(name, descr, var) \
1624 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1625
1626
1627 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1628 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1629
1630
1631 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1632 {
1633 if (argc == 1)
1634 {
1635 arm11_vcr = strtoul(args[0], NULL, 0);
1636 }
1637 else if (argc != 0)
1638 {
1639 return ERROR_COMMAND_SYNTAX_ERROR;
1640 }
1641
1642 INFO("VCR 0x%08X", arm11_vcr);
1643 return ERROR_OK;
1644 }
1645
1646 const u32 arm11_coproc_instruction_limits[] =
1647 {
1648 15, /* coprocessor */
1649 7, /* opcode 1 */
1650 15, /* CRn */
1651 15, /* CRm */
1652 7, /* opcode 2 */
1653 0xFFFFFFFF, /* value */
1654 };
1655
1656 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1657 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1658
1659
1660 arm11_common_t * arm11_find_target(const char * arg)
1661 {
1662 size_t jtag_target = strtoul(arg, NULL, 0);
1663
1664 {target_t * t;
1665 for (t = targets; t; t = t->next)
1666 {
1667 if (t->type != &arm11_target)
1668 continue;
1669
1670 arm11_common_t * arm11 = t->arch_info;
1671
1672 if (arm11->jtag_info.chain_pos != jtag_target)
1673 continue;
1674
1675 return arm11;
1676 }}
1677
1678 return 0;
1679 }
1680
1681 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1682 {
1683 if (argc != (read ? 6 : 7))
1684 {
1685 ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1686 return -1;
1687 }
1688
1689 arm11_common_t * arm11 = arm11_find_target(args[0]);
1690
1691 if (!arm11)
1692 {
1693 ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1694 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1695
1696 return -1;
1697
1698 }
1699
1700 if (arm11->target->state != TARGET_HALTED)
1701 {
1702 WARNING("target was not halted");
1703 return ERROR_TARGET_NOT_HALTED;
1704 }
1705
1706
1707 u32 values[6];
1708
1709 {size_t i;
1710 for (i = 0; i < (read ? 5 : 6); i++)
1711 {
1712 values[i] = strtoul(args[i + 1], NULL, 0);
1713
1714 if (values[i] > arm11_coproc_instruction_limits[i])
1715 {
1716 ERROR("Parameter %d out of bounds (%d max). %s",
1717 i + 2, arm11_coproc_instruction_limits[i],
1718 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1719 return -1;
1720 }
1721 }}
1722
1723 u32 instr = 0xEE000010 |
1724 (values[0] << 8) |
1725 (values[1] << 21) |
1726 (values[2] << 16) |
1727 (values[3] << 0) |
1728 (values[4] << 5);
1729
1730 if (read)
1731 instr |= 0x00100000;
1732
1733
1734 arm11_run_instr_data_prepare(arm11);
1735
1736 if (read)
1737 {
1738 u32 result;
1739 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1740
1741 INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1742 values[0], values[1], values[2], values[3], values[4], result, result);
1743 }
1744 else
1745 {
1746 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1747
1748 INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1749 values[0], values[1],
1750 values[5],
1751 values[2], values[3], values[4]);
1752 }
1753
1754 arm11_run_instr_data_finish(arm11);
1755
1756
1757 return ERROR_OK;
1758 }
1759
1760 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1761 {
1762 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1763 }
1764
1765 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1766 {
1767 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1768 }
1769
1770 int arm11_register_commands(struct command_context_s *cmd_ctx)
1771 {
1772 FNC_INFO;
1773
1774 command_t * top_cmd = NULL;
1775
1776 RC_TOP( "arm11", "arm11 specific commands",
1777
1778 RC_TOP( "memwrite", "Control memory write transfer mode",
1779
1780 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1781 memwrite_burst)
1782
1783 RC_FINAL_BOOL( "error_fatal",
1784 "Terminate program if transfer error was found (default: enabled)",
1785 memwrite_error_fatal)
1786 )
1787
1788 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1789 arm11_handle_vcr)
1790
1791 RC_FINAL( "mrc", "Read Coprocessor register",
1792 arm11_handle_mrc)
1793
1794 RC_FINAL( "mcr", "Write Coprocessor register",
1795 arm11_handle_mcr)
1796 )
1797
1798 return ERROR_OK;
1799 }
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