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added arm11 timeout error messages
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "target_type.h"
33
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 uint32_t arm11_vcr = 0;
56 bool arm11_config_memrw_no_increment = false;
57 bool arm11_config_step_irq_enable = false;
58 bool arm11_config_hardware_step = false;
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 ARM11_HANDLER(quit),
101 };
102
103 int arm11_regs_arch_type = -1;
104
105
106 enum arm11_regtype
107 {
108 ARM11_REGISTER_CORE,
109 ARM11_REGISTER_CPSR,
110
111 ARM11_REGISTER_FX,
112 ARM11_REGISTER_FPS,
113
114 ARM11_REGISTER_FIQ,
115 ARM11_REGISTER_SVC,
116 ARM11_REGISTER_ABT,
117 ARM11_REGISTER_IRQ,
118 ARM11_REGISTER_UND,
119 ARM11_REGISTER_MON,
120
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
127
128 /* debug regs */
129 ARM11_REGISTER_DSCR,
130 ARM11_REGISTER_WDTR,
131 ARM11_REGISTER_RDTR,
132 };
133
134
135 typedef struct arm11_reg_defs_s
136 {
137 char * name;
138 uint32_t num;
139 int gdb_num;
140 enum arm11_regtype type;
141 } arm11_reg_defs_t;
142
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
145 {
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
162
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
173 #endif
174
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
176
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
186
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
190
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
194
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
198
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
202
203 /* ARM1176 only */
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
207 #endif
208
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
213 };
214
215 enum arm11_regcache_ids
216 {
217 ARM11_RC_R0,
218 ARM11_RC_RX = ARM11_RC_R0,
219
220 ARM11_RC_R1,
221 ARM11_RC_R2,
222 ARM11_RC_R3,
223 ARM11_RC_R4,
224 ARM11_RC_R5,
225 ARM11_RC_R6,
226 ARM11_RC_R7,
227 ARM11_RC_R8,
228 ARM11_RC_R9,
229 ARM11_RC_R10,
230 ARM11_RC_R11,
231 ARM11_RC_R12,
232 ARM11_RC_R13,
233 ARM11_RC_SP = ARM11_RC_R13,
234 ARM11_RC_R14,
235 ARM11_RC_LR = ARM11_RC_R14,
236 ARM11_RC_R15,
237 ARM11_RC_PC = ARM11_RC_R15,
238
239 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_F0,
241 ARM11_RC_FX = ARM11_RC_F0,
242 ARM11_RC_F1,
243 ARM11_RC_F2,
244 ARM11_RC_F3,
245 ARM11_RC_F4,
246 ARM11_RC_F5,
247 ARM11_RC_F6,
248 ARM11_RC_F7,
249 ARM11_RC_FPS,
250 #endif
251
252 ARM11_RC_CPSR,
253
254 #if ARM11_REGCACHE_MODEREGS
255 ARM11_RC_R8_FIQ,
256 ARM11_RC_R9_FIQ,
257 ARM11_RC_R10_FIQ,
258 ARM11_RC_R11_FIQ,
259 ARM11_RC_R12_FIQ,
260 ARM11_RC_R13_FIQ,
261 ARM11_RC_R14_FIQ,
262 ARM11_RC_SPSR_FIQ,
263
264 ARM11_RC_R13_SVC,
265 ARM11_RC_R14_SVC,
266 ARM11_RC_SPSR_SVC,
267
268 ARM11_RC_R13_ABT,
269 ARM11_RC_R14_ABT,
270 ARM11_RC_SPSR_ABT,
271
272 ARM11_RC_R13_IRQ,
273 ARM11_RC_R14_IRQ,
274 ARM11_RC_SPSR_IRQ,
275
276 ARM11_RC_R13_UND,
277 ARM11_RC_R14_UND,
278 ARM11_RC_SPSR_UND,
279
280 ARM11_RC_R13_MON,
281 ARM11_RC_R14_MON,
282 ARM11_RC_SPSR_MON,
283 #endif
284
285 ARM11_RC_DSCR,
286 ARM11_RC_WDTR,
287 ARM11_RC_RDTR,
288
289 ARM11_RC_MAX,
290 };
291
292 #define ARM11_GDB_REGISTER_COUNT 26
293
294 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295
296 reg_t arm11_gdb_dummy_fp_reg =
297 {
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
299 };
300
301 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
302
303 reg_t arm11_gdb_dummy_fps_reg =
304 {
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 };
307
308
309
310 /** Check and if necessary take control of the system
311 *
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
316 */
317 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
318 {
319 FNC_INFO;
320
321 uint32_t dscr_local_tmp_copy;
322
323 if (!dscr)
324 {
325 dscr = &dscr_local_tmp_copy;
326
327 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
328 }
329
330 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
331 {
332 LOG_DEBUG("Bringing target into debug mode");
333
334 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
335 arm11_write_DSCR(arm11, *dscr);
336
337 /* add further reset initialization here */
338
339 arm11->simulate_reset_on_next_halt = true;
340
341 if (*dscr & ARM11_DSCR_CORE_HALTED)
342 {
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
346 * the target.
347 */
348
349 arm11->target->state = TARGET_HALTED;
350 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 }
352 else
353 {
354 arm11->target->state = TARGET_RUNNING;
355 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
356 }
357
358 arm11_sc7_clear_vbw(arm11);
359 }
360
361 return ERROR_OK;
362 }
363
364
365
366 #define R(x) \
367 (arm11->reg_values[ARM11_RC_##x])
368
369 /** Save processor state.
370 *
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
373 *
374 */
375 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
376 {
377 int retval;
378 FNC_INFO;
379
380 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
381 {
382 arm11->reg_list[i].valid = 1;
383 arm11->reg_list[i].dirty = 0;
384 }
385
386 /* Save DSCR */
387 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
388
389 /* Save wDTR */
390
391 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
392 {
393 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
394
395 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
396
397 scan_field_t chain5_fields[3];
398
399 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
400 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
402
403 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
404 }
405 else
406 {
407 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
408 }
409
410
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
414
415 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
416
417 /* this executes JTAG queue: */
418
419 arm11_write_DSCR(arm11, new_dscr);
420
421
422 /* From the spec:
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
425
426 /** \todo TODO: Test drain write buffer. */
427
428 #if 0
429 while (1)
430 {
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
433
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11, 0xee070f9a);
436
437 uint32_t dscr = arm11_read_DSCR(arm11);
438
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
440
441 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
442 {
443 arm11_run_instr_no_data1(arm11, 0xe320f000);
444
445 dscr = arm11_read_DSCR(arm11);
446
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
448
449 break;
450 }
451 }
452 #endif
453
454 arm11_run_instr_data_prepare(arm11);
455
456 /* save r0 - r14 */
457
458 /** \todo TODO: handle other mode registers */
459
460 for (size_t i = 0; i < 15; i++)
461 {
462 /* MCR p14,0,R?,c0,c5,0 */
463 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
464 if (retval != ERROR_OK)
465 return retval;
466 }
467
468 /* save rDTR */
469
470 /* check rDTRfull in DSCR */
471
472 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
473 {
474 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
475 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
476 }
477 else
478 {
479 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
480 }
481
482 /* save CPSR */
483
484 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
485 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
486
487 /* save PC */
488
489 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
490 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
491 if (retval != ERROR_OK)
492 return retval;
493
494 /* adjust PC depending on ARM state */
495
496 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 0;
499 }
500 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
501 {
502 arm11->reg_values[ARM11_RC_PC] -= 4;
503 }
504 else /* ARM state */
505 {
506 arm11->reg_values[ARM11_RC_PC] -= 8;
507 }
508
509 if (arm11->simulate_reset_on_next_halt)
510 {
511 arm11->simulate_reset_on_next_halt = false;
512
513 LOG_DEBUG("Reset c1 Control Register");
514
515 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
516
517 /* MCR p15,0,R0,c1,c0,0 */
518 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
519
520 }
521
522 arm11_run_instr_data_finish(arm11);
523
524 arm11_dump_reg_changes(arm11);
525
526 return ERROR_OK;
527 }
528
529 void arm11_dump_reg_changes(arm11_common_t * arm11)
530 {
531
532 if (!(debug_level >= LOG_LVL_DEBUG))
533 {
534 return;
535 }
536
537 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
538 {
539 if (!arm11->reg_list[i].valid)
540 {
541 if (arm11->reg_history[i].valid)
542 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
543 }
544 else
545 {
546 if (arm11->reg_history[i].valid)
547 {
548 if (arm11->reg_history[i].value != arm11->reg_values[i])
549 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
550 }
551 else
552 {
553 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
554 }
555 }
556 }
557 }
558
559 /** Restore processor state
560 *
561 * This is called in preparation for the RESTART function.
562 *
563 */
564 int arm11_leave_debug_state(arm11_common_t * arm11)
565 {
566 FNC_INFO;
567
568 arm11_run_instr_data_prepare(arm11);
569
570 /** \todo TODO: handle other mode registers */
571
572 /* restore R1 - R14 */
573
574 for (size_t i = 1; i < 15; i++)
575 {
576 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
577 continue;
578
579 /* MRC p14,0,r?,c0,c5,0 */
580 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
581
582 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
583 }
584
585 arm11_run_instr_data_finish(arm11);
586
587 /* spec says clear wDTR and rDTR; we assume they are clear as
588 otherwise our programming would be sloppy */
589 {
590 uint32_t DSCR;
591
592 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
593
594 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
595 {
596 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
597 }
598 }
599
600 arm11_run_instr_data_prepare(arm11);
601
602 /* restore original wDTR */
603
604 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
605 {
606 /* MCR p14,0,R0,c0,c5,0 */
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
608 }
609
610 /* restore CPSR */
611
612 /* MSR CPSR,R0*/
613 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
614
615 /* restore PC */
616
617 /* MOV PC,R0 */
618 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
619
620 /* restore R0 */
621
622 /* MRC p14,0,r0,c0,c5,0 */
623 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
624
625 arm11_run_instr_data_finish(arm11);
626
627 /* restore DSCR */
628
629 arm11_write_DSCR(arm11, R(DSCR));
630
631 /* restore rDTR */
632
633 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
634 {
635 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
636
637 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
638
639 scan_field_t chain5_fields[3];
640
641 uint8_t Ready = 0; /* ignored */
642 uint8_t Valid = 0; /* ignored */
643
644 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
645 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
646 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
647
648 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
649 }
650
651 arm11_record_register_history(arm11);
652
653 return ERROR_OK;
654 }
655
656 void arm11_record_register_history(arm11_common_t * arm11)
657 {
658 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
659 {
660 arm11->reg_history[i].value = arm11->reg_values[i];
661 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
662
663 arm11->reg_list[i].valid = 0;
664 arm11->reg_list[i].dirty = 0;
665 }
666 }
667
668
669 /* poll current target status */
670 int arm11_poll(struct target_s *target)
671 {
672 FNC_INFO;
673 int retval;
674
675 arm11_common_t * arm11 = target->arch_info;
676
677 if (arm11->trst_active)
678 return ERROR_OK;
679
680 uint32_t dscr;
681
682 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
683
684 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
685
686 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
687
688 if (dscr & ARM11_DSCR_CORE_HALTED)
689 {
690 if (target->state != TARGET_HALTED)
691 {
692 enum target_state old_state = target->state;
693
694 LOG_DEBUG("enter TARGET_HALTED");
695 target->state = TARGET_HALTED;
696 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
697 retval = arm11_on_enter_debug_state(arm11);
698 if (retval != ERROR_OK)
699 return retval;
700
701 target_call_event_callbacks(target,
702 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
703 }
704 }
705 else
706 {
707 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
708 {
709 LOG_DEBUG("enter TARGET_RUNNING");
710 target->state = TARGET_RUNNING;
711 target->debug_reason = DBG_REASON_NOTHALTED;
712 }
713 }
714
715 return ERROR_OK;
716 }
717 /* architecture specific status reply */
718 int arm11_arch_state(struct target_s *target)
719 {
720 arm11_common_t * arm11 = target->arch_info;
721
722 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
723 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
724 R(CPSR),
725 R(PC));
726
727 return ERROR_OK;
728 }
729
730 /* target request support */
731 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
732 {
733 FNC_INFO_NOTIMPLEMENTED;
734
735 return ERROR_OK;
736 }
737
738 /* target execution control */
739 int arm11_halt(struct target_s *target)
740 {
741 FNC_INFO;
742
743 arm11_common_t * arm11 = target->arch_info;
744
745 LOG_DEBUG("target->state: %s",
746 target_state_name(target));
747
748 if (target->state == TARGET_UNKNOWN)
749 {
750 arm11->simulate_reset_on_next_halt = true;
751 }
752
753 if (target->state == TARGET_HALTED)
754 {
755 LOG_DEBUG("target was already halted");
756 return ERROR_OK;
757 }
758
759 if (arm11->trst_active)
760 {
761 arm11->halt_requested = true;
762 return ERROR_OK;
763 }
764
765 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
766
767 CHECK_RETVAL(jtag_execute_queue());
768
769 uint32_t dscr;
770
771 while (1)
772 {
773 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
774
775 if (dscr & ARM11_DSCR_CORE_HALTED)
776 break;
777 }
778
779 arm11_on_enter_debug_state(arm11);
780
781 enum target_state old_state = target->state;
782
783 target->state = TARGET_HALTED;
784 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
785
786 CHECK_RETVAL(
787 target_call_event_callbacks(target,
788 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
789
790 return ERROR_OK;
791 }
792
793 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
794 {
795 FNC_INFO;
796
797 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
798 // current, address, handle_breakpoints, debug_execution);
799
800 arm11_common_t * arm11 = target->arch_info;
801
802 LOG_DEBUG("target->state: %s",
803 target_state_name(target));
804
805
806 if (target->state != TARGET_HALTED)
807 {
808 LOG_ERROR("Target not halted");
809 return ERROR_TARGET_NOT_HALTED;
810 }
811
812 if (!current)
813 R(PC) = address;
814
815 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
816
817 /* clear breakpoints/watchpoints and VCR*/
818 arm11_sc7_clear_vbw(arm11);
819
820 /* Set up breakpoints */
821 if (!debug_execution)
822 {
823 /* check if one matches PC and step over it if necessary */
824
825 breakpoint_t * bp;
826
827 for (bp = target->breakpoints; bp; bp = bp->next)
828 {
829 if (bp->address == R(PC))
830 {
831 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
832 arm11_step(target, 1, 0, 0);
833 break;
834 }
835 }
836
837 /* set all breakpoints */
838
839 size_t brp_num = 0;
840
841 for (bp = target->breakpoints; bp; bp = bp->next)
842 {
843 arm11_sc7_action_t brp[2];
844
845 brp[0].write = 1;
846 brp[0].address = ARM11_SC7_BVR0 + brp_num;
847 brp[0].value = bp->address;
848 brp[1].write = 1;
849 brp[1].address = ARM11_SC7_BCR0 + brp_num;
850 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
851
852 arm11_sc7_run(arm11, brp, asizeof(brp));
853
854 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
855
856 brp_num++;
857 }
858
859 arm11_sc7_set_vcr(arm11, arm11_vcr);
860 }
861
862 arm11_leave_debug_state(arm11);
863
864 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
865
866 CHECK_RETVAL(jtag_execute_queue());
867
868 while (1)
869 {
870 uint32_t dscr;
871
872 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
873
874 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
875
876 if (dscr & ARM11_DSCR_CORE_RESTARTED)
877 break;
878 }
879
880 if (!debug_execution)
881 {
882 target->state = TARGET_RUNNING;
883 target->debug_reason = DBG_REASON_NOTHALTED;
884
885 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
886 }
887 else
888 {
889 target->state = TARGET_DEBUG_RUNNING;
890 target->debug_reason = DBG_REASON_NOTHALTED;
891
892 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
893 }
894
895 return ERROR_OK;
896 }
897
898
899 static int armv4_5_to_arm11(int reg)
900 {
901 if (reg < 16)
902 return reg;
903 switch (reg)
904 {
905 case ARMV4_5_CPSR:
906 return ARM11_RC_CPSR;
907 case 16:
908 /* FIX!!! handle thumb better! */
909 return ARM11_RC_CPSR;
910 default:
911 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
912 exit(-1);
913 }
914 }
915
916
917 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
918 {
919 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
920
921 reg=armv4_5_to_arm11(reg);
922
923 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
924 }
925
926 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
927 {
928 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
929
930 reg=armv4_5_to_arm11(reg);
931
932 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
933 }
934
935 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
936 {
937 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
938
939 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
940 }
941
942 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
943 {
944 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
945
946 /* FIX!!!! we should implement thumb for arm11 */
947 return ARMV4_5_STATE_ARM;
948 }
949
950 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
951 {
952 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
953
954 /* FIX!!!! we should implement thumb for arm11 */
955 LOG_ERROR("Not implemetned!");
956 }
957
958
959 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
960 {
961 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
962
963 /* FIX!!!! we should implement something that returns the current mode here!!! */
964 return ARMV4_5_MODE_USR;
965 }
966
967 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
968 {
969 struct arm_sim_interface sim;
970
971 sim.user_data=target->arch_info;
972 sim.get_reg=&arm11_sim_get_reg;
973 sim.set_reg=&arm11_sim_set_reg;
974 sim.get_reg_mode=&arm11_sim_get_reg;
975 sim.set_reg_mode=&arm11_sim_set_reg;
976 sim.get_cpsr=&arm11_sim_get_cpsr;
977 sim.get_mode=&arm11_sim_get_mode;
978 sim.get_state=&arm11_sim_get_state;
979 sim.set_state=&arm11_sim_set_state;
980
981 return arm_simulate_step_core(target, dry_run_pc, &sim);
982
983 }
984
985 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
986 {
987 FNC_INFO;
988
989 LOG_DEBUG("target->state: %s",
990 target_state_name(target));
991
992 if (target->state != TARGET_HALTED)
993 {
994 LOG_WARNING("target was not halted");
995 return ERROR_TARGET_NOT_HALTED;
996 }
997
998 arm11_common_t * arm11 = target->arch_info;
999
1000 if (!current)
1001 R(PC) = address;
1002
1003 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1004
1005
1006 /** \todo TODO: Thumb not supported here */
1007
1008 uint32_t next_instruction;
1009
1010 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1011
1012 /* skip over BKPT */
1013 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1014 {
1015 R(PC) += 4;
1016 arm11->reg_list[ARM11_RC_PC].valid = 1;
1017 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1018 LOG_DEBUG("Skipping BKPT");
1019 }
1020 /* skip over Wait for interrupt / Standby */
1021 /* mcr 15, 0, r?, cr7, cr0, {4} */
1022 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1023 {
1024 R(PC) += 4;
1025 arm11->reg_list[ARM11_RC_PC].valid = 1;
1026 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1027 LOG_DEBUG("Skipping WFI");
1028 }
1029 /* ignore B to self */
1030 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1031 {
1032 LOG_DEBUG("Not stepping jump to self");
1033 }
1034 else
1035 {
1036 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1037 * with this. */
1038
1039 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1040 * the VCR might be something worth looking into. */
1041
1042
1043 /* Set up breakpoint for stepping */
1044
1045 arm11_sc7_action_t brp[2];
1046
1047 brp[0].write = 1;
1048 brp[0].address = ARM11_SC7_BVR0;
1049 brp[1].write = 1;
1050 brp[1].address = ARM11_SC7_BCR0;
1051
1052 if (arm11_config_hardware_step)
1053 {
1054 /* hardware single stepping be used if possible or is it better to
1055 * always use the same code path? Hardware single stepping is not supported
1056 * on all hardware
1057 */
1058 brp[0].value = R(PC);
1059 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1060 } else
1061 {
1062 /* sets a breakpoint on the next PC(calculated by simulation),
1063 */
1064 uint32_t next_pc;
1065 int retval;
1066 retval = arm11_simulate_step(target, &next_pc);
1067 if (retval != ERROR_OK)
1068 return retval;
1069
1070 brp[0].value = next_pc;
1071 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1072 }
1073
1074 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1075
1076 /* resume */
1077
1078
1079 if (arm11_config_step_irq_enable)
1080 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1081 else
1082 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1083
1084
1085 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1086
1087 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1088
1089 CHECK_RETVAL(jtag_execute_queue());
1090
1091 /** \todo TODO: add a timeout */
1092
1093 /* wait for halt */
1094
1095 while (1)
1096 {
1097 uint32_t dscr;
1098
1099 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1100
1101 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1102
1103 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1104 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1105 break;
1106 }
1107
1108 /* clear breakpoint */
1109 arm11_sc7_clear_vbw(arm11);
1110
1111 /* save state */
1112 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1113
1114 /* restore default state */
1115 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1116
1117 }
1118
1119 // target->state = TARGET_HALTED;
1120 target->debug_reason = DBG_REASON_SINGLESTEP;
1121
1122 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1123
1124 return ERROR_OK;
1125 }
1126
1127 /* target reset control */
1128 int arm11_assert_reset(struct target_s *target)
1129 {
1130 FNC_INFO;
1131
1132 #if 0
1133 /* assert reset lines */
1134 /* resets only the DBGTAP, not the ARM */
1135
1136 jtag_add_reset(1, 0);
1137 jtag_add_sleep(5000);
1138
1139 arm11_common_t * arm11 = target->arch_info;
1140 arm11->trst_active = true;
1141 #endif
1142
1143 if (target->reset_halt)
1144 {
1145 CHECK_RETVAL(target_halt(target));
1146 }
1147
1148 return ERROR_OK;
1149 }
1150
1151 int arm11_deassert_reset(struct target_s *target)
1152 {
1153 FNC_INFO;
1154
1155 #if 0
1156 LOG_DEBUG("target->state: %s",
1157 target_state_name(target));
1158
1159
1160 /* deassert reset lines */
1161 jtag_add_reset(0, 0);
1162
1163 arm11_common_t * arm11 = target->arch_info;
1164 arm11->trst_active = false;
1165
1166 if (arm11->halt_requested)
1167 return arm11_halt(target);
1168 #endif
1169
1170 return ERROR_OK;
1171 }
1172
1173 int arm11_soft_reset_halt(struct target_s *target)
1174 {
1175 FNC_INFO_NOTIMPLEMENTED;
1176
1177 return ERROR_OK;
1178 }
1179
1180 /* target register access for gdb */
1181 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1182 {
1183 FNC_INFO;
1184
1185 arm11_common_t * arm11 = target->arch_info;
1186
1187 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1188 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1189
1190 for (size_t i = 16; i < 24; i++)
1191 {
1192 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1193 }
1194
1195 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1196
1197 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1198 {
1199 if (arm11_reg_defs[i].gdb_num == -1)
1200 continue;
1201
1202 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1203 }
1204
1205 return ERROR_OK;
1206 }
1207
1208 /* target memory access
1209 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1210 * count: number of items of <size>
1211 */
1212 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1213 {
1214 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1215
1216 FNC_INFO;
1217
1218 if (target->state != TARGET_HALTED)
1219 {
1220 LOG_WARNING("target was not halted");
1221 return ERROR_TARGET_NOT_HALTED;
1222 }
1223
1224 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1225
1226 arm11_common_t * arm11 = target->arch_info;
1227
1228 arm11_run_instr_data_prepare(arm11);
1229
1230 /* MRC p14,0,r0,c0,c5,0 */
1231 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1232
1233 switch (size)
1234 {
1235 case 1:
1236 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1237 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1238
1239 for (size_t i = 0; i < count; i++)
1240 {
1241 /* ldrb r1, [r0], #1 */
1242 /* ldrb r1, [r0] */
1243 arm11_run_instr_no_data1(arm11,
1244 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1245
1246 uint32_t res;
1247 /* MCR p14,0,R1,c0,c5,0 */
1248 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1249
1250 *buffer++ = res;
1251 }
1252
1253 break;
1254
1255 case 2:
1256 {
1257 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1258
1259 for (size_t i = 0; i < count; i++)
1260 {
1261 /* ldrh r1, [r0], #2 */
1262 arm11_run_instr_no_data1(arm11,
1263 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1264
1265 uint32_t res;
1266
1267 /* MCR p14,0,R1,c0,c5,0 */
1268 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1269
1270 uint16_t svalue = res;
1271 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1272 }
1273
1274 break;
1275 }
1276
1277 case 4:
1278 {
1279 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1280 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1281 uint32_t *words = (uint32_t *)buffer;
1282
1283 /* LDC p14,c5,[R0],#4 */
1284 /* LDC p14,c5,[R0] */
1285 arm11_run_instr_data_from_core(arm11, instr, words, count);
1286 break;
1287 }
1288 }
1289
1290 arm11_run_instr_data_finish(arm11);
1291
1292 return ERROR_OK;
1293 }
1294
1295 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1296 {
1297 FNC_INFO;
1298
1299 if (target->state != TARGET_HALTED)
1300 {
1301 LOG_WARNING("target was not halted");
1302 return ERROR_TARGET_NOT_HALTED;
1303 }
1304
1305 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1306
1307 arm11_common_t * arm11 = target->arch_info;
1308
1309 arm11_run_instr_data_prepare(arm11);
1310
1311 /* MRC p14,0,r0,c0,c5,0 */
1312 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1313
1314 switch (size)
1315 {
1316 case 1:
1317 {
1318 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1319
1320 for (size_t i = 0; i < count; i++)
1321 {
1322 /* MRC p14,0,r1,c0,c5,0 */
1323 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1324
1325 /* strb r1, [r0], #1 */
1326 /* strb r1, [r0] */
1327 arm11_run_instr_no_data1(arm11,
1328 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1329 }
1330
1331 break;
1332 }
1333
1334 case 2:
1335 {
1336 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1337
1338 for (size_t i = 0; i < count; i++)
1339 {
1340 uint16_t value;
1341 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1342
1343 /* MRC p14,0,r1,c0,c5,0 */
1344 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1345
1346 /* strh r1, [r0], #2 */
1347 /* strh r1, [r0] */
1348 arm11_run_instr_no_data1(arm11,
1349 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1350 }
1351
1352 break;
1353 }
1354
1355 case 4: {
1356 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1357
1358 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1359 uint32_t *words = (uint32_t*)buffer;
1360
1361 if (!arm11_config_memwrite_burst)
1362 {
1363 /* STC p14,c5,[R0],#4 */
1364 /* STC p14,c5,[R0]*/
1365 arm11_run_instr_data_to_core(arm11, instr, words, count);
1366 }
1367 else
1368 {
1369 /* STC p14,c5,[R0],#4 */
1370 /* STC p14,c5,[R0]*/
1371 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1372 }
1373
1374 break;
1375 }
1376 }
1377
1378 #if 1
1379 /* r0 verification */
1380 if (!arm11_config_memrw_no_increment)
1381 {
1382 uint32_t r0;
1383
1384 /* MCR p14,0,R0,c0,c5,0 */
1385 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1386
1387 if (address + size * count != r0)
1388 {
1389 LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
1390
1391 if (arm11_config_memwrite_burst)
1392 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1393
1394 if (arm11_config_memwrite_error_fatal)
1395 return ERROR_FAIL;
1396 }
1397 }
1398 #endif
1399
1400 arm11_run_instr_data_finish(arm11);
1401
1402 return ERROR_OK;
1403 }
1404
1405
1406 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1407 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1408 {
1409 FNC_INFO;
1410
1411 if (target->state != TARGET_HALTED)
1412 {
1413 LOG_WARNING("target was not halted");
1414 return ERROR_TARGET_NOT_HALTED;
1415 }
1416
1417 return arm11_write_memory(target, address, 4, count, buffer);
1418 }
1419
1420 /* here we have nothing target specific to contribute, so we fail and then the
1421 * fallback code will read data from the target and calculate the CRC on the
1422 * host.
1423 */
1424 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1425 {
1426 return ERROR_FAIL;
1427 }
1428
1429 /* target break-/watchpoint control
1430 * rw: 0 = write, 1 = read, 2 = access
1431 */
1432 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1433 {
1434 FNC_INFO;
1435
1436 arm11_common_t * arm11 = target->arch_info;
1437
1438 #if 0
1439 if (breakpoint->type == BKPT_SOFT)
1440 {
1441 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1443 }
1444 #endif
1445
1446 if (!arm11->free_brps)
1447 {
1448 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1450 }
1451
1452 if (breakpoint->length != 4)
1453 {
1454 LOG_DEBUG("only breakpoints of four bytes length supported");
1455 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1456 }
1457
1458 arm11->free_brps--;
1459
1460 return ERROR_OK;
1461 }
1462
1463 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1464 {
1465 FNC_INFO;
1466
1467 arm11_common_t * arm11 = target->arch_info;
1468
1469 arm11->free_brps++;
1470
1471 return ERROR_OK;
1472 }
1473
1474 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1475 {
1476 FNC_INFO_NOTIMPLEMENTED;
1477
1478 return ERROR_OK;
1479 }
1480
1481 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1482 {
1483 FNC_INFO_NOTIMPLEMENTED;
1484
1485 return ERROR_OK;
1486 }
1487
1488 // HACKHACKHACK - FIXME mode/state
1489 /* target algorithm support */
1490 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1491 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1492 int timeout_ms, void *arch_info)
1493 {
1494 arm11_common_t *arm11 = target->arch_info;
1495 // enum armv4_5_state core_state = arm11->core_state;
1496 // enum armv4_5_mode core_mode = arm11->core_mode;
1497 uint32_t context[16];
1498 uint32_t cpsr;
1499 int exit_breakpoint_size = 0;
1500 int retval = ERROR_OK;
1501 LOG_DEBUG("Running algorithm");
1502
1503
1504 if (target->state != TARGET_HALTED)
1505 {
1506 LOG_WARNING("target not halted");
1507 return ERROR_TARGET_NOT_HALTED;
1508 }
1509
1510 // FIXME
1511 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1512 // return ERROR_FAIL;
1513
1514 // Save regs
1515 for (size_t i = 0; i < 16; i++)
1516 {
1517 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1518 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1519 }
1520
1521 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1522 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1523
1524 for (int i = 0; i < num_mem_params; i++)
1525 {
1526 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1527 }
1528
1529 // Set register parameters
1530 for (int i = 0; i < num_reg_params; i++)
1531 {
1532 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1533 if (!reg)
1534 {
1535 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1536 exit(-1);
1537 }
1538
1539 if (reg->size != reg_params[i].size)
1540 {
1541 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1542 exit(-1);
1543 }
1544 arm11_set_reg(reg,reg_params[i].value);
1545 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1546 }
1547
1548 exit_breakpoint_size = 4;
1549
1550 /* arm11->core_state = arm11_algorithm_info->core_state;
1551 if (arm11->core_state == ARMV4_5_STATE_ARM)
1552 exit_breakpoint_size = 4;
1553 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1554 exit_breakpoint_size = 2;
1555 else
1556 {
1557 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1558 exit(-1);
1559 }
1560 */
1561
1562
1563 /* arm11 at this point only supports ARM not THUMB mode
1564 however if this test needs to be reactivated the current state can be read back
1565 from CPSR */
1566 #if 0
1567 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1568 {
1569 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1570 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1571 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1572 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1573 }
1574 #endif
1575
1576 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1577 {
1578 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1579 retval = ERROR_TARGET_FAILURE;
1580 goto restore;
1581 }
1582
1583 // no debug, otherwise breakpoint is not set
1584 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1585
1586 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1587
1588 if (target->state != TARGET_HALTED)
1589 {
1590 CHECK_RETVAL(target_halt(target));
1591
1592 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1593
1594 retval = ERROR_TARGET_TIMEOUT;
1595
1596 goto del_breakpoint;
1597 }
1598
1599 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1600 {
1601 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1602 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1603 retval = ERROR_TARGET_TIMEOUT;
1604 goto del_breakpoint;
1605 }
1606
1607 for (int i = 0; i < num_mem_params; i++)
1608 {
1609 if (mem_params[i].direction != PARAM_OUT)
1610 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1611 }
1612
1613 for (int i = 0; i < num_reg_params; i++)
1614 {
1615 if (reg_params[i].direction != PARAM_OUT)
1616 {
1617 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1618 if (!reg)
1619 {
1620 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1621 exit(-1);
1622 }
1623
1624 if (reg->size != reg_params[i].size)
1625 {
1626 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1627 exit(-1);
1628 }
1629
1630 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1631 }
1632 }
1633
1634 del_breakpoint:
1635 breakpoint_remove(target, exit_point);
1636
1637 restore:
1638 // Restore context
1639 for (size_t i = 0; i < 16; i++)
1640 {
1641 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1642 arm11->reg_list[i].name, context[i]);
1643 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1644 }
1645 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1646 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1647
1648 // arm11->core_state = core_state;
1649 // arm11->core_mode = core_mode;
1650
1651 return retval;
1652 }
1653
1654 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1655 {
1656 FNC_INFO;
1657
1658 NEW(arm11_common_t, arm11, 1);
1659
1660 arm11->target = target;
1661
1662 if (target->tap == NULL)
1663 return ERROR_FAIL;
1664
1665 if (target->tap->ir_length != 5)
1666 {
1667 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1668 return ERROR_COMMAND_SYNTAX_ERROR;
1669 }
1670
1671 target->arch_info = arm11;
1672
1673 return ERROR_OK;
1674 }
1675
1676 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1677 {
1678 /* Initialize anything we can set up without talking to the target */
1679 return arm11_build_reg_cache(target);
1680 }
1681
1682 /* talk to the target and set things up */
1683 int arm11_examine(struct target_s *target)
1684 {
1685 FNC_INFO;
1686
1687 arm11_common_t * arm11 = target->arch_info;
1688
1689 /* check IDCODE */
1690
1691 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1692
1693 scan_field_t idcode_field;
1694
1695 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1696
1697 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1698
1699 /* check DIDR */
1700
1701 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1702
1703 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1704
1705 scan_field_t chain0_fields[2];
1706
1707 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1708 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1709
1710 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1711
1712 CHECK_RETVAL(jtag_execute_queue());
1713
1714 switch (arm11->device_id & 0x0FFFF000)
1715 {
1716 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1717 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1718 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1719 default:
1720 {
1721 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1722 return ERROR_FAIL;
1723 }
1724 }
1725
1726 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1727
1728 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1729 arm11->debug_version != ARM11_DEBUG_V61)
1730 {
1731 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1732 return ERROR_FAIL;
1733 }
1734
1735 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1736 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1737
1738 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1739 arm11->free_brps = arm11->brp;
1740 arm11->free_wrps = arm11->wrp;
1741
1742 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1743 arm11->device_id,
1744 (int)(arm11->implementor),
1745 arm11->didr);
1746
1747 /* as a side-effect this reads DSCR and thus
1748 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1749 * as suggested by the spec.
1750 */
1751
1752 arm11_check_init(arm11, NULL);
1753
1754 target_set_examined(target);
1755
1756 return ERROR_OK;
1757 }
1758
1759 int arm11_quit(void)
1760 {
1761 FNC_INFO_NOTIMPLEMENTED;
1762
1763 return ERROR_OK;
1764 }
1765
1766 /** Load a register that is marked !valid in the register cache */
1767 int arm11_get_reg(reg_t *reg)
1768 {
1769 FNC_INFO;
1770
1771 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1772
1773 if (target->state != TARGET_HALTED)
1774 {
1775 LOG_WARNING("target was not halted");
1776 return ERROR_TARGET_NOT_HALTED;
1777 }
1778
1779 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1780
1781 #if 0
1782 arm11_common_t *arm11 = target->arch_info;
1783 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1784 #endif
1785
1786 return ERROR_OK;
1787 }
1788
1789 /** Change a value in the register cache */
1790 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1791 {
1792 FNC_INFO;
1793
1794 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1795 arm11_common_t *arm11 = target->arch_info;
1796 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1797
1798 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1799 reg->valid = 1;
1800 reg->dirty = 1;
1801
1802 return ERROR_OK;
1803 }
1804
1805 int arm11_build_reg_cache(target_t *target)
1806 {
1807 arm11_common_t *arm11 = target->arch_info;
1808
1809 NEW(reg_cache_t, cache, 1);
1810 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1811 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1812
1813 if (arm11_regs_arch_type == -1)
1814 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1815
1816 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1817 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1818
1819 arm11->reg_list = reg_list;
1820
1821 /* Build the process context cache */
1822 cache->name = "arm11 registers";
1823 cache->next = NULL;
1824 cache->reg_list = reg_list;
1825 cache->num_regs = ARM11_REGCACHE_COUNT;
1826
1827 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1828 (*cache_p) = cache;
1829
1830 arm11->core_cache = cache;
1831 // armv7m->process_context = cache;
1832
1833 size_t i;
1834
1835 /* Not very elegant assertion */
1836 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1837 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1838 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1839 {
1840 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1841 exit(-1);
1842 }
1843
1844 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1845 {
1846 reg_t * r = reg_list + i;
1847 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1848 arm11_reg_state_t * rs = arm11_reg_states + i;
1849
1850 r->name = rd->name;
1851 r->size = 32;
1852 r->value = (uint8_t *)(arm11->reg_values + i);
1853 r->dirty = 0;
1854 r->valid = 0;
1855 r->bitfield_desc = NULL;
1856 r->num_bitfields = 0;
1857 r->arch_type = arm11_regs_arch_type;
1858 r->arch_info = rs;
1859
1860 rs->def_index = i;
1861 rs->target = target;
1862 }
1863
1864 return ERROR_OK;
1865 }
1866
1867 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1868 {
1869 if (argc == 0)
1870 {
1871 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1872 return ERROR_OK;
1873 }
1874
1875 if (argc != 1)
1876 return ERROR_COMMAND_SYNTAX_ERROR;
1877
1878 switch (args[0][0])
1879 {
1880 case '0': /* 0 */
1881 case 'f': /* false */
1882 case 'F':
1883 case 'd': /* disable */
1884 case 'D':
1885 *var = false;
1886 break;
1887
1888 case '1': /* 1 */
1889 case 't': /* true */
1890 case 'T':
1891 case 'e': /* enable */
1892 case 'E':
1893 *var = true;
1894 break;
1895 }
1896
1897 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1898
1899 return ERROR_OK;
1900 }
1901
1902 #define BOOL_WRAPPER(name, print_name) \
1903 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1904 { \
1905 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1906 }
1907
1908 #define RC_TOP(name, descr, more) \
1909 { \
1910 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1911 command_t * top_cmd = new_cmd; \
1912 more \
1913 }
1914
1915 #define RC_FINAL(name, descr, handler) \
1916 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1917
1918 #define RC_FINAL_BOOL(name, descr, var) \
1919 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1920
1921 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1922 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1923 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1924 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1925 BOOL_WRAPPER(hardware_step, "hardware single step")
1926
1927 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1928 {
1929 if (argc == 1)
1930 {
1931 arm11_vcr = strtoul(args[0], NULL, 0);
1932 }
1933 else if (argc != 0)
1934 {
1935 return ERROR_COMMAND_SYNTAX_ERROR;
1936 }
1937
1938 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1939 return ERROR_OK;
1940 }
1941
1942 const uint32_t arm11_coproc_instruction_limits[] =
1943 {
1944 15, /* coprocessor */
1945 7, /* opcode 1 */
1946 15, /* CRn */
1947 15, /* CRm */
1948 7, /* opcode 2 */
1949 0xFFFFFFFF, /* value */
1950 };
1951
1952 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1953 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1954
1955 arm11_common_t * arm11_find_target(const char * arg)
1956 {
1957 jtag_tap_t * tap;
1958 target_t * t;
1959
1960 tap = jtag_tap_by_string(arg);
1961
1962 if (!tap)
1963 return 0;
1964
1965 for (t = all_targets; t; t = t->next)
1966 {
1967 if (t->tap != tap)
1968 continue;
1969
1970 /* if (t->type == arm11_target) */
1971 if (0 == strcmp(target_get_name(t), "arm11"))
1972 return t->arch_info;
1973 }
1974
1975 return 0;
1976 }
1977
1978 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1979 {
1980 if (argc != (read ? 6 : 7))
1981 {
1982 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1983 return -1;
1984 }
1985
1986 arm11_common_t * arm11 = arm11_find_target(args[0]);
1987
1988 if (!arm11)
1989 {
1990 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1991 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1992
1993 return -1;
1994 }
1995
1996 if (arm11->target->state != TARGET_HALTED)
1997 {
1998 LOG_WARNING("target was not halted");
1999 return ERROR_TARGET_NOT_HALTED;
2000 }
2001
2002 uint32_t values[6];
2003
2004 for (size_t i = 0; i < (read ? 5 : 6); i++)
2005 {
2006 values[i] = strtoul(args[i + 1], NULL, 0);
2007
2008 if (values[i] > arm11_coproc_instruction_limits[i])
2009 {
2010 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
2011 (long)(i + 2),
2012 arm11_coproc_instruction_limits[i],
2013 read ? arm11_mrc_syntax : arm11_mcr_syntax);
2014 return -1;
2015 }
2016 }
2017
2018 uint32_t instr = 0xEE000010 |
2019 (values[0] << 8) |
2020 (values[1] << 21) |
2021 (values[2] << 16) |
2022 (values[3] << 0) |
2023 (values[4] << 5);
2024
2025 if (read)
2026 instr |= 0x00100000;
2027
2028 arm11_run_instr_data_prepare(arm11);
2029
2030 if (read)
2031 {
2032 uint32_t result;
2033 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2034
2035 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2036 (int)(values[0]),
2037 (int)(values[1]),
2038 (int)(values[2]),
2039 (int)(values[3]),
2040 (int)(values[4]), result, result);
2041 }
2042 else
2043 {
2044 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2045
2046 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2047 (int)(values[0]), (int)(values[1]),
2048 values[5],
2049 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2050 }
2051
2052 arm11_run_instr_data_finish(arm11);
2053
2054
2055 return ERROR_OK;
2056 }
2057
2058 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2059 {
2060 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2061 }
2062
2063 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2064 {
2065 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2066 }
2067
2068 int arm11_register_commands(struct command_context_s *cmd_ctx)
2069 {
2070 FNC_INFO;
2071
2072 command_t * top_cmd = NULL;
2073
2074 RC_TOP("arm11", "arm11 specific commands",
2075
2076 RC_TOP("memwrite", "Control memory write transfer mode",
2077
2078 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
2079 memwrite_burst)
2080
2081 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
2082 memwrite_error_fatal)
2083 ) /* memwrite */
2084
2085 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
2086 memrw_no_increment)
2087
2088 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
2089 step_irq_enable)
2090 RC_FINAL_BOOL("hardware_step", "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
2091 hardware_step)
2092
2093 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
2094 arm11_handle_vcr)
2095
2096 RC_FINAL("mrc", "Read Coprocessor register",
2097 arm11_handle_mrc)
2098
2099 RC_FINAL("mcr", "Write Coprocessor register",
2100 arm11_handle_mcr)
2101 ) /* arm11 */
2102
2103 return ERROR_OK;
2104 }
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