src/target/arm11.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  19  ***************************************************************************/
  20
  21 #ifndef OPENOCD_TARGET_ARM11_H
  22 #define OPENOCD_TARGET_ARM11_H
  23
  24 #include "arm.h"
  25 #include "arm_dpm.h"
  26
  27 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  28
  29 #define CHECK_RETVAL(action)                    \
  30         do {                                    \
  31                 int __retval = (action);        \
  32                 if (__retval != ERROR_OK) {     \
  33                         LOG_DEBUG("error while calling \"%s\"", \
  34                                 # action);     \
  35                         return __retval;        \
  36                 }                               \
  37         } while (0)
  38
  39 /* bits from ARMv7 DIDR */
  40 enum arm11_debug_version {
  41         ARM11_DEBUG_V6                  = 0x01,
  42         ARM11_DEBUG_V61                 = 0x02,
  43         ARM11_DEBUG_V7                  = 0x03,
  44         ARM11_DEBUG_V7_CP14             = 0x04,
  45 };
  46
  47 struct arm11_common {
  48         struct arm arm;
  49
  50         /** Debug module state. */
  51         struct arm_dpm dpm;
  52         struct arm11_sc7_action *bpwp_actions;
  53         unsigned bpwp_n;
  54
  55         size_t brp;                     /**< Number of Breakpoint Register Pairs from DIDR      */
  56         size_t free_brps;               /**< Number of breakpoints allocated */
  57
  58         uint32_t dscr;                  /**< Last retrieved DSCR value. */
  59
  60         uint32_t saved_rdtr;
  61         uint32_t saved_wdtr;
  62
  63         bool is_rdtr_saved;
  64         bool is_wdtr_saved;
  65
  66         bool simulate_reset_on_next_halt;       /**< Perform cleanups of the ARM state on next halt **/
  67
  68         /* Per-core configurable options.
  69          * NOTE that several of these boolean options should not exist
  70          * once the relevant code is known to work correctly.
  71          */
  72         bool memwrite_burst;
  73         bool memwrite_error_fatal;
  74         bool step_irq_enable;
  75         bool hardware_step;
  76
  77         /** Configured Vector Catch Register settings. */
  78         uint32_t vcr;
  79
  80         struct arm_jtag jtag_info;
  81 };
  82
  83 static inline struct arm11_common *target_to_arm11(struct target *target)
  84 {
  85         return container_of(target->arch_info, struct arm11_common, arm);
  86 }
  87
  88 /**
  89  * ARM11 DBGTAP instructions
  90  *
  91  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  92  */
  93 enum arm11_instructions {
  94         ARM11_EXTEST    = 0x00,
  95         ARM11_SCAN_N    = 0x02,
  96         ARM11_RESTART   = 0x04,
  97         ARM11_HALT          = 0x08,
  98         ARM11_INTEST    = 0x0C,
  99         ARM11_ITRSEL    = 0x1D,
 100         ARM11_IDCODE    = 0x1E,
 101         ARM11_BYPASS    = 0x1F,
 102 };
 103
 104 enum arm11_sc7 {
 105         ARM11_SC7_NULL                          = 0,
 106         ARM11_SC7_VCR                           = 7,
 107         ARM11_SC7_PC                            = 8,
 108         ARM11_SC7_BVR0                          = 64,
 109         ARM11_SC7_BCR0                          = 80,
 110         ARM11_SC7_WVR0                          = 96,
 111         ARM11_SC7_WCR0                          = 112,
 112 };
 113
 114 #endif /* OPENOCD_TARGET_ARM11_H */