1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
31 #define JTAG_DEBUG(expr ...) \
33 log_printf (LOG_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr); \
36 #define JTAG_DEBUG(expr ...) \
40 enum tap_state arm11_move_pi_to_si_via_ci
[] =
42 TAP_E2I
, TAP_UI
, TAP_SDS
, TAP_SIS
, TAP_CI
, TAP_SI
46 int arm11_add_ir_scan_vc(int num_fields
, scan_field_t
*fields
, enum tap_state state
)
48 if (cmd_queue_cur_state
== TAP_PI
)
49 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
51 return jtag_add_ir_scan(num_fields
, fields
, state
);
54 enum tap_state arm11_move_pd_to_sd_via_cd
[] =
56 TAP_E2D
, TAP_UD
, TAP_SDS
, TAP_CD
, TAP_SD
59 int arm11_add_dr_scan_vc(int num_fields
, scan_field_t
*fields
, enum tap_state state
)
61 if (cmd_queue_cur_state
== TAP_PD
)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
64 return jtag_add_dr_scan(num_fields
, fields
, state
);
68 /** Code de-clutter: Construct scan_field_t to write out a value
70 * \param arm11 Target state variable.
71 * \param num_bits Length of the data field
72 * \param out_data pointer to the data that will be sent out
73 * <em>(data is read when it is added to the JTAG queue)</em>
74 * \param in_data pointer to the memory that will receive data that was clocked in
75 * <em>(data is written when the JTAG queue is executed)</em>
76 * \param field target data structure that will be initialized
78 void arm11_setup_field(arm11_common_t
* arm11
, int num_bits
, void * out_data
, void * in_data
, scan_field_t
* field
)
80 field
->device
= arm11
->jtag_info
.chain_pos
;
81 field
->num_bits
= num_bits
;
82 field
->out_mask
= NULL
;
83 field
->in_check_mask
= NULL
;
84 field
->in_check_value
= NULL
;
85 field
->in_handler
= NULL
;
86 field
->in_handler_priv
= NULL
;
88 field
->out_value
= out_data
;
89 field
->in_value
= in_data
;
93 /** Write JTAG instruction register
95 * \param arm11 Target state variable.
96 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
97 * \param state Pass the final TAP state or -1 for the default value (Pause-IR).
99 * \remarks This adds to the JTAG command queue but does \em not execute it.
101 void arm11_add_IR(arm11_common_t
* arm11
, u8 instr
, enum tap_state state
)
103 jtag_device_t
*device
= jtag_get_device(arm11
->jtag_info
.chain_pos
);
105 if (buf_get_u32(device
->cur_instr
, 0, 5) == instr
)
107 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
111 JTAG_DEBUG("IR <= 0x%02x", instr
);
115 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
117 arm11_add_ir_scan_vc(1, &field
, state
== -1 ? TAP_PI
: state
);
120 /** Verify shifted out data from Scan Chain Register (SCREG)
121 * Used as parameter to scan_field_t::in_handler in
122 * arm11_add_debug_SCAN_N().
125 static int arm11_in_handler_SCAN_N(u8
*in_value
, void *priv
, struct scan_field_s
*field
)
127 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
128 u8 v
= *in_value
& 0x1F;
132 ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
136 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
140 /** Select and write to Scan Chain Register (SCREG)
142 * This function sets the instruction register to SCAN_N and writes
143 * the data register with the selected chain number.
145 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
147 * \param arm11 Target state variable.
148 * \param chain Scan chain that will be selected.
149 * \param state Pass the final TAP state or -1 for the default
152 * The chain takes effect when Update-DR is passed (usually when subsequently
153 * the INTEXT/EXTEST instructions are written).
155 * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
156 * in Pause-DR. The second call, due to the IR caching, will not
157 * go through Capture-DR when shifting in the new scan chain number.
158 * As a result the verification in arm11_in_handler_SCAN_N() must
161 * \remarks This adds to the JTAG command queue but does \em not execute it.
164 void arm11_add_debug_SCAN_N(arm11_common_t
* arm11
, u8 chain
, enum tap_state state
)
166 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
168 arm11_add_IR(arm11
, ARM11_SCAN_N
, -1);
172 arm11_setup_field(arm11
, 5, &chain
, NULL
, &field
);
174 field
.in_handler
= arm11_in_handler_SCAN_N
;
176 arm11_add_dr_scan_vc(1, &field
, state
== -1 ? TAP_PD
: state
);
179 /** Write an instruction into the ITR register
181 * \param arm11 Target state variable.
182 * \param inst An ARM11 processor instruction/opcode.
183 * \param flag Optional parameter to retrieve the InstCompl flag
184 * (this will be written when the JTAG chain is executed).
185 * \param state Pass the final TAP state or -1 for the default
186 * value (Run-Test/Idle).
188 * \remarks By default this ends with Run-Test/Idle state
189 * and causes the instruction to be executed. If
190 * a subsequent write to DTR is needed before
191 * executing the instruction then TAP_PD should be
192 * passed to \p state.
194 * \remarks This adds to the JTAG command queue but does \em not execute it.
196 void arm11_add_debug_INST(arm11_common_t
* arm11
, u32 inst
, u8
* flag
, enum tap_state state
)
198 JTAG_DEBUG("INST <= 0x%08x", inst
);
202 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
203 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
205 arm11_add_dr_scan_vc(asizeof(itr
), itr
, state
== -1 ? TAP_RTI
: state
);
208 /** Read the Debug Status and Control Register (DSCR)
212 * \param arm11 Target state variable.
213 * \return DSCR content
215 * \remarks This is a stand-alone function that executes the JTAG command queue.
217 u32
arm11_read_DSCR(arm11_common_t
* arm11
)
219 arm11_add_debug_SCAN_N(arm11
, 0x01, -1);
221 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
224 scan_field_t chain1_field
;
226 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
228 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_PD
);
230 jtag_execute_queue();
232 if (arm11
->last_dscr
!= dscr
)
233 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
235 arm11
->last_dscr
= dscr
;
240 /** Write the Debug Status and Control Register (DSCR)
244 * \param arm11 Target state variable.
245 * \param dscr DSCR content
247 * \remarks This is a stand-alone function that executes the JTAG command queue.
249 void arm11_write_DSCR(arm11_common_t
* arm11
, u32 dscr
)
251 arm11_add_debug_SCAN_N(arm11
, 0x01, -1);
253 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
255 scan_field_t chain1_field
;
257 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
259 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_PD
);
261 jtag_execute_queue();
263 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
265 arm11
->last_dscr
= dscr
;
270 /** Get the debug reason from Debug Status and Control Register (DSCR)
272 * \param dscr DSCR value to analyze
273 * \return Debug reason
276 enum target_debug_reason
arm11_get_DSCR_debug_reason(u32 dscr
)
278 switch (dscr
& ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
)
280 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
: return DBG_REASON_DBGRQ
;
281 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
: return DBG_REASON_BREAKPOINT
;
282 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
: return DBG_REASON_WATCHPOINT
;
283 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
: return DBG_REASON_BREAKPOINT
;
284 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
: return DBG_REASON_DBGRQ
;
285 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
: return DBG_REASON_BREAKPOINT
;
288 return DBG_REASON_DBGRQ
;
294 /** Prepare the stage for ITR/DTR operations
295 * from the arm11_run_instr... group of functions.
297 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
298 * around a block of arm11_run_instr_... calls.
300 * Select scan chain 5 to allow quick access to DTR. When scan
301 * chain 4 is needed to put in a register the ITRSel instruction
302 * shortcut is used instead of actually changing the Scan_N
305 * \param arm11 Target state variable.
308 void arm11_run_instr_data_prepare(arm11_common_t
* arm11
)
310 arm11_add_debug_SCAN_N(arm11
, 0x05, -1);
313 /** Cleanup after ITR/DTR operations
314 * from the arm11_run_instr... group of functions
316 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
317 * around a block of arm11_run_instr_... calls.
319 * Any RTI can lead to an instruction execution when
320 * scan chains 4 or 5 are selected and the IR holds
321 * INTEST or EXTEST. So we must disable that before
322 * any following activities lead to an RTI.
324 * \param arm11 Target state variable.
327 void arm11_run_instr_data_finish(arm11_common_t
* arm11
)
329 arm11_add_debug_SCAN_N(arm11
, 0x00, -1);
333 /** Execute one or multiple instructions via ITR
335 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
337 * \param arm11 Target state variable.
338 * \param opcode Pointer to sequence of ARM opcodes
339 * \param count Number of opcodes to execute
342 void arm11_run_instr_no_data(arm11_common_t
* arm11
, u32
* opcode
, size_t count
)
344 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
348 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_RTI
);
354 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_RTI
: TAP_PD
);
356 jtag_execute_queue();
364 /** Execute one instruction via ITR
366 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
368 * \param arm11 Target state variable.
369 * \param opcode ARM opcode
372 void arm11_run_instr_no_data1(arm11_common_t
* arm11
, u32 opcode
)
374 arm11_run_instr_no_data(arm11
, &opcode
, 1);
378 /** Execute one instruction via ITR repeatedly while
379 * passing data to the core via DTR on each execution.
381 * The executed instruction \em must read data from DTR.
383 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
385 * \param arm11 Target state variable.
386 * \param opcode ARM opcode
387 * \param data Pointer to the data words to be passed to the core
388 * \param count Number of data words and instruction repetitions
391 void arm11_run_instr_data_to_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
393 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
395 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_PD
);
397 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
399 scan_field_t chain5_fields
[3];
405 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
406 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
407 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
415 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_RTI
);
416 jtag_execute_queue();
418 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
425 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
431 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
432 jtag_execute_queue();
434 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
439 /** JTAG path for arm11_run_instr_data_to_core_noack
441 * The repeated TAP_RTI's do not cause a repeated execution
442 * if passed without leaving the state.
444 * Since this is more than 7 bits (adjustable via adding more
445 * TAP_RTI's) it produces an artificial delay in the lower
446 * layer (FT2232) that is long enough to finish execution on
447 * the core but still shorter than any manually inducible delays.
450 enum tap_state arm11_MOVE_PD_RTI_PD_with_delay
[] =
452 TAP_E2D
, TAP_UD
, TAP_RTI
, TAP_RTI
, TAP_RTI
, TAP_SDS
, TAP_CD
, TAP_SD
457 /** Execute one instruction via ITR repeatedly while
458 * passing data to the core via DTR on each execution.
460 * No Ready check during transmission.
462 * The executed instruction \em must read data from DTR.
464 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
466 * \param arm11 Target state variable.
467 * \param opcode ARM opcode
468 * \param data Pointer to the data words to be passed to the core
469 * \param count Number of data words and instruction repetitions
472 void arm11_run_instr_data_to_core_noack(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
474 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
476 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_PD
);
478 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
480 scan_field_t chain5_fields
[3];
482 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
483 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
484 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
486 u8 Readies
[count
+ 1];
487 u8
* ReadyPos
= Readies
;
491 chain5_fields
[0].out_value
= (void *)(data
++);
492 chain5_fields
[1].in_value
= ReadyPos
++;
496 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
497 jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay
),
498 arm11_MOVE_PD_RTI_PD_with_delay
);
502 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_RTI
);
506 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
508 chain5_fields
[0].out_value
= 0;
509 chain5_fields
[1].in_value
= ReadyPos
++;
511 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_PD
);
513 jtag_execute_queue();
515 size_t error_count
= 0;
518 for (i
= 0; i
< asizeof(Readies
); i
++)
527 ERROR("Transfer errors %d", error_count
);
531 /** Execute an instruction via ITR while handing data into the core via DTR.
533 * The executed instruction \em must read data from DTR.
535 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
537 * \param arm11 Target state variable.
538 * \param opcode ARM opcode
539 * \param data Data word to be passed to the core via DTR
542 void arm11_run_instr_data_to_core1(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
544 arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
548 /** Execute one instruction via ITR repeatedly while
549 * reading data from the core via DTR on each execution.
551 * The executed instruction \em must write data to DTR.
553 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
555 * \param arm11 Target state variable.
556 * \param opcode ARM opcode
557 * \param data Pointer to an array that receives the data words from the core
558 * \param count Number of data words and instruction repetitions
561 void arm11_run_instr_data_from_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
563 arm11_add_IR(arm11
, ARM11_ITRSEL
, -1);
565 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_RTI
);
567 arm11_add_IR(arm11
, ARM11_INTEST
, -1);
569 scan_field_t chain5_fields
[3];
575 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
576 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
577 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
583 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, count
? TAP_RTI
: TAP_PD
);
584 jtag_execute_queue();
586 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
594 /** Execute one instruction via ITR
595 * then load r0 into DTR and read DTR from core.
597 * The first executed instruction (\p opcode) should write data to r0.
599 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
601 * \param arm11 Target state variable.
602 * \param opcode ARM opcode to write r0 with the value of interest
603 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
606 void arm11_run_instr_data_from_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32
* data
)
608 arm11_run_instr_no_data1(arm11
, opcode
);
610 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
611 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
614 /** Load data into core via DTR then move it to r0 then
615 * execute one instruction via ITR
617 * The final executed instruction (\p opcode) should read data from r0.
619 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
621 * \param arm11 Target state variable.
622 * \param opcode ARM opcode to read r0 act upon it
623 * \param data Data word that will be written to r0 before \p opcode is executed
626 void arm11_run_instr_data_to_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
628 /* MRC p14,0,r0,c0,c5,0 */
629 arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
631 arm11_run_instr_no_data1(arm11
, opcode
);
634 /** Apply reads and writes to scan chain 7
636 * \see arm11_sc7_action_t
638 * \param arm11 Target state variable.
639 * \param actions A list of read and/or write instructions
640 * \param count Number of instructions in the list.
643 void arm11_sc7_run(arm11_common_t
* arm11
, arm11_sc7_action_t
* actions
, size_t count
)
645 arm11_add_debug_SCAN_N(arm11
, 0x07, -1);
647 arm11_add_IR(arm11
, ARM11_EXTEST
, -1);
649 scan_field_t chain7_fields
[3];
658 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
659 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
660 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
663 for (i
= 0; i
< count
+ 1; i
++)
667 nRW
= actions
[i
].write
? 1 : 0;
668 DataOut
= actions
[i
].value
;
669 AddressOut
= actions
[i
].address
;
680 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut
, DataOut
, nRW
);
682 arm11_add_dr_scan_vc(asizeof(chain7_fields
), chain7_fields
, TAP_PD
);
683 jtag_execute_queue();
685 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn
, DataIn
, Ready
);
687 while (!Ready
); /* 'nRW' is 'Ready' on read out */
691 if (actions
[i
- 1].address
!= AddressIn
)
693 WARNING("Scan chain 7 shifted out unexpected address");
696 if (!actions
[i
- 1].write
)
698 actions
[i
- 1].value
= DataIn
;
702 if (actions
[i
- 1].value
!= DataIn
)
704 WARNING("Scan chain 7 shifted out unexpected data");
711 for (i
= 0; i
< count
; i
++)
713 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i
, actions
[i
].address
, actions
[i
].write
? "<=" : "=>", actions
[i
].value
);
717 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
719 * \param arm11 Target state variable.
722 void arm11_sc7_clear_vbw(arm11_common_t
* arm11
)
724 arm11_sc7_action_t clear_bw
[arm11
->brp
+ arm11
->wrp
+ 1];
725 arm11_sc7_action_t
* pos
= clear_bw
;
728 for (i
= 0; i
< asizeof(clear_bw
); i
++)
730 clear_bw
[i
].write
= 1;
731 clear_bw
[i
].value
= 0;
735 for (i
= 0; i
< arm11
->brp
; i
++)
736 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
740 for (i
= 0; i
< arm11
->wrp
; i
++)
741 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
744 (pos
++)->address
= ARM11_SC7_VCR
;
747 /** Write VCR register
749 * \param arm11 Target state variable.
750 * \param value Value to be written
752 void arm11_sc7_set_vcr(arm11_common_t
* arm11
, u32 value
)
754 arm11_sc7_action_t set_vcr
;
757 set_vcr
.address
= ARM11_SC7_VCR
;
758 set_vcr
.value
= value
;
761 arm11_sc7_run(arm11
, &set_vcr
, 1);
766 /** Read word from address
768 * \param arm11 Target state variable.
769 * \param address Memory address to be read
770 * \param result Pointer where to store result
773 void arm11_read_memory_word(arm11_common_t
* arm11
, u32 address
, u32
* result
)
775 arm11_run_instr_data_prepare(arm11
);
777 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
778 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
780 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
781 arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1);
783 arm11_run_instr_data_finish(arm11
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)