1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
39 tap_state_t arm11_move_pi_to_si_via_ci
[] =
41 TAP_IREXIT2
, TAP_IRUPDATE
, TAP_DRSELECT
, TAP_IRSELECT
, TAP_IRCAPTURE
, TAP_IRSHIFT
45 int arm11_add_ir_scan_vc(int num_fields
, scan_field_t
*fields
, tap_state_t state
)
47 if (cmd_queue_cur_state
== TAP_IRPAUSE
)
48 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
50 jtag_add_ir_scan(num_fields
, fields
, state
);
54 tap_state_t arm11_move_pd_to_sd_via_cd
[] =
56 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
59 int arm11_add_dr_scan_vc(int num_fields
, scan_field_t
*fields
, tap_state_t state
)
61 if (cmd_queue_cur_state
== TAP_DRPAUSE
)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
64 jtag_add_dr_scan(num_fields
, fields
, state
);
69 /** Code de-clutter: Construct scan_field_t to write out a value
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
79 void arm11_setup_field(arm11_common_t
* arm11
, int num_bits
, void * out_data
, void * in_data
, scan_field_t
* field
)
81 field
->tap
= arm11
->jtag_info
.tap
;
82 field
->num_bits
= num_bits
;
83 field
->out_mask
= NULL
;
84 field
->in_check_mask
= NULL
;
85 field
->in_check_value
= NULL
;
86 field
->in_handler
= NULL
;
87 field
->in_handler_priv
= NULL
;
89 field
->out_value
= out_data
;
90 field
->in_value
= in_data
;
94 /** Write JTAG instruction register
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
102 void arm11_add_IR(arm11_common_t
* arm11
, u8 instr
, tap_state_t state
)
105 tap
= arm11
->jtag_info
.tap
;
107 if (buf_get_u32(tap
->cur_instr
, 0, 5) == instr
)
109 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
113 JTAG_DEBUG("IR <= 0x%02x", instr
);
117 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
119 arm11_add_ir_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_IRPAUSE
: state
);
122 /** Verify shifted out data from Scan Chain Register (SCREG)
123 * Used as parameter to scan_field_t::in_handler in
124 * arm11_add_debug_SCAN_N().
127 static int arm11_in_handler_SCAN_N(u8
*in_value
, void *priv
, struct scan_field_s
*field
)
129 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
130 u8 v
= *in_value
& 0x1F;
134 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
138 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
142 /** Select and write to Scan Chain Register (SCREG)
144 * This function sets the instruction register to SCAN_N and writes
145 * the data register with the selected chain number.
147 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
149 * \param arm11 Target state variable.
150 * \param chain Scan chain that will be selected.
151 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
154 * The chain takes effect when Update-DR is passed (usually when subsequently
155 * the INTEXT/EXTEST instructions are written).
157 * \warning (Obsolete) Using this twice in a row will \em fail. The first
158 * call will end in Pause-DR. The second call, due to the IR
159 * caching, will not go through Capture-DR when shifting in the
160 * new scan chain number. As a result the verification in
161 * arm11_in_handler_SCAN_N() must fail.
163 * \remarks This adds to the JTAG command queue but does \em not execute it.
166 void arm11_add_debug_SCAN_N(arm11_common_t
* arm11
, u8 chain
, tap_state_t state
)
168 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
170 arm11_add_IR(arm11
, ARM11_SCAN_N
, ARM11_TAP_DEFAULT
);
174 arm11_setup_field(arm11
, 5, &chain
, NULL
, &field
);
176 field
.in_handler
= arm11_in_handler_SCAN_N
;
178 arm11_add_dr_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_DRPAUSE
: state
);
181 /** Write an instruction into the ITR register
183 * \param arm11 Target state variable.
184 * \param inst An ARM11 processor instruction/opcode.
185 * \param flag Optional parameter to retrieve the InstCompl flag
186 * (this will be written when the JTAG chain is executed).
187 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
188 * value (Run-Test/Idle).
190 * \remarks By default this ends with Run-Test/Idle state
191 * and causes the instruction to be executed. If
192 * a subsequent write to DTR is needed before
193 * executing the instruction then TAP_DRPAUSE should be
194 * passed to \p state.
196 * \remarks This adds to the JTAG command queue but does \em not execute it.
198 void arm11_add_debug_INST(arm11_common_t
* arm11
, u32 inst
, u8
* flag
, tap_state_t state
)
200 JTAG_DEBUG("INST <= 0x%08x", inst
);
204 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
205 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
207 arm11_add_dr_scan_vc(asizeof(itr
), itr
, state
== ARM11_TAP_DEFAULT
? TAP_IDLE
: state
);
210 /** Read the Debug Status and Control Register (DSCR)
214 * \param arm11 Target state variable.
215 * \return DSCR content
217 * \remarks This is a stand-alone function that executes the JTAG command queue.
219 int arm11_read_DSCR(arm11_common_t
* arm11
, u32
*value
)
221 arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
223 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
226 scan_field_t chain1_field
;
228 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
230 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
232 CHECK_RETVAL(jtag_execute_queue());
234 if (arm11
->last_dscr
!= dscr
)
235 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
237 arm11
->last_dscr
= dscr
;
244 /** Write the Debug Status and Control Register (DSCR)
248 * \param arm11 Target state variable.
249 * \param dscr DSCR content
251 * \remarks This is a stand-alone function that executes the JTAG command queue.
253 int arm11_write_DSCR(arm11_common_t
* arm11
, u32 dscr
)
255 arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
257 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
259 scan_field_t chain1_field
;
261 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
263 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
265 CHECK_RETVAL(jtag_execute_queue());
267 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
269 arm11
->last_dscr
= dscr
;
276 /** Get the debug reason from Debug Status and Control Register (DSCR)
278 * \param dscr DSCR value to analyze
279 * \return Debug reason
282 enum target_debug_reason
arm11_get_DSCR_debug_reason(u32 dscr
)
284 switch (dscr
& ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
)
286 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
:
287 LOG_INFO("Debug entry: JTAG HALT");
288 return DBG_REASON_DBGRQ
;
290 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
:
291 LOG_INFO("Debug entry: breakpoint");
292 return DBG_REASON_BREAKPOINT
;
294 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
:
295 LOG_INFO("Debug entry: watchpoint");
296 return DBG_REASON_WATCHPOINT
;
298 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
:
299 LOG_INFO("Debug entry: BKPT instruction");
300 return DBG_REASON_BREAKPOINT
;
302 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
:
303 LOG_INFO("Debug entry: EDBGRQ signal");
304 return DBG_REASON_DBGRQ
;
306 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
:
307 LOG_INFO("Debug entry: VCR vector catch");
308 return DBG_REASON_BREAKPOINT
;
311 LOG_INFO("Debug entry: unknown");
312 return DBG_REASON_DBGRQ
;
318 /** Prepare the stage for ITR/DTR operations
319 * from the arm11_run_instr... group of functions.
321 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
322 * around a block of arm11_run_instr_... calls.
324 * Select scan chain 5 to allow quick access to DTR. When scan
325 * chain 4 is needed to put in a register the ITRSel instruction
326 * shortcut is used instead of actually changing the Scan_N
329 * \param arm11 Target state variable.
332 void arm11_run_instr_data_prepare(arm11_common_t
* arm11
)
334 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
337 /** Cleanup after ITR/DTR operations
338 * from the arm11_run_instr... group of functions
340 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
341 * around a block of arm11_run_instr_... calls.
343 * Any IDLE can lead to an instruction execution when
344 * scan chains 4 or 5 are selected and the IR holds
345 * INTEST or EXTEST. So we must disable that before
346 * any following activities lead to an IDLE.
348 * \param arm11 Target state variable.
351 void arm11_run_instr_data_finish(arm11_common_t
* arm11
)
353 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
357 /** Execute one or multiple instructions via ITR
359 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
361 * \param arm11 Target state variable.
362 * \param opcode Pointer to sequence of ARM opcodes
363 * \param count Number of opcodes to execute
366 int arm11_run_instr_no_data(arm11_common_t
* arm11
, u32
* opcode
, size_t count
)
368 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
372 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_IDLE
);
378 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_IDLE
: TAP_DRPAUSE
);
380 CHECK_RETVAL(jtag_execute_queue());
390 /** Execute one instruction via ITR
392 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
394 * \param arm11 Target state variable.
395 * \param opcode ARM opcode
398 void arm11_run_instr_no_data1(arm11_common_t
* arm11
, u32 opcode
)
400 arm11_run_instr_no_data(arm11
, &opcode
, 1);
404 /** Execute one instruction via ITR repeatedly while
405 * passing data to the core via DTR on each execution.
407 * The executed instruction \em must read data from DTR.
409 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
411 * \param arm11 Target state variable.
412 * \param opcode ARM opcode
413 * \param data Pointer to the data words to be passed to the core
414 * \param count Number of data words and instruction repetitions
417 int arm11_run_instr_data_to_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
419 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
421 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
423 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
425 scan_field_t chain5_fields
[3];
431 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
432 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
433 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
441 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_IDLE
);
443 CHECK_RETVAL(jtag_execute_queue());
445 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
452 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
458 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
460 CHECK_RETVAL(jtag_execute_queue());
462 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
469 /** JTAG path for arm11_run_instr_data_to_core_noack
471 * The repeated TAP_IDLE's do not cause a repeated execution
472 * if passed without leaving the state.
474 * Since this is more than 7 bits (adjustable via adding more
475 * TAP_IDLE's) it produces an artificial delay in the lower
476 * layer (FT2232) that is long enough to finish execution on
477 * the core but still shorter than any manually inducible delays.
480 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
[] =
482 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_IDLE
, TAP_IDLE
, TAP_IDLE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
487 /** Execute one instruction via ITR repeatedly while
488 * passing data to the core via DTR on each execution.
490 * No Ready check during transmission.
492 * The executed instruction \em must read data from DTR.
494 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
496 * \param arm11 Target state variable.
497 * \param opcode ARM opcode
498 * \param data Pointer to the data words to be passed to the core
499 * \param count Number of data words and instruction repetitions
502 int arm11_run_instr_data_to_core_noack(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
504 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
506 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
508 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
510 scan_field_t chain5_fields
[3];
512 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
513 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
514 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
516 u8 Readies
[count
+ 1];
517 u8
* ReadyPos
= Readies
;
521 chain5_fields
[0].out_value
= (void *)(data
++);
522 chain5_fields
[1].in_value
= ReadyPos
++;
526 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
527 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
),
528 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
);
532 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_IDLE
);
536 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
538 chain5_fields
[0].out_value
= 0;
539 chain5_fields
[1].in_value
= ReadyPos
++;
541 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
543 CHECK_RETVAL(jtag_execute_queue());
545 size_t error_count
= 0;
548 for (i
= 0; i
< asizeof(Readies
); i
++)
557 LOG_ERROR("Transfer errors " ZU
, error_count
);
563 /** Execute an instruction via ITR while handing data into the core via DTR.
565 * The executed instruction \em must read data from DTR.
567 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
569 * \param arm11 Target state variable.
570 * \param opcode ARM opcode
571 * \param data Data word to be passed to the core via DTR
574 int arm11_run_instr_data_to_core1(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
576 return arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
580 /** Execute one instruction via ITR repeatedly while
581 * reading data from the core via DTR on each execution.
583 * The executed instruction \em must write data to DTR.
585 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
587 * \param arm11 Target state variable.
588 * \param opcode ARM opcode
589 * \param data Pointer to an array that receives the data words from the core
590 * \param count Number of data words and instruction repetitions
593 int arm11_run_instr_data_from_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
595 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
597 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_IDLE
);
599 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
601 scan_field_t chain5_fields
[3];
607 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
608 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
609 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
615 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, count
? TAP_IDLE
: TAP_DRPAUSE
);
617 CHECK_RETVAL(jtag_execute_queue());
619 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
629 /** Execute one instruction via ITR
630 * then load r0 into DTR and read DTR from core.
632 * The first executed instruction (\p opcode) should write data to r0.
634 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
636 * \param arm11 Target state variable.
637 * \param opcode ARM opcode to write r0 with the value of interest
638 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
641 void arm11_run_instr_data_from_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32
* data
)
643 arm11_run_instr_no_data1(arm11
, opcode
);
645 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
646 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
649 /** Load data into core via DTR then move it to r0 then
650 * execute one instruction via ITR
652 * The final executed instruction (\p opcode) should read data from r0.
654 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
656 * \param arm11 Target state variable.
657 * \param opcode ARM opcode to read r0 act upon it
658 * \param data Data word that will be written to r0 before \p opcode is executed
661 void arm11_run_instr_data_to_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
663 /* MRC p14,0,r0,c0,c5,0 */
664 arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
666 arm11_run_instr_no_data1(arm11
, opcode
);
669 /** Apply reads and writes to scan chain 7
671 * \see arm11_sc7_action_t
673 * \param arm11 Target state variable.
674 * \param actions A list of read and/or write instructions
675 * \param count Number of instructions in the list.
678 int arm11_sc7_run(arm11_common_t
* arm11
, arm11_sc7_action_t
* actions
, size_t count
)
680 arm11_add_debug_SCAN_N(arm11
, 0x07, ARM11_TAP_DEFAULT
);
682 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
684 scan_field_t chain7_fields
[3];
693 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
694 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
695 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
698 for (i
= 0; i
< count
+ 1; i
++)
702 nRW
= actions
[i
].write
? 1 : 0;
703 DataOut
= actions
[i
].value
;
704 AddressOut
= actions
[i
].address
;
715 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut
, DataOut
, nRW
);
717 arm11_add_dr_scan_vc(asizeof(chain7_fields
), chain7_fields
, TAP_DRPAUSE
);
719 CHECK_RETVAL(jtag_execute_queue());
721 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn
, DataIn
, Ready
);
723 while (!Ready
); /* 'nRW' is 'Ready' on read out */
727 if (actions
[i
- 1].address
!= AddressIn
)
729 LOG_WARNING("Scan chain 7 shifted out unexpected address");
732 if (!actions
[i
- 1].write
)
734 actions
[i
- 1].value
= DataIn
;
738 if (actions
[i
- 1].value
!= DataIn
)
740 LOG_WARNING("Scan chain 7 shifted out unexpected data");
747 for (i
= 0; i
< count
; i
++)
749 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i
, actions
[i
].address
, actions
[i
].write
? "<=" : "=>", actions
[i
].value
);
755 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
757 * \param arm11 Target state variable.
760 void arm11_sc7_clear_vbw(arm11_common_t
* arm11
)
762 arm11_sc7_action_t clear_bw
[arm11
->brp
+ arm11
->wrp
+ 1];
763 arm11_sc7_action_t
* pos
= clear_bw
;
766 for (i
= 0; i
< asizeof(clear_bw
); i
++)
768 clear_bw
[i
].write
= true;
769 clear_bw
[i
].value
= 0;
773 for (i
= 0; i
< arm11
->brp
; i
++)
774 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
778 for (i
= 0; i
< arm11
->wrp
; i
++)
779 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
782 (pos
++)->address
= ARM11_SC7_VCR
;
784 arm11_sc7_run(arm11
, clear_bw
, asizeof(clear_bw
));
787 /** Write VCR register
789 * \param arm11 Target state variable.
790 * \param value Value to be written
792 void arm11_sc7_set_vcr(arm11_common_t
* arm11
, u32 value
)
794 arm11_sc7_action_t set_vcr
;
796 set_vcr
.write
= true;
797 set_vcr
.address
= ARM11_SC7_VCR
;
798 set_vcr
.value
= value
;
801 arm11_sc7_run(arm11
, &set_vcr
, 1);
806 /** Read word from address
808 * \param arm11 Target state variable.
809 * \param address Memory address to be read
810 * \param result Pointer where to store result
813 int arm11_read_memory_word(arm11_common_t
* arm11
, u32 address
, u32
* result
)
815 arm11_run_instr_data_prepare(arm11
);
817 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
818 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
));
820 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
821 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1));
823 arm11_run_instr_data_finish(arm11
);
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