1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm720t_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm720t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm720t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm720t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 /* forward declarations */
45 int arm720t_target_create(struct target_s
*target
,Jim_Interp
*interp
);
46 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm720t_quit(void);
48 int arm720t_arch_state(struct target_s
*target
);
49 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
50 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
51 int arm720t_soft_reset_halt(struct target_s
*target
);
53 target_type_t arm720t_target
=
58 .arch_state
= arm720t_arch_state
,
61 .resume
= arm7_9_resume
,
64 .assert_reset
= arm7_9_assert_reset
,
65 .deassert_reset
= arm7_9_deassert_reset
,
66 .soft_reset_halt
= arm720t_soft_reset_halt
,
68 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
70 .read_memory
= arm720t_read_memory
,
71 .write_memory
= arm720t_write_memory
,
72 .bulk_write_memory
= arm7_9_bulk_write_memory
,
73 .checksum_memory
= arm7_9_checksum_memory
,
74 .blank_check_memory
= arm7_9_blank_check_memory
,
76 .run_algorithm
= armv4_5_run_algorithm
,
78 .add_breakpoint
= arm7_9_add_breakpoint
,
79 .remove_breakpoint
= arm7_9_remove_breakpoint
,
80 .add_watchpoint
= arm7_9_add_watchpoint
,
81 .remove_watchpoint
= arm7_9_remove_watchpoint
,
83 .register_commands
= arm720t_register_commands
,
84 .target_create
= arm720t_target_create
,
85 .init_target
= arm720t_init_target
,
86 .examine
= arm7tdmi_examine
,
90 int arm720t_scan_cp15(target_t
*target
, u32 out
, u32
*in
, int instruction
, int clock
)
92 int retval
= ERROR_OK
;
93 armv4_5_common_t
*armv4_5
= target
->arch_info
;
94 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
95 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
96 scan_field_t fields
[2];
98 u8 instruction_buf
= instruction
;
100 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
102 jtag_add_end_state(TAP_PD
);
103 if((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
107 if((retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
)) != ERROR_OK
)
112 fields
[0].tap
= jtag_info
->tap
;
113 fields
[0].num_bits
= 1;
114 fields
[0].out_value
= &instruction_buf
;
115 fields
[0].out_mask
= NULL
;
116 fields
[0].in_value
= NULL
;
117 fields
[0].in_check_value
= NULL
;
118 fields
[0].in_check_mask
= NULL
;
119 fields
[0].in_handler
= NULL
;
120 fields
[0].in_handler_priv
= NULL
;
122 fields
[1].tap
= jtag_info
->tap
;
123 fields
[1].num_bits
= 32;
124 fields
[1].out_value
= out_buf
;
125 fields
[1].out_mask
= NULL
;
126 fields
[1].in_value
= NULL
;
129 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
130 fields
[1].in_handler_priv
= in
;
133 fields
[1].in_handler
= NULL
;
134 fields
[1].in_handler_priv
= NULL
;
136 fields
[1].in_check_value
= NULL
;
137 fields
[1].in_check_mask
= NULL
;
139 jtag_add_dr_scan(2, fields
, -1);
142 jtag_add_runtest(0, -1);
144 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
145 if((retval
= jtag_execute_queue()) != ERROR_OK
)
151 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
153 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
155 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
161 int arm720t_read_cp15(target_t
*target
, u32 opcode
, u32
*value
)
163 /* fetch CP15 opcode */
164 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
166 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
167 /* "EXECUTE" stage (1) */
168 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
169 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
170 /* "EXECUTE" stage (2) */
171 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
172 /* "EXECUTE" stage (3), CDATA is read */
173 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
178 int arm720t_write_cp15(target_t
*target
, u32 opcode
, u32 value
)
180 /* fetch CP15 opcode */
181 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
183 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
184 /* "EXECUTE" stage (1) */
185 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
186 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
187 /* "EXECUTE" stage (2) */
188 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
189 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
194 u32
arm720t_get_ttb(target_t
*target
)
198 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
199 jtag_execute_queue();
206 void arm720t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
210 /* read cp15 control register */
211 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
212 jtag_execute_queue();
215 cp15_control
&= ~0x1U
;
217 if (d_u_cache
|| i_cache
)
218 cp15_control
&= ~0x4U
;
220 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
223 void arm720t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
227 /* read cp15 control register */
228 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
229 jtag_execute_queue();
232 cp15_control
|= 0x1U
;
234 if (d_u_cache
|| i_cache
)
235 cp15_control
|= 0x4U
;
237 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
240 void arm720t_post_debug_entry(target_t
*target
)
242 armv4_5_common_t
*armv4_5
= target
->arch_info
;
243 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
244 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
245 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
247 /* examine cp15 control reg */
248 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
249 jtag_execute_queue();
250 LOG_DEBUG("cp15_control_reg: %8.8x", arm720t
->cp15_control_reg
);
252 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
253 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
254 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
256 /* save i/d fault status and address register */
257 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
258 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
259 jtag_execute_queue();
262 void arm720t_pre_restore_context(target_t
*target
)
264 armv4_5_common_t
*armv4_5
= target
->arch_info
;
265 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
266 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
267 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
269 /* restore i/d fault status and address register */
270 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
271 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
274 int arm720t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm7tdmi_common_t
**arm7tdmi_p
, arm720t_common_t
**arm720t_p
)
276 armv4_5_common_t
*armv4_5
= target
->arch_info
;
277 arm7_9_common_t
*arm7_9
;
278 arm7tdmi_common_t
*arm7tdmi
;
279 arm720t_common_t
*arm720t
;
281 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
286 arm7_9
= armv4_5
->arch_info
;
287 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
292 arm7tdmi
= arm7_9
->arch_info
;
293 if (arm7tdmi
->common_magic
!= ARM7TDMI_COMMON_MAGIC
)
298 arm720t
= arm7tdmi
->arch_info
;
299 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
)
304 *armv4_5_p
= armv4_5
;
306 *arm7tdmi_p
= arm7tdmi
;
307 *arm720t_p
= arm720t
;
312 int arm720t_arch_state(struct target_s
*target
)
314 armv4_5_common_t
*armv4_5
= target
->arch_info
;
315 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
316 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
317 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
321 "disabled", "enabled"
324 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
326 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
330 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
331 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
332 "MMU: %s, Cache: %s",
333 armv4_5_state_strings
[armv4_5
->core_state
],
334 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
335 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
336 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
337 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
338 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
339 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
344 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
347 armv4_5_common_t
*armv4_5
= target
->arch_info
;
348 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
349 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
350 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
352 /* disable cache, but leave MMU enabled */
353 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
354 arm720t_disable_mmu_caches(target
, 0, 1, 0);
356 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
358 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
359 arm720t_enable_mmu_caches(target
, 0, 1, 0);
364 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
368 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
374 int arm720t_soft_reset_halt(struct target_s
*target
)
376 int retval
= ERROR_OK
;
377 armv4_5_common_t
*armv4_5
= target
->arch_info
;
378 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
379 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
380 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
381 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
383 if ((retval
= target_halt(target
)) != ERROR_OK
)
388 long long then
=timeval_ms();
390 while (!(timeout
=((timeval_ms()-then
)>1000)))
392 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
394 embeddedice_read_reg(dbg_stat
);
395 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
413 LOG_ERROR("Failed to halt CPU after 1 sec");
414 return ERROR_TARGET_TIMEOUT
;
417 target
->state
= TARGET_HALTED
;
419 /* SVC, ARM state, IRQ and FIQ disabled */
420 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
421 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
422 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
424 /* start fetching from 0x0 */
425 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
426 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
427 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
429 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
430 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
432 arm720t_disable_mmu_caches(target
, 1, 1, 1);
433 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
434 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
435 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
437 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
445 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
447 arm7tdmi_init_target(cmd_ctx
, target
);
453 int arm720t_quit(void)
459 int arm720t_init_arch_info(target_t
*target
, arm720t_common_t
*arm720t
, jtag_tap_t
*tap
, const char *variant
)
461 arm7tdmi_common_t
*arm7tdmi
= &arm720t
->arm7tdmi_common
;
462 arm7_9_common_t
*arm7_9
= &arm7tdmi
->arm7_9_common
;
464 arm7tdmi_init_arch_info(target
, arm7tdmi
, tap
, variant
);
466 arm7tdmi
->arch_info
= arm720t
;
467 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
469 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
470 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
472 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
473 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
474 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
475 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
476 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
477 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
478 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
479 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
484 int arm720t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
486 arm720t_common_t
*arm720t
= calloc(1,sizeof(arm720t_common_t
));
488 arm720t_init_arch_info(target
, arm720t
, target
->tap
, target
->variant
);
493 int arm720t_register_commands(struct command_context_s
*cmd_ctx
)
496 command_t
*arm720t_cmd
;
499 retval
= arm7tdmi_register_commands(cmd_ctx
);
501 arm720t_cmd
= register_command(cmd_ctx
, NULL
, "arm720t", NULL
, COMMAND_ANY
, "arm720t specific commands");
503 register_command(cmd_ctx
, arm720t_cmd
, "cp15", arm720t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode> [value]");
504 register_command(cmd_ctx
, arm720t_cmd
, "virt2phys", arm720t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
506 register_command(cmd_ctx
, arm720t_cmd
, "mdw_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
507 register_command(cmd_ctx
, arm720t_cmd
, "mdh_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
508 register_command(cmd_ctx
, arm720t_cmd
, "mdb_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
510 register_command(cmd_ctx
, arm720t_cmd
, "mww_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
511 register_command(cmd_ctx
, arm720t_cmd
, "mwh_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
512 register_command(cmd_ctx
, arm720t_cmd
, "mwb_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
517 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
520 target_t
*target
= get_current_target(cmd_ctx
);
521 armv4_5_common_t
*armv4_5
;
522 arm7_9_common_t
*arm7_9
;
523 arm7tdmi_common_t
*arm7tdmi
;
524 arm720t_common_t
*arm720t
;
525 arm_jtag_t
*jtag_info
;
527 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
529 command_print(cmd_ctx
, "current target isn't an ARM720t target");
533 jtag_info
= &arm7_9
->jtag_info
;
535 if (target
->state
!= TARGET_HALTED
)
537 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
541 /* one or more argument, access a single register (write if second argument is given */
544 u32 opcode
= strtoul(args
[0], NULL
, 0);
549 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
551 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
555 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
560 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
564 u32 value
= strtoul(args
[1], NULL
, 0);
565 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
567 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
570 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
577 int arm720t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
579 target_t
*target
= get_current_target(cmd_ctx
);
580 armv4_5_common_t
*armv4_5
;
581 arm7_9_common_t
*arm7_9
;
582 arm7tdmi_common_t
*arm7tdmi
;
583 arm720t_common_t
*arm720t
;
584 arm_jtag_t
*jtag_info
;
586 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
588 command_print(cmd_ctx
, "current target isn't an ARM720t target");
592 jtag_info
= &arm7_9
->jtag_info
;
594 if (target
->state
!= TARGET_HALTED
)
596 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
600 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
603 int arm720t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
605 target_t
*target
= get_current_target(cmd_ctx
);
606 armv4_5_common_t
*armv4_5
;
607 arm7_9_common_t
*arm7_9
;
608 arm7tdmi_common_t
*arm7tdmi
;
609 arm720t_common_t
*arm720t
;
610 arm_jtag_t
*jtag_info
;
612 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
614 command_print(cmd_ctx
, "current target isn't an ARM720t target");
618 jtag_info
= &arm7_9
->jtag_info
;
620 if (target
->state
!= TARGET_HALTED
)
622 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
626 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
629 int arm720t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
631 target_t
*target
= get_current_target(cmd_ctx
);
632 armv4_5_common_t
*armv4_5
;
633 arm7_9_common_t
*arm7_9
;
634 arm7tdmi_common_t
*arm7tdmi
;
635 arm720t_common_t
*arm720t
;
636 arm_jtag_t
*jtag_info
;
638 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
640 command_print(cmd_ctx
, "current target isn't an ARM720t target");
644 jtag_info
= &arm7_9
->jtag_info
;
646 if (target
->state
!= TARGET_HALTED
)
648 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
652 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)