1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm720t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm720t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm720t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm720t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 /* forward declarations */
44 int arm720t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
45 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm720t_arch_state(struct target_s
*target
);
48 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
49 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
50 int arm720t_soft_reset_halt(struct target_s
*target
);
52 target_type_t arm720t_target
=
57 .arch_state
= arm720t_arch_state
,
60 .resume
= arm7_9_resume
,
63 .assert_reset
= arm7_9_assert_reset
,
64 .deassert_reset
= arm7_9_deassert_reset
,
65 .soft_reset_halt
= arm720t_soft_reset_halt
,
67 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
69 .read_memory
= arm720t_read_memory
,
70 .write_memory
= arm720t_write_memory
,
71 .bulk_write_memory
= arm7_9_bulk_write_memory
,
72 .checksum_memory
= arm7_9_checksum_memory
,
74 .run_algorithm
= armv4_5_run_algorithm
,
76 .add_breakpoint
= arm7_9_add_breakpoint
,
77 .remove_breakpoint
= arm7_9_remove_breakpoint
,
78 .add_watchpoint
= arm7_9_add_watchpoint
,
79 .remove_watchpoint
= arm7_9_remove_watchpoint
,
81 .register_commands
= arm720t_register_commands
,
82 .target_command
= arm720t_target_command
,
83 .init_target
= arm720t_init_target
,
87 int arm720t_scan_cp15(target_t
*target
, u32 out
, u32
*in
, int instruction
, int clock
)
89 armv4_5_common_t
*armv4_5
= target
->arch_info
;
90 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
91 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
92 scan_field_t fields
[2];
94 u8 instruction_buf
= instruction
;
96 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
98 jtag_add_end_state(TAP_PD
);
99 arm_jtag_scann(jtag_info
, 0xf);
100 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
102 fields
[0].device
= jtag_info
->chain_pos
;
103 fields
[0].num_bits
= 1;
104 fields
[0].out_value
= &instruction_buf
;
105 fields
[0].out_mask
= NULL
;
106 fields
[0].in_value
= NULL
;
107 fields
[0].in_check_value
= NULL
;
108 fields
[0].in_check_mask
= NULL
;
109 fields
[0].in_handler
= NULL
;
110 fields
[0].in_handler_priv
= NULL
;
112 fields
[1].device
= jtag_info
->chain_pos
;
113 fields
[1].num_bits
= 32;
114 fields
[1].out_value
= out_buf
;
115 fields
[1].out_mask
= NULL
;
116 fields
[1].in_value
= NULL
;
119 fields
[1].in_handler
= arm_jtag_buf_to_u32_flip
;
120 fields
[1].in_handler_priv
= in
;
123 fields
[1].in_handler
= NULL
;
124 fields
[1].in_handler_priv
= NULL
;
126 fields
[1].in_check_value
= NULL
;
127 fields
[1].in_check_mask
= NULL
;
129 jtag_add_dr_scan(2, fields
, -1);
132 jtag_add_runtest(0, -1);
134 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
135 jtag_execute_queue();
138 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
140 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
142 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
148 int arm720t_read_cp15(target_t
*target
, u32 opcode
, u32
*value
)
150 /* fetch CP15 opcode */
151 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
153 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
154 /* "EXECUTE" stage (1) */
155 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
156 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
157 /* "EXECUTE" stage (2) */
158 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
159 /* "EXECUTE" stage (3), CDATA is read */
160 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
165 int arm720t_write_cp15(target_t
*target
, u32 opcode
, u32 value
)
167 /* fetch CP15 opcode */
168 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
170 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
171 /* "EXECUTE" stage (1) */
172 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
173 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
174 /* "EXECUTE" stage (2) */
175 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
176 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
181 u32
arm720t_get_ttb(target_t
*target
)
185 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
186 jtag_execute_queue();
193 void arm720t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
197 /* read cp15 control register */
198 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
199 jtag_execute_queue();
202 cp15_control
&= ~0x1U
;
204 if (d_u_cache
|| i_cache
)
205 cp15_control
&= ~0x4U
;
207 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
210 void arm720t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
214 /* read cp15 control register */
215 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
216 jtag_execute_queue();
219 cp15_control
|= 0x1U
;
221 if (d_u_cache
|| i_cache
)
222 cp15_control
|= 0x4U
;
224 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
227 void arm720t_post_debug_entry(target_t
*target
)
229 armv4_5_common_t
*armv4_5
= target
->arch_info
;
230 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
231 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
232 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
234 /* examine cp15 control reg */
235 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
236 jtag_execute_queue();
237 LOG_DEBUG("cp15_control_reg: %8.8x", arm720t
->cp15_control_reg
);
239 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
240 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
241 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
243 /* save i/d fault status and address register */
244 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
245 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
246 jtag_execute_queue();
249 void arm720t_pre_restore_context(target_t
*target
)
251 armv4_5_common_t
*armv4_5
= target
->arch_info
;
252 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
253 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
254 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
256 /* restore i/d fault status and address register */
257 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
258 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
261 int arm720t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm7tdmi_common_t
**arm7tdmi_p
, arm720t_common_t
**arm720t_p
)
263 armv4_5_common_t
*armv4_5
= target
->arch_info
;
264 arm7_9_common_t
*arm7_9
;
265 arm7tdmi_common_t
*arm7tdmi
;
266 arm720t_common_t
*arm720t
;
268 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
273 arm7_9
= armv4_5
->arch_info
;
274 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
279 arm7tdmi
= arm7_9
->arch_info
;
280 if (arm7tdmi
->common_magic
!= ARM7TDMI_COMMON_MAGIC
)
285 arm720t
= arm7tdmi
->arch_info
;
286 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
)
291 *armv4_5_p
= armv4_5
;
293 *arm7tdmi_p
= arm7tdmi
;
294 *arm720t_p
= arm720t
;
299 int arm720t_arch_state(struct target_s
*target
)
301 armv4_5_common_t
*armv4_5
= target
->arch_info
;
302 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
303 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
304 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
308 "disabled", "enabled"
311 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
313 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
317 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
318 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
319 "MMU: %s, Cache: %s",
320 armv4_5_state_strings
[armv4_5
->core_state
],
321 target_debug_reason_strings
[target
->debug_reason
],
322 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
323 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
324 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
325 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
326 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
331 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
334 armv4_5_common_t
*armv4_5
= target
->arch_info
;
335 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
336 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
337 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
339 /* disable cache, but leave MMU enabled */
340 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
341 arm720t_disable_mmu_caches(target
, 0, 1, 0);
343 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
345 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
346 arm720t_enable_mmu_caches(target
, 0, 1, 0);
351 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
355 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
361 int arm720t_soft_reset_halt(struct target_s
*target
)
363 armv4_5_common_t
*armv4_5
= target
->arch_info
;
364 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
365 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
366 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
368 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
370 target
->type
->halt(target
);
374 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
376 embeddedice_read_reg(dbg_stat
);
377 jtag_execute_queue();
382 /* do not eat all CPU, time out after 1 se*/
387 LOG_ERROR("Failed to halt CPU after 1 sec");
388 return ERROR_TARGET_TIMEOUT
;
391 target
->state
= TARGET_HALTED
;
393 /* SVC, ARM state, IRQ and FIQ disabled */
394 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
395 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
396 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
398 /* start fetching from 0x0 */
399 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
400 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
401 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
403 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
404 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
406 arm720t_disable_mmu_caches(target
, 1, 1, 1);
407 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
408 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
409 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
411 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
416 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
418 arm7tdmi_init_target(cmd_ctx
, target
);
430 int arm720t_init_arch_info(target_t
*target
, arm720t_common_t
*arm720t
, int chain_pos
, char *variant
)
432 arm7tdmi_common_t
*arm7tdmi
= &arm720t
->arm7tdmi_common
;
433 arm7_9_common_t
*arm7_9
= &arm7tdmi
->arm7_9_common
;
435 arm7tdmi_init_arch_info(target
, arm7tdmi
, chain_pos
, variant
);
437 arm7tdmi
->arch_info
= arm720t
;
438 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
440 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
441 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
443 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
444 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
445 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
446 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
447 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
448 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
449 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
450 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
455 int arm720t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
458 char *variant
= NULL
;
459 arm720t_common_t
*arm720t
= malloc(sizeof(arm720t_common_t
));
460 memset(arm720t
, 0, sizeof(*arm720t
));
464 LOG_ERROR("'target arm720t' requires at least one additional argument");
468 chain_pos
= strtoul(args
[3], NULL
, 0);
473 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
475 arm720t_init_arch_info(target
, arm720t
, chain_pos
, variant
);
480 int arm720t_register_commands(struct command_context_s
*cmd_ctx
)
483 command_t
*arm720t_cmd
;
486 retval
= arm7tdmi_register_commands(cmd_ctx
);
488 arm720t_cmd
= register_command(cmd_ctx
, NULL
, "arm720t", NULL
, COMMAND_ANY
, "arm720t specific commands");
490 register_command(cmd_ctx
, arm720t_cmd
, "cp15", arm720t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode> [value]");
491 register_command(cmd_ctx
, arm720t_cmd
, "virt2phys", arm720t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
493 register_command(cmd_ctx
, arm720t_cmd
, "mdw_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
494 register_command(cmd_ctx
, arm720t_cmd
, "mdh_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
495 register_command(cmd_ctx
, arm720t_cmd
, "mdb_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
497 register_command(cmd_ctx
, arm720t_cmd
, "mww_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
498 register_command(cmd_ctx
, arm720t_cmd
, "mwh_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
499 register_command(cmd_ctx
, arm720t_cmd
, "mwb_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
504 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
507 target_t
*target
= get_current_target(cmd_ctx
);
508 armv4_5_common_t
*armv4_5
;
509 arm7_9_common_t
*arm7_9
;
510 arm7tdmi_common_t
*arm7tdmi
;
511 arm720t_common_t
*arm720t
;
512 arm_jtag_t
*jtag_info
;
514 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
516 command_print(cmd_ctx
, "current target isn't an ARM720t target");
520 jtag_info
= &arm7_9
->jtag_info
;
522 if (target
->state
!= TARGET_HALTED
)
524 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
528 /* one or more argument, access a single register (write if second argument is given */
531 u32 opcode
= strtoul(args
[0], NULL
, 0);
536 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
538 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
541 jtag_execute_queue();
543 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
547 u32 value
= strtoul(args
[1], NULL
, 0);
548 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
550 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
553 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
560 int arm720t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
562 target_t
*target
= get_current_target(cmd_ctx
);
563 armv4_5_common_t
*armv4_5
;
564 arm7_9_common_t
*arm7_9
;
565 arm7tdmi_common_t
*arm7tdmi
;
566 arm720t_common_t
*arm720t
;
567 arm_jtag_t
*jtag_info
;
569 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
571 command_print(cmd_ctx
, "current target isn't an ARM720t target");
575 jtag_info
= &arm7_9
->jtag_info
;
577 if (target
->state
!= TARGET_HALTED
)
579 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
583 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
586 int arm720t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
588 target_t
*target
= get_current_target(cmd_ctx
);
589 armv4_5_common_t
*armv4_5
;
590 arm7_9_common_t
*arm7_9
;
591 arm7tdmi_common_t
*arm7tdmi
;
592 arm720t_common_t
*arm720t
;
593 arm_jtag_t
*jtag_info
;
595 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
597 command_print(cmd_ctx
, "current target isn't an ARM720t target");
601 jtag_info
= &arm7_9
->jtag_info
;
603 if (target
->state
!= TARGET_HALTED
)
605 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
609 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
612 int arm720t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
614 target_t
*target
= get_current_target(cmd_ctx
);
615 armv4_5_common_t
*armv4_5
;
616 arm7_9_common_t
*arm7_9
;
617 arm7tdmi_common_t
*arm7tdmi
;
618 arm720t_common_t
*arm720t
;
619 arm_jtag_t
*jtag_info
;
621 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
623 command_print(cmd_ctx
, "current target isn't an ARM720t target");
627 jtag_info
= &arm7_9
->jtag_info
;
629 if (target
->state
!= TARGET_HALTED
)
631 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
635 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
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