src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm720t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27 #include "time_support.h"
  28
  29 #include <stdlib.h>
  30 #include <string.h>
  31
  32 #if 0
  33 #define _DEBUG_INSTRUCTION_EXECUTION_
  34 #endif
  35
  36 /* cli handling */
  37 int arm720t_register_commands(struct command_context_s *cmd_ctx);
  38
  39 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 /* forward declarations */
  45 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  46 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  47 int arm720t_quit(void);
  48 int arm720t_arch_state(struct target_s *target);
  49 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  50 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  51 int arm720t_soft_reset_halt(struct target_s *target);
  52
  53 target_type_t arm720t_target =
  54 {
  55         .name = "arm720t",
  56
  57         .poll = arm7_9_poll,
  58         .arch_state = arm720t_arch_state,
  59
  60         .halt = arm7_9_halt,
  61         .resume = arm7_9_resume,
  62         .step = arm7_9_step,
  63
  64         .assert_reset = arm7_9_assert_reset,
  65         .deassert_reset = arm7_9_deassert_reset,
  66         .soft_reset_halt = arm720t_soft_reset_halt,
  67
  68         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  69
  70         .read_memory = arm720t_read_memory,
  71         .write_memory = arm720t_write_memory,
  72         .bulk_write_memory = arm7_9_bulk_write_memory,
  73         .checksum_memory = arm7_9_checksum_memory,
  74         .blank_check_memory = arm7_9_blank_check_memory,
  75
  76         .run_algorithm = armv4_5_run_algorithm,
  77
  78         .add_breakpoint = arm7_9_add_breakpoint,
  79         .remove_breakpoint = arm7_9_remove_breakpoint,
  80         .add_watchpoint = arm7_9_add_watchpoint,
  81         .remove_watchpoint = arm7_9_remove_watchpoint,
  82
  83         .register_commands = arm720t_register_commands,
  84         .target_command = arm720t_target_command,
  85         .init_target = arm720t_init_target,
  86         .examine = arm7tdmi_examine,
  87         .quit = arm720t_quit
  88 };
  89
  90 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
  91 {
  92         armv4_5_common_t *armv4_5 = target->arch_info;
  93         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  94         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  95         scan_field_t fields[2];
  96         u8 out_buf[4];
  97         u8 instruction_buf = instruction;
  98
  99         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 100
 101         jtag_add_end_state(TAP_PD);
 102         arm_jtag_scann(jtag_info, 0xf);
 103         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 104
 105         fields[0].device = jtag_info->chain_pos;
 106         fields[0].num_bits = 1;
 107         fields[0].out_value = &instruction_buf;
 108         fields[0].out_mask = NULL;
 109         fields[0].in_value = NULL;
 110         fields[0].in_check_value = NULL;
 111         fields[0].in_check_mask = NULL;
 112         fields[0].in_handler = NULL;
 113         fields[0].in_handler_priv = NULL;
 114
 115         fields[1].device = jtag_info->chain_pos;
 116         fields[1].num_bits = 32;
 117         fields[1].out_value = out_buf;
 118         fields[1].out_mask = NULL;
 119         fields[1].in_value = NULL;
 120         if (in)
 121         {
 122                 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
 123                 fields[1].in_handler_priv = in;
 124         } else
 125         {
 126                 fields[1].in_handler = NULL;
 127                 fields[1].in_handler_priv = NULL;
 128         }
 129         fields[1].in_check_value = NULL;
 130         fields[1].in_check_mask = NULL;
 131
 132         jtag_add_dr_scan(2, fields, -1);
 133
 134         if (clock)
 135                 jtag_add_runtest(0, -1);
 136
 137 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 138         jtag_execute_queue();
 139
 140         if (in)
 141                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 142         else
 143                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 144 #else
 145                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 146 #endif
 147
 148         return ERROR_OK;
 149 }
 150
 151 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
 152 {
 153         /* fetch CP15 opcode */
 154         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 155         /* "DECODE" stage */
 156         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 157         /* "EXECUTE" stage (1) */
 158         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 159         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 160         /* "EXECUTE" stage (2) */
 161         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 162         /* "EXECUTE" stage (3), CDATA is read */
 163         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 164
 165         return ERROR_OK;
 166 }
 167
 168 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
 169 {
 170         /* fetch CP15 opcode */
 171         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 172         /* "DECODE" stage */
 173         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 174         /* "EXECUTE" stage (1) */
 175         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 176         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 177         /* "EXECUTE" stage (2) */
 178         arm720t_scan_cp15(target, value, NULL, 0, 1);
 179         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 180
 181         return ERROR_OK;
 182 }
 183
 184 u32 arm720t_get_ttb(target_t *target)
 185 {
 186         u32 ttb = 0x0;
 187
 188         arm720t_read_cp15(target, 0xee120f10, &ttb);
 189         jtag_execute_queue();
 190
 191         ttb &= 0xffffc000;
 192
 193         return ttb;
 194 }
 195
 196 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 197 {
 198         u32 cp15_control;
 199
 200         /* read cp15 control register */
 201         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 202         jtag_execute_queue();
 203
 204         if (mmu)
 205                 cp15_control &= ~0x1U;
 206
 207         if (d_u_cache || i_cache)
 208                 cp15_control &= ~0x4U;
 209
 210         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 211 }
 212
 213 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 214 {
 215         u32 cp15_control;
 216
 217         /* read cp15 control register */
 218         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 219         jtag_execute_queue();
 220
 221         if (mmu)
 222                 cp15_control |= 0x1U;
 223
 224         if (d_u_cache || i_cache)
 225                 cp15_control |= 0x4U;
 226
 227         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 228 }
 229
 230 void arm720t_post_debug_entry(target_t *target)
 231 {
 232         armv4_5_common_t *armv4_5 = target->arch_info;
 233         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 234         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 235         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 236
 237         /* examine cp15 control reg */
 238         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 239         jtag_execute_queue();
 240         LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
 241
 242         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 243         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 244         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 245
 246         /* save i/d fault status and address register */
 247         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 248         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 249         jtag_execute_queue();
 250 }
 251
 252 void arm720t_pre_restore_context(target_t *target)
 253 {
 254         armv4_5_common_t *armv4_5 = target->arch_info;
 255         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 256         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 257         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 258
 259         /* restore i/d fault status and address register */
 260         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 261         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 262 }
 263
 264 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
 265 {
 266         armv4_5_common_t *armv4_5 = target->arch_info;
 267         arm7_9_common_t *arm7_9;
 268         arm7tdmi_common_t *arm7tdmi;
 269         arm720t_common_t *arm720t;
 270
 271         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 272         {
 273                 return -1;
 274         }
 275
 276         arm7_9 = armv4_5->arch_info;
 277         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 278         {
 279                 return -1;
 280         }
 281
 282         arm7tdmi = arm7_9->arch_info;
 283         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
 284         {
 285                 return -1;
 286         }
 287
 288         arm720t = arm7tdmi->arch_info;
 289         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
 290         {
 291                 return -1;
 292         }
 293
 294         *armv4_5_p = armv4_5;
 295         *arm7_9_p = arm7_9;
 296         *arm7tdmi_p = arm7tdmi;
 297         *arm720t_p = arm720t;
 298
 299         return ERROR_OK;
 300 }
 301
 302 int arm720t_arch_state(struct target_s *target)
 303 {
 304         armv4_5_common_t *armv4_5 = target->arch_info;
 305         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 306         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 307         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 308
 309         char *state[] =
 310         {
 311                 "disabled", "enabled"
 312         };
 313
 314         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 315         {
 316                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 317                 exit(-1);
 318         }
 319
 320         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 321                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 322                         "MMU: %s, Cache: %s",
 323                          armv4_5_state_strings[armv4_5->core_state],
 324                          Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
 325                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 326                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 327                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 328                          state[arm720t->armv4_5_mmu.mmu_enabled],
 329                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 330
 331         return ERROR_OK;
 332 }
 333
 334 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 335 {
 336         int retval;
 337         armv4_5_common_t *armv4_5 = target->arch_info;
 338         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 339         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 340         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 341
 342         /* disable cache, but leave MMU enabled */
 343         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 344                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 345
 346         retval = arm7_9_read_memory(target, address, size, count, buffer);
 347
 348         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 349                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 350
 351         return retval;
 352 }
 353
 354 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 355 {
 356         int retval;
 357
 358         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 359                 return retval;
 360
 361         return retval;
 362 }
 363
 364 int arm720t_soft_reset_halt(struct target_s *target)
 365 {
 366         armv4_5_common_t *armv4_5 = target->arch_info;
 367         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 368         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 369         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 370         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 371
 372         target_halt(target);
 373
 374         long long then=timeval_ms();
 375         int timeout;
 376         while (!(timeout=((timeval_ms()-then)>1000)))
 377         {
 378                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 379                 {
 380                         embeddedice_read_reg(dbg_stat);
 381                         jtag_execute_queue();
 382                 } else
 383                 {
 384                         break;
 385                 }
 386                 if (debug_level>=3)
 387                 {
 388                         alive_sleep(100);
 389                 } else
 390                 {
 391                         keep_alive();
 392                 }
 393         }
 394         if (timeout)
 395         {
 396                 LOG_ERROR("Failed to halt CPU after 1 sec");
 397                 return ERROR_TARGET_TIMEOUT;
 398         }
 399
 400         target->state = TARGET_HALTED;
 401
 402         /* SVC, ARM state, IRQ and FIQ disabled */
 403         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 404         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 405         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 406
 407         /* start fetching from 0x0 */
 408         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 409         armv4_5->core_cache->reg_list[15].dirty = 1;
 410         armv4_5->core_cache->reg_list[15].valid = 1;
 411
 412         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 413         armv4_5->core_state = ARMV4_5_STATE_ARM;
 414
 415         arm720t_disable_mmu_caches(target, 1, 1, 1);
 416         arm720t->armv4_5_mmu.mmu_enabled = 0;
 417         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 418         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 419
 420         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 421
 422         return ERROR_OK;
 423 }
 424
 425 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 426 {
 427         arm7tdmi_init_target(cmd_ctx, target);
 428
 429         return ERROR_OK;
 430
 431 }
 432
 433 int arm720t_quit(void)
 434 {
 435
 436         return ERROR_OK;
 437 }
 438
 439 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant)
 440 {
 441         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 442         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 443
 444         arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
 445
 446         arm7tdmi->arch_info = arm720t;
 447         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 448
 449         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 450         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 451
 452         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 453         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 454         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 455         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 456         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 457         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 458         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 459         arm720t->armv4_5_mmu.mmu_enabled = 0;
 460
 461         return ERROR_OK;
 462 }
 463
 464 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 465 {
 466         int chain_pos;
 467         char *variant = NULL;
 468         arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));
 469         memset(arm720t, 0, sizeof(*arm720t));
 470
 471         if (argc < 4)
 472         {
 473                 LOG_ERROR("'target arm720t' requires at least one additional argument");
 474                 exit(-1);
 475         }
 476
 477         chain_pos = strtoul(args[3], NULL, 0);
 478
 479         if (argc >= 5)
 480                 variant = args[4];
 481
 482         LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 483
 484         arm720t_init_arch_info(target, arm720t, chain_pos, variant);
 485
 486         return ERROR_OK;
 487 }
 488
 489 int arm720t_register_commands(struct command_context_s *cmd_ctx)
 490 {
 491         int retval;
 492         command_t *arm720t_cmd;
 493
 494
 495         retval = arm7tdmi_register_commands(cmd_ctx);
 496
 497         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 498
 499         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
 500         register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 501
 502         register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 503         register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 504         register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 505
 506         register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 507         register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 508         register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 509
 510         return ERROR_OK;
 511 }
 512
 513 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 514 {
 515         int retval;
 516         target_t *target = get_current_target(cmd_ctx);
 517         armv4_5_common_t *armv4_5;
 518         arm7_9_common_t *arm7_9;
 519         arm7tdmi_common_t *arm7tdmi;
 520         arm720t_common_t *arm720t;
 521         arm_jtag_t *jtag_info;
 522
 523         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 524         {
 525                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 526                 return ERROR_OK;
 527         }
 528
 529         jtag_info = &arm7_9->jtag_info;
 530
 531         if (target->state != TARGET_HALTED)
 532         {
 533                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 534                 return ERROR_OK;
 535         }
 536
 537         /* one or more argument, access a single register (write if second argument is given */
 538         if (argc >= 1)
 539         {
 540                 u32 opcode = strtoul(args[0], NULL, 0);
 541
 542                 if (argc == 1)
 543                 {
 544                         u32 value;
 545                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 546                         {
 547                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 548                                 return ERROR_OK;
 549                         }
 550                         jtag_execute_queue();
 551
 552                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 553                 }
 554                 else if (argc == 2)
 555                 {
 556                         u32 value = strtoul(args[1], NULL, 0);
 557                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 558                         {
 559                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 560                                 return ERROR_OK;
 561                         }
 562                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 563                 }
 564         }
 565
 566         return ERROR_OK;
 567 }
 568
 569 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 570 {
 571         target_t *target = get_current_target(cmd_ctx);
 572         armv4_5_common_t *armv4_5;
 573         arm7_9_common_t *arm7_9;
 574         arm7tdmi_common_t *arm7tdmi;
 575         arm720t_common_t *arm720t;
 576         arm_jtag_t *jtag_info;
 577
 578         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 579         {
 580                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 581                 return ERROR_OK;
 582         }
 583
 584         jtag_info = &arm7_9->jtag_info;
 585
 586         if (target->state != TARGET_HALTED)
 587         {
 588                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 589                 return ERROR_OK;
 590         }
 591
 592         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 593 }
 594
 595 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 596 {
 597         target_t *target = get_current_target(cmd_ctx);
 598         armv4_5_common_t *armv4_5;
 599         arm7_9_common_t *arm7_9;
 600         arm7tdmi_common_t *arm7tdmi;
 601         arm720t_common_t *arm720t;
 602         arm_jtag_t *jtag_info;
 603
 604         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 605         {
 606                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 607                 return ERROR_OK;
 608         }
 609
 610         jtag_info = &arm7_9->jtag_info;
 611
 612         if (target->state != TARGET_HALTED)
 613         {
 614                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 615                 return ERROR_OK;
 616         }
 617
 618         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 619 }
 620
 621 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 622 {
 623         target_t *target = get_current_target(cmd_ctx);
 624         armv4_5_common_t *armv4_5;
 625         arm7_9_common_t *arm7_9;
 626         arm7tdmi_common_t *arm7tdmi;
 627         arm720t_common_t *arm720t;
 628         arm_jtag_t *jtag_info;
 629
 630         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 631         {
 632                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 633                 return ERROR_OK;
 634         }
 635
 636         jtag_info = &arm7_9->jtag_info;
 637
 638         if (target->state != TARGET_HALTED)
 639         {
 640                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 641                 return ERROR_OK;
 642         }
 643
 644         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 645 }
 646