src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm720t.h"
  25 #include "time_support.h"
  26 #include "target_type.h"
  27
  28
  29 #if 0
  30 #define _DEBUG_INSTRUCTION_EXECUTION_
  31 #endif
  32
  33 /* cli handling */
  34 int arm720t_register_commands(struct command_context_s *cmd_ctx);
  35
  36 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37
  38 /* forward declarations */
  39 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
  40 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  41 int arm720t_quit(void);
  42 int arm720t_arch_state(struct target_s *target);
  43 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  44 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  45 int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  46 int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  47 int arm720t_soft_reset_halt(struct target_s *target);
  48
  49 target_type_t arm720t_target =
  50 {
  51         .name = "arm720t",
  52
  53         .poll = arm7_9_poll,
  54         .arch_state = arm720t_arch_state,
  55
  56         .halt = arm7_9_halt,
  57         .resume = arm7_9_resume,
  58         .step = arm7_9_step,
  59
  60         .assert_reset = arm7_9_assert_reset,
  61         .deassert_reset = arm7_9_deassert_reset,
  62         .soft_reset_halt = arm720t_soft_reset_halt,
  63
  64         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  65
  66         .read_memory = arm720t_read_memory,
  67         .write_memory = arm720t_write_memory,
  68         .read_phys_memory = arm720t_read_phys_memory,
  69         .write_phys_memory = arm720t_write_phys_memory,
  70         .bulk_write_memory = arm7_9_bulk_write_memory,
  71         .checksum_memory = arm7_9_checksum_memory,
  72         .blank_check_memory = arm7_9_blank_check_memory,
  73
  74         .run_algorithm = armv4_5_run_algorithm,
  75
  76         .add_breakpoint = arm7_9_add_breakpoint,
  77         .remove_breakpoint = arm7_9_remove_breakpoint,
  78         .add_watchpoint = arm7_9_add_watchpoint,
  79         .remove_watchpoint = arm7_9_remove_watchpoint,
  80
  81         .register_commands = arm720t_register_commands,
  82         .target_create = arm720t_target_create,
  83         .init_target = arm720t_init_target,
  84         .examine = arm7tdmi_examine,
  85         .quit = arm720t_quit
  86
  87 };
  88
  89 int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
  90 {
  91         int retval = ERROR_OK;
  92         armv4_5_common_t *armv4_5 = target->arch_info;
  93         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  94         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  95         scan_field_t fields[2];
  96         uint8_t out_buf[4];
  97         uint8_t instruction_buf = instruction;
  98
  99         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 100
 101         jtag_set_end_state(TAP_DRPAUSE);
 102         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 103         {
 104                 return retval;
 105         }
 106         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
 107         {
 108                 return retval;
 109         }
 110
 111         fields[0].tap = jtag_info->tap;
 112         fields[0].num_bits = 1;
 113         fields[0].out_value = &instruction_buf;
 114         fields[0].in_value = NULL;
 115
 116         fields[1].tap = jtag_info->tap;
 117         fields[1].num_bits = 32;
 118         fields[1].out_value = out_buf;
 119         fields[1].in_value = NULL;
 120
 121         if (in)
 122         {
 123                 fields[1].in_value = (uint8_t *)in;
 124                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 125                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 126         } else
 127         {
 128                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 129         }
 130
 131         if (clock)
 132                 jtag_add_runtest(0, jtag_get_end_state());
 133
 134 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 135         if ((retval = jtag_execute_queue()) != ERROR_OK)
 136         {
 137                 return retval;
 138         }
 139
 140         if (in)
 141                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 142         else
 143                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 144 #else
 145                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 146 #endif
 147
 148         return ERROR_OK;
 149 }
 150
 151 int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
 152 {
 153         /* fetch CP15 opcode */
 154         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 155         /* "DECODE" stage */
 156         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 157         /* "EXECUTE" stage (1) */
 158         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 159         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 160         /* "EXECUTE" stage (2) */
 161         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 162         /* "EXECUTE" stage (3), CDATA is read */
 163         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 164
 165         return ERROR_OK;
 166 }
 167
 168 int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
 169 {
 170         /* fetch CP15 opcode */
 171         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 172         /* "DECODE" stage */
 173         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 174         /* "EXECUTE" stage (1) */
 175         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 176         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 177         /* "EXECUTE" stage (2) */
 178         arm720t_scan_cp15(target, value, NULL, 0, 1);
 179         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 180
 181         return ERROR_OK;
 182 }
 183
 184 uint32_t arm720t_get_ttb(target_t *target)
 185 {
 186         uint32_t ttb = 0x0;
 187
 188         arm720t_read_cp15(target, 0xee120f10, &ttb);
 189         jtag_execute_queue();
 190
 191         ttb &= 0xffffc000;
 192
 193         return ttb;
 194 }
 195
 196 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 197 {
 198         uint32_t cp15_control;
 199
 200         /* read cp15 control register */
 201         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 202         jtag_execute_queue();
 203
 204         if (mmu)
 205                 cp15_control &= ~0x1U;
 206
 207         if (d_u_cache || i_cache)
 208                 cp15_control &= ~0x4U;
 209
 210         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 211 }
 212
 213 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 214 {
 215         uint32_t cp15_control;
 216
 217         /* read cp15 control register */
 218         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 219         jtag_execute_queue();
 220
 221         if (mmu)
 222                 cp15_control |= 0x1U;
 223
 224         if (d_u_cache || i_cache)
 225                 cp15_control |= 0x4U;
 226
 227         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 228 }
 229
 230 void arm720t_post_debug_entry(target_t *target)
 231 {
 232         armv4_5_common_t *armv4_5 = target->arch_info;
 233         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 234         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 235         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 236
 237         /* examine cp15 control reg */
 238         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 239         jtag_execute_queue();
 240         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 241
 242         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 243         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 244         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 245
 246         /* save i/d fault status and address register */
 247         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 248         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 249         jtag_execute_queue();
 250 }
 251
 252 void arm720t_pre_restore_context(target_t *target)
 253 {
 254         armv4_5_common_t *armv4_5 = target->arch_info;
 255         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 256         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 257         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 258
 259         /* restore i/d fault status and address register */
 260         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 261         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 262 }
 263
 264 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
 265 {
 266         armv4_5_common_t *armv4_5 = target->arch_info;
 267         arm7_9_common_t *arm7_9;
 268         arm7tdmi_common_t *arm7tdmi;
 269         arm720t_common_t *arm720t;
 270
 271         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 272         {
 273                 return -1;
 274         }
 275
 276         arm7_9 = armv4_5->arch_info;
 277         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 278         {
 279                 return -1;
 280         }
 281
 282         arm7tdmi = arm7_9->arch_info;
 283         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
 284         {
 285                 return -1;
 286         }
 287
 288         arm720t = arm7tdmi->arch_info;
 289         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
 290         {
 291                 return -1;
 292         }
 293
 294         *armv4_5_p = armv4_5;
 295         *arm7_9_p = arm7_9;
 296         *arm7tdmi_p = arm7tdmi;
 297         *arm720t_p = arm720t;
 298
 299         return ERROR_OK;
 300 }
 301
 302 int arm720t_arch_state(struct target_s *target)
 303 {
 304         armv4_5_common_t *armv4_5 = target->arch_info;
 305         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 306         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 307         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 308
 309         char *state[] =
 310         {
 311                 "disabled", "enabled"
 312         };
 313
 314         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 315         {
 316                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 317                 exit(-1);
 318         }
 319
 320         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 321                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 322                         "MMU: %s, Cache: %s",
 323                          armv4_5_state_strings[armv4_5->core_state],
 324                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 325                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 326                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 327                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 328                          state[arm720t->armv4_5_mmu.mmu_enabled],
 329                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 330
 331         return ERROR_OK;
 332 }
 333
 334 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 335 {
 336         int retval;
 337         armv4_5_common_t *armv4_5 = target->arch_info;
 338         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 339         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 340         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 341
 342         /* disable cache, but leave MMU enabled */
 343         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 344                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 345
 346         retval = arm7_9_read_memory(target, address, size, count, buffer);
 347
 348         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 349                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 350
 351         return retval;
 352 }
 353
 354 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 355 {
 356         int retval;
 357
 358         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 359                 return retval;
 360
 361         return retval;
 362 }
 363
 364
 365 int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 366 {
 367         armv4_5_common_t *armv4_5 = target->arch_info;
 368         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 369         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 370         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 371
 372         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 373 }
 374
 375 int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 376 {
 377         armv4_5_common_t *armv4_5 = target->arch_info;
 378         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 379         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 380         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 381
 382         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 383 }
 384
 385
 386 int arm720t_soft_reset_halt(struct target_s *target)
 387 {
 388         int retval = ERROR_OK;
 389         armv4_5_common_t *armv4_5 = target->arch_info;
 390         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 391         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 392         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 393         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 394
 395         if ((retval = target_halt(target)) != ERROR_OK)
 396         {
 397                 return retval;
 398         }
 399
 400         long long then = timeval_ms();
 401         int timeout;
 402         while (!(timeout = ((timeval_ms()-then) > 1000)))
 403         {
 404                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 405                 {
 406                         embeddedice_read_reg(dbg_stat);
 407                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 408                         {
 409                                 return retval;
 410                         }
 411                 } else
 412                 {
 413                         break;
 414                 }
 415                 if (debug_level >= 3)
 416                 {
 417                         alive_sleep(100);
 418                 } else
 419                 {
 420                         keep_alive();
 421                 }
 422         }
 423         if (timeout)
 424         {
 425                 LOG_ERROR("Failed to halt CPU after 1 sec");
 426                 return ERROR_TARGET_TIMEOUT;
 427         }
 428
 429         target->state = TARGET_HALTED;
 430
 431         /* SVC, ARM state, IRQ and FIQ disabled */
 432         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 433         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 434         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 435
 436         /* start fetching from 0x0 */
 437         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 438         armv4_5->core_cache->reg_list[15].dirty = 1;
 439         armv4_5->core_cache->reg_list[15].valid = 1;
 440
 441         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 442         armv4_5->core_state = ARMV4_5_STATE_ARM;
 443
 444         arm720t_disable_mmu_caches(target, 1, 1, 1);
 445         arm720t->armv4_5_mmu.mmu_enabled = 0;
 446         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 447         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 448
 449         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 450         {
 451                 return retval;
 452         }
 453
 454         return ERROR_OK;
 455 }
 456
 457 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 458 {
 459         arm7tdmi_init_target(cmd_ctx, target);
 460
 461         return ERROR_OK;
 462 }
 463
 464 int arm720t_quit(void)
 465 {
 466         return ERROR_OK;
 467 }
 468
 469 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
 470 {
 471         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 472         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 473
 474         arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 475
 476         arm7tdmi->arch_info = arm720t;
 477         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 478
 479         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 480         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 481
 482         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 483         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 484         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 485         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 486         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 487         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 488         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 489         arm720t->armv4_5_mmu.mmu_enabled = 0;
 490
 491         return ERROR_OK;
 492 }
 493
 494 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
 495 {
 496         arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
 497
 498         arm720t_init_arch_info(target, arm720t, target->tap);
 499
 500         return ERROR_OK;
 501 }
 502
 503 int arm720t_register_commands(struct command_context_s *cmd_ctx)
 504 {
 505         int retval;
 506         command_t *arm720t_cmd;
 507
 508
 509         retval = arm7tdmi_register_commands(cmd_ctx);
 510
 511         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 512
 513         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
 514
 515         return ERROR_OK;
 516 }
 517
 518 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 519 {
 520         int retval;
 521         target_t *target = get_current_target(cmd_ctx);
 522         armv4_5_common_t *armv4_5;
 523         arm7_9_common_t *arm7_9;
 524         arm7tdmi_common_t *arm7tdmi;
 525         arm720t_common_t *arm720t;
 526         arm_jtag_t *jtag_info;
 527
 528         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 529         {
 530                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 531                 return ERROR_OK;
 532         }
 533
 534         jtag_info = &arm7_9->jtag_info;
 535
 536         if (target->state != TARGET_HALTED)
 537         {
 538                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 539                 return ERROR_OK;
 540         }
 541
 542         /* one or more argument, access a single register (write if second argument is given */
 543         if (argc >= 1)
 544         {
 545                 uint32_t opcode = strtoul(args[0], NULL, 0);
 546
 547                 if (argc == 1)
 548                 {
 549                         uint32_t value;
 550                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 551                         {
 552                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 553                                 return ERROR_OK;
 554                         }
 555
 556                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 557                         {
 558                                 return retval;
 559                         }
 560
 561                         command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 562                 }
 563                 else if (argc == 2)
 564                 {
 565                         uint32_t value = strtoul(args[1], NULL, 0);
 566                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 567                         {
 568                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 569                                 return ERROR_OK;
 570                         }
 571                         command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 572                 }
 573         }
 574
 575         return ERROR_OK;
 576 }