src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include <helper/time_support.h>
  29 #include "target_type.h"
  30 #include "register.h"
  31 #include "arm_opcodes.h"
  32
  33
  34 /*
  35  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  36  * ARM DDI 0229C especially Chapter 9 about debug support.
  37  */
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static int arm720t_scan_cp15(struct target *target,
  44                 uint32_t out, uint32_t *in, int instruction, int clock)
  45 {
  46         int retval;
  47         struct arm720t_common *arm720t = target_to_arm720(target);
  48         struct arm_jtag *jtag_info;
  49         struct scan_field fields[2];
  50         uint8_t out_buf[4];
  51         uint8_t instruction_buf = instruction;
  52
  53         jtag_info = &arm720t->arm7_9_common.jtag_info;
  54
  55         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  56
  57         if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
  58         {
  59                 return retval;
  60         }
  61         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
  62         {
  63                 return retval;
  64         }
  65
  66         fields[0].num_bits = 1;
  67         fields[0].out_value = &instruction_buf;
  68         fields[0].in_value = NULL;
  69
  70         fields[1].num_bits = 32;
  71         fields[1].out_value = out_buf;
  72         fields[1].in_value = NULL;
  73
  74         if (in)
  75         {
  76                 fields[1].in_value = (uint8_t *)in;
  77                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  78                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  79         } else
  80         {
  81                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  82         }
  83
  84         if (clock)
  85                 jtag_add_runtest(0, TAP_DRPAUSE);
  86
  87 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  88         if ((retval = jtag_execute_queue()) != ERROR_OK)
  89         {
  90                 return retval;
  91         }
  92
  93         if (in)
  94                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  95         else
  96                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  97 #else
  98                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
  99 #endif
 100
 101         return ERROR_OK;
 102 }
 103
 104 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
 105 {
 106         /* fetch CP15 opcode */
 107         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 108         /* "DECODE" stage */
 109         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 110         /* "EXECUTE" stage (1) */
 111         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 112         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 113         /* "EXECUTE" stage (2) */
 114         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 115         /* "EXECUTE" stage (3), CDATA is read */
 116         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 117
 118         return ERROR_OK;
 119 }
 120
 121 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 122 {
 123         /* fetch CP15 opcode */
 124         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 125         /* "DECODE" stage */
 126         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 127         /* "EXECUTE" stage (1) */
 128         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 129         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 130         /* "EXECUTE" stage (2) */
 131         arm720t_scan_cp15(target, value, NULL, 0, 1);
 132         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 133
 134         return ERROR_OK;
 135 }
 136
 137 static uint32_t arm720t_get_ttb(struct target *target)
 138 {
 139         uint32_t ttb = 0x0;
 140
 141         arm720t_read_cp15(target, 0xee120f10, &ttb);
 142         jtag_execute_queue();
 143
 144         ttb &= 0xffffc000;
 145
 146         return ttb;
 147 }
 148
 149 static void arm720t_disable_mmu_caches(struct target *target,
 150                 int mmu, int d_u_cache, int i_cache)
 151 {
 152         uint32_t cp15_control;
 153
 154         /* read cp15 control register */
 155         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 156         jtag_execute_queue();
 157
 158         if (mmu)
 159                 cp15_control &= ~0x1U;
 160
 161         if (d_u_cache || i_cache)
 162                 cp15_control &= ~0x4U;
 163
 164         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 165 }
 166
 167 static void arm720t_enable_mmu_caches(struct target *target,
 168                 int mmu, int d_u_cache, int i_cache)
 169 {
 170         uint32_t cp15_control;
 171
 172         /* read cp15 control register */
 173         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 174         jtag_execute_queue();
 175
 176         if (mmu)
 177                 cp15_control |= 0x1U;
 178
 179         if (d_u_cache || i_cache)
 180                 cp15_control |= 0x4U;
 181
 182         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 183 }
 184
 185 static void arm720t_post_debug_entry(struct target *target)
 186 {
 187         struct arm720t_common *arm720t = target_to_arm720(target);
 188
 189         /* examine cp15 control reg */
 190         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 191         jtag_execute_queue();
 192         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 193
 194         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 195         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 196         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 197
 198         /* save i/d fault status and address register */
 199         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 200         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 201         jtag_execute_queue();
 202 }
 203
 204 static void arm720t_pre_restore_context(struct target *target)
 205 {
 206         struct arm720t_common *arm720t = target_to_arm720(target);
 207
 208         /* restore i/d fault status and address register */
 209         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 210         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 211 }
 212
 213 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 214                 struct arm720t_common *arm720t)
 215 {
 216         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 217                 command_print(cmd_ctx, "target is not an ARM720");
 218                 return ERROR_TARGET_INVALID;
 219         }
 220         return ERROR_OK;
 221 }
 222
 223 static int arm720t_arch_state(struct target *target)
 224 {
 225         struct arm720t_common *arm720t = target_to_arm720(target);
 226         struct arm *armv4_5;
 227
 228         static const char *state[] =
 229         {
 230                 "disabled", "enabled"
 231         };
 232
 233         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 234
 235         arm_arch_state(target);
 236         LOG_USER("MMU: %s, Cache: %s",
 237                          state[arm720t->armv4_5_mmu.mmu_enabled],
 238                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 239
 240         return ERROR_OK;
 241 }
 242
 243 static int arm720_mmu(struct target *target, int *enabled)
 244 {
 245         if (target->state != TARGET_HALTED) {
 246                 LOG_ERROR("%s: target not halted", __func__);
 247                 return ERROR_TARGET_INVALID;
 248         }
 249
 250         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 251         return ERROR_OK;
 252 }
 253
 254 static int arm720_virt2phys(struct target *target,
 255                 uint32_t virtual, uint32_t *physical)
 256 {
 257         uint32_t cb;
 258         struct arm720t_common *arm720t = target_to_arm720(target);
 259
 260         uint32_t ret;
 261         int retval = armv4_5_mmu_translate_va(target,
 262                         &arm720t->armv4_5_mmu, virtual, &cb, &ret);
 263         if (retval != ERROR_OK)
 264                 return retval;
 265         *physical = ret;
 266         return ERROR_OK;
 267 }
 268
 269 static int arm720t_read_memory(struct target *target,
 270                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 271 {
 272         int retval;
 273         struct arm720t_common *arm720t = target_to_arm720(target);
 274
 275         /* disable cache, but leave MMU enabled */
 276         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 277                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 278
 279         retval = arm7_9_read_memory(target, address, size, count, buffer);
 280
 281         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 282                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 283
 284         return retval;
 285 }
 286
 287 static int arm720t_read_phys_memory(struct target *target,
 288                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 289 {
 290         struct arm720t_common *arm720t = target_to_arm720(target);
 291
 292         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 293 }
 294
 295 static int arm720t_write_phys_memory(struct target *target,
 296                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 297 {
 298         struct arm720t_common *arm720t = target_to_arm720(target);
 299
 300         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 301 }
 302
 303 static int arm720t_soft_reset_halt(struct target *target)
 304 {
 305         int retval = ERROR_OK;
 306         struct arm720t_common *arm720t = target_to_arm720(target);
 307         struct reg *dbg_stat = &arm720t->arm7_9_common
 308                         .eice_cache->reg_list[EICE_DBG_STAT];
 309         struct arm *armv4_5 = &arm720t->arm7_9_common
 310                         .armv4_5_common;
 311
 312         if ((retval = target_halt(target)) != ERROR_OK)
 313         {
 314                 return retval;
 315         }
 316
 317         long long then = timeval_ms();
 318         int timeout;
 319         while (!(timeout = ((timeval_ms()-then) > 1000)))
 320         {
 321                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 322                 {
 323                         embeddedice_read_reg(dbg_stat);
 324                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 325                         {
 326                                 return retval;
 327                         }
 328                 } else
 329                 {
 330                         break;
 331                 }
 332                 if (debug_level >= 3)
 333                 {
 334                         alive_sleep(100);
 335                 } else
 336                 {
 337                         keep_alive();
 338                 }
 339         }
 340         if (timeout)
 341         {
 342                 LOG_ERROR("Failed to halt CPU after 1 sec");
 343                 return ERROR_TARGET_TIMEOUT;
 344         }
 345
 346         target->state = TARGET_HALTED;
 347
 348         /* SVC, ARM state, IRQ and FIQ disabled */
 349         uint32_t cpsr;
 350
 351         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 352         cpsr &= ~0xff;
 353         cpsr |= 0xd3;
 354         arm_set_cpsr(armv4_5, cpsr);
 355         armv4_5->cpsr->dirty = 1;
 356
 357         /* start fetching from 0x0 */
 358         buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
 359         armv4_5->pc->dirty = 1;
 360         armv4_5->pc->valid = 1;
 361
 362         arm720t_disable_mmu_caches(target, 1, 1, 1);
 363         arm720t->armv4_5_mmu.mmu_enabled = 0;
 364         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 365         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 366
 367         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 368         {
 369                 return retval;
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 376 {
 377         return arm7tdmi_init_target(cmd_ctx, target);
 378 }
 379
 380 /* FIXME remove forward decls */
 381 static int arm720t_mrc(struct target *target, int cpnum,
 382                 uint32_t op1, uint32_t op2,
 383                 uint32_t CRn, uint32_t CRm,
 384                 uint32_t *value);
 385 static int arm720t_mcr(struct target *target, int cpnum,
 386                 uint32_t op1, uint32_t op2,
 387                 uint32_t CRn, uint32_t CRm,
 388                 uint32_t value);
 389
 390 static int arm720t_init_arch_info(struct target *target,
 391                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 392 {
 393         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 394
 395         arm7_9->armv4_5_common.mrc = arm720t_mrc;
 396         arm7_9->armv4_5_common.mcr = arm720t_mcr;
 397
 398         arm7tdmi_init_arch_info(target, arm7_9, tap);
 399
 400         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 401
 402         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 403         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 404
 405         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 406         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 407         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 408         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 409         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 410         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 411         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 412         arm720t->armv4_5_mmu.mmu_enabled = 0;
 413
 414         return ERROR_OK;
 415 }
 416
 417 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 418 {
 419         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 420
 421         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
 422         return arm720t_init_arch_info(target, arm720t, target->tap);
 423 }
 424
 425 COMMAND_HANDLER(arm720t_handle_cp15_command)
 426 {
 427         int retval;
 428         struct target *target = get_current_target(CMD_CTX);
 429         struct arm720t_common *arm720t = target_to_arm720(target);
 430         struct arm_jtag *jtag_info;
 431
 432         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 433         if (retval != ERROR_OK)
 434                 return retval;
 435
 436         jtag_info = &arm720t->arm7_9_common.jtag_info;
 437
 438         if (target->state != TARGET_HALTED)
 439         {
 440                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 441                 return ERROR_OK;
 442         }
 443
 444         /* one or more argument, access a single register (write if second argument is given */
 445         if (CMD_ARGC >= 1)
 446         {
 447                 uint32_t opcode;
 448                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 449
 450                 if (CMD_ARGC == 1)
 451                 {
 452                         uint32_t value;
 453                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 454                         {
 455                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 456                                 return ERROR_OK;
 457                         }
 458
 459                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 460                         {
 461                                 return retval;
 462                         }
 463
 464                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 465                 }
 466                 else if (CMD_ARGC == 2)
 467                 {
 468                         uint32_t value;
 469                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 470
 471                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 472                         {
 473                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 474                                 return ERROR_OK;
 475                         }
 476                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 477                 }
 478         }
 479
 480         return ERROR_OK;
 481 }
 482
 483 static int arm720t_mrc(struct target *target, int cpnum,
 484                 uint32_t op1, uint32_t op2,
 485                 uint32_t CRn, uint32_t CRm,
 486                 uint32_t *value)
 487 {
 488         if (cpnum!=15)
 489         {
 490                 LOG_ERROR("Only cp15 is supported");
 491                 return ERROR_FAIL;
 492         }
 493
 494         /* read "to" r0 */
 495         return arm720t_read_cp15(target,
 496                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
 497                         value);
 498
 499 }
 500
 501 static int arm720t_mcr(struct target *target, int cpnum,
 502                 uint32_t op1, uint32_t op2,
 503                 uint32_t CRn, uint32_t CRm,
 504                 uint32_t value)
 505 {
 506         if (cpnum!=15)
 507         {
 508                 LOG_ERROR("Only cp15 is supported");
 509                 return ERROR_FAIL;
 510         }
 511
 512         /* write "from" r0 */
 513         return arm720t_write_cp15(target,
 514                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
 515                         value);
 516 }
 517
 518 static const struct command_registration arm720t_exec_command_handlers[] = {
 519         {
 520                 .name = "cp15",
 521                 .handler = arm720t_handle_cp15_command,
 522                 .mode = COMMAND_EXEC,
 523                 /* prefer using less error-prone "arm mcr" or "arm mrc" */
 524                 .help = "display/modify cp15 register using ARM opcode"
 525                         " (DEPRECATED)",
 526                 .usage = "instruction [value]",
 527         },
 528         COMMAND_REGISTRATION_DONE
 529 };
 530
 531 static const struct command_registration arm720t_command_handlers[] = {
 532         {
 533                 .chain = arm7_9_command_handlers,
 534         },
 535         {
 536                 .name = "arm720t",
 537                 .mode = COMMAND_ANY,
 538                 .help = "arm720t command group",
 539                 .chain = arm720t_exec_command_handlers,
 540         },
 541         COMMAND_REGISTRATION_DONE
 542 };
 543
 544 /** Holds methods for ARM720 targets. */
 545 struct target_type arm720t_target =
 546 {
 547         .name = "arm720t",
 548
 549         .poll = arm7_9_poll,
 550         .arch_state = arm720t_arch_state,
 551
 552         .halt = arm7_9_halt,
 553         .resume = arm7_9_resume,
 554         .step = arm7_9_step,
 555
 556         .assert_reset = arm7_9_assert_reset,
 557         .deassert_reset = arm7_9_deassert_reset,
 558         .soft_reset_halt = arm720t_soft_reset_halt,
 559
 560         .get_gdb_reg_list = arm_get_gdb_reg_list,
 561
 562         .read_memory = arm720t_read_memory,
 563         .write_memory = arm7_9_write_memory,
 564         .read_phys_memory = arm720t_read_phys_memory,
 565         .write_phys_memory = arm720t_write_phys_memory,
 566         .mmu = arm720_mmu,
 567         .virt2phys = arm720_virt2phys,
 568
 569         .bulk_write_memory = arm7_9_bulk_write_memory,
 570
 571         .checksum_memory = arm_checksum_memory,
 572         .blank_check_memory = arm_blank_check_memory,
 573
 574         .run_algorithm = armv4_5_run_algorithm,
 575
 576         .add_breakpoint = arm7_9_add_breakpoint,
 577         .remove_breakpoint = arm7_9_remove_breakpoint,
 578         .add_watchpoint = arm7_9_add_watchpoint,
 579         .remove_watchpoint = arm7_9_remove_watchpoint,
 580
 581         .commands = arm720t_command_handlers,
 582         .target_create = arm720t_target_create,
 583         .init_target = arm720t_init_target,
 584         .examine = arm7_9_examine,
 585         .check_reset = arm7_9_check_reset,
 586 };