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- fix issue when target is already halted
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "target_request.h"
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "jtag.h"
32 #include "log.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 #include <sys/types.h>
41 #include <sys/stat.h>
42 #include <sys/time.h>
43 #include <errno.h>
44
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
47
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 arm7_9->reinit_embeddedice = 0;
88
89 return ERROR_OK;
90 }
91
92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 {
94 target_t *target = priv;
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
101 */
102 if (event == JTAG_TRST_ASSERTED)
103 {
104 arm7_9->reinit_embeddedice = 1;
105 }
106
107 return ERROR_OK;
108 }
109
110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 {
112 armv4_5_common_t *armv4_5 = target->arch_info;
113 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114
115 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
116 {
117 return -1;
118 }
119
120 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
121 {
122 return -1;
123 }
124
125 *armv4_5_p = armv4_5;
126 *arm7_9_p = arm7_9;
127
128 return ERROR_OK;
129 }
130
131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 {
133 armv4_5_common_t *armv4_5 = target->arch_info;
134 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135
136 if (target->state != TARGET_HALTED)
137 {
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED;
140 }
141
142 if (arm7_9->force_hw_bkpts)
143 breakpoint->type = BKPT_HARD;
144
145 if (breakpoint->set)
146 {
147 WARNING("breakpoint already set");
148 return ERROR_OK;
149 }
150
151 if (breakpoint->type == BKPT_HARD)
152 {
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
155 if (!arm7_9->wp0_used)
156 {
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162
163 jtag_execute_queue();
164 arm7_9->wp0_used = 1;
165 breakpoint->set = 1;
166 }
167 else if (!arm7_9->wp1_used)
168 {
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
173 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174
175 jtag_execute_queue();
176 arm7_9->wp1_used = 1;
177 breakpoint->set = 2;
178 }
179 else
180 {
181 ERROR("BUG: no hardware comparator available");
182 return ERROR_OK;
183 }
184 }
185 else if (breakpoint->type == BKPT_SOFT)
186 {
187 if (breakpoint->length == 4)
188 {
189 u32 verify = 0xffffffff;
190 /* keep the original instruction in target endianness */
191 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
192 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
193 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
194
195 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
196 if (verify != arm7_9->arm_bkpt)
197 {
198 ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
199 return ERROR_OK;
200 }
201 }
202 else
203 {
204 u16 verify = 0xffff;
205 /* keep the original instruction in target endianness */
206 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
207 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
208 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
209
210 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
211 if (verify != arm7_9->thumb_bkpt)
212 {
213 ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
214 return ERROR_OK;
215 }
216 }
217 breakpoint->set = 1;
218 }
219
220 return ERROR_OK;
221
222 }
223
224 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
225 {
226 armv4_5_common_t *armv4_5 = target->arch_info;
227 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
228
229 if (target->state != TARGET_HALTED)
230 {
231 WARNING("target not halted");
232 return ERROR_TARGET_NOT_HALTED;
233 }
234
235 if (!breakpoint->set)
236 {
237 WARNING("breakpoint not set");
238 return ERROR_OK;
239 }
240
241 if (breakpoint->type == BKPT_HARD)
242 {
243 if (breakpoint->set == 1)
244 {
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
246 jtag_execute_queue();
247 arm7_9->wp0_used = 0;
248 }
249 else if (breakpoint->set == 2)
250 {
251 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
252 jtag_execute_queue();
253 arm7_9->wp1_used = 0;
254 }
255 breakpoint->set = 0;
256 }
257 else
258 {
259 /* restore original instruction (kept in target endianness) */
260 if (breakpoint->length == 4)
261 {
262 u32 current_instr;
263 /* check that user program as not modified breakpoint instruction */
264 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
265 if (current_instr==arm7_9->arm_bkpt)
266 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
267 }
268 else
269 {
270 u16 current_instr;
271 /* check that user program as not modified breakpoint instruction */
272 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
273 if (current_instr==arm7_9->thumb_bkpt)
274 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
275 }
276 breakpoint->set = 0;
277 }
278
279 return ERROR_OK;
280 }
281
282 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
283 {
284 armv4_5_common_t *armv4_5 = target->arch_info;
285 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
286
287 if (target->state != TARGET_HALTED)
288 {
289 WARNING("target not halted");
290 return ERROR_TARGET_NOT_HALTED;
291 }
292
293 if (arm7_9->force_hw_bkpts)
294 {
295 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
296 breakpoint->type = BKPT_HARD;
297 }
298
299 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
300 {
301 INFO("sw breakpoint requested, but software breakpoints not enabled");
302 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
303 }
304
305 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
306 {
307 INFO("no watchpoint unit available for hardware breakpoint");
308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
309 }
310
311 if ((breakpoint->length != 2) && (breakpoint->length != 4))
312 {
313 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
315 }
316
317 if (breakpoint->type == BKPT_HARD)
318 arm7_9->wp_available--;
319
320 return ERROR_OK;
321 }
322
323 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
324 {
325 armv4_5_common_t *armv4_5 = target->arch_info;
326 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327
328 if (target->state != TARGET_HALTED)
329 {
330 WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED;
332 }
333
334 if (breakpoint->set)
335 {
336 arm7_9_unset_breakpoint(target, breakpoint);
337 }
338
339 if (breakpoint->type == BKPT_HARD)
340 arm7_9->wp_available++;
341
342 return ERROR_OK;
343 }
344
345 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
346 {
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
349 int rw_mask = 1;
350 u32 mask;
351
352 mask = watchpoint->length - 1;
353
354 if (target->state != TARGET_HALTED)
355 {
356 WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED;
358 }
359
360 if (watchpoint->rw == WPT_ACCESS)
361 rw_mask = 0;
362 else
363 rw_mask = 1;
364
365 if (!arm7_9->wp0_used)
366 {
367 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
368 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
369 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
370 if( watchpoint->mask != 0xffffffffu )
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
374
375 jtag_execute_queue();
376 watchpoint->set = 1;
377 arm7_9->wp0_used = 2;
378 }
379 else if (!arm7_9->wp1_used)
380 {
381 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
382 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
383 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
384 if( watchpoint->mask != 0xffffffffu )
385 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
386 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
387 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
388
389 jtag_execute_queue();
390 watchpoint->set = 2;
391 arm7_9->wp1_used = 2;
392 }
393 else
394 {
395 ERROR("BUG: no hardware comparator available");
396 return ERROR_OK;
397 }
398
399 return ERROR_OK;
400 }
401
402 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
403 {
404 armv4_5_common_t *armv4_5 = target->arch_info;
405 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
406
407 if (target->state != TARGET_HALTED)
408 {
409 WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED;
411 }
412
413 if (!watchpoint->set)
414 {
415 WARNING("breakpoint not set");
416 return ERROR_OK;
417 }
418
419 if (watchpoint->set == 1)
420 {
421 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
422 jtag_execute_queue();
423 arm7_9->wp0_used = 0;
424 }
425 else if (watchpoint->set == 2)
426 {
427 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
428 jtag_execute_queue();
429 arm7_9->wp1_used = 0;
430 }
431 watchpoint->set = 0;
432
433 return ERROR_OK;
434 }
435
436 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
437 {
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440
441 if (target->state != TARGET_HALTED)
442 {
443 WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED;
445 }
446
447 if (arm7_9->wp_available < 1)
448 {
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
450 }
451
452 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
453 {
454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
455 }
456
457 arm7_9->wp_available--;
458
459 return ERROR_OK;
460 }
461
462 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
463 {
464 armv4_5_common_t *armv4_5 = target->arch_info;
465 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
466
467 if (target->state != TARGET_HALTED)
468 {
469 WARNING("target not halted");
470 return ERROR_TARGET_NOT_HALTED;
471 }
472
473 if (watchpoint->set)
474 {
475 arm7_9_unset_watchpoint(target, watchpoint);
476 }
477
478 arm7_9->wp_available++;
479
480 return ERROR_OK;
481 }
482
483 int arm7_9_enable_sw_bkpts(struct target_s *target)
484 {
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 int retval;
488
489 if (arm7_9->sw_bkpts_enabled)
490 return ERROR_OK;
491
492 if (arm7_9->wp_available < 1)
493 {
494 WARNING("can't enable sw breakpoints with no watchpoint unit available");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
496 }
497 arm7_9->wp_available--;
498
499 if (!arm7_9->wp0_used)
500 {
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 1;
507 arm7_9->wp0_used = 3;
508 }
509 else if (!arm7_9->wp1_used)
510 {
511 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
512 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
513 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
514 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
515 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
516 arm7_9->sw_bkpts_enabled = 2;
517 arm7_9->wp1_used = 3;
518 }
519 else
520 {
521 ERROR("BUG: both watchpoints used, but wp_available >= 1");
522 exit(-1);
523 }
524
525 if ((retval = jtag_execute_queue()) != ERROR_OK)
526 {
527 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
528 exit(-1);
529 };
530
531 return ERROR_OK;
532 }
533
534 int arm7_9_disable_sw_bkpts(struct target_s *target)
535 {
536 armv4_5_common_t *armv4_5 = target->arch_info;
537 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
538
539 if (!arm7_9->sw_bkpts_enabled)
540 return ERROR_OK;
541
542 if (arm7_9->sw_bkpts_enabled == 1)
543 {
544 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
545 arm7_9->sw_bkpts_enabled = 0;
546 arm7_9->wp0_used = 0;
547 arm7_9->wp_available++;
548 }
549 else if (arm7_9->sw_bkpts_enabled == 2)
550 {
551 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
552 arm7_9->sw_bkpts_enabled = 0;
553 arm7_9->wp1_used = 0;
554 arm7_9->wp_available++;
555 }
556
557 return ERROR_OK;
558 }
559
560 int arm7_9_execute_sys_speed(struct target_s *target)
561 {
562 int timeout;
563 int retval;
564
565 armv4_5_common_t *armv4_5 = target->arch_info;
566 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
567 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
568 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
569
570 /* set RESTART instruction */
571 jtag_add_end_state(TAP_RTI);
572 arm_jtag_set_instr(jtag_info, 0x4, NULL);
573
574 for (timeout=0; timeout<50; timeout++)
575 {
576 /* read debug status register */
577 embeddedice_read_reg(dbg_stat);
578 if ((retval = jtag_execute_queue()) != ERROR_OK)
579 return retval;
580 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
581 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
582 break;
583 usleep(100000);
584 }
585 if (timeout == 50)
586 {
587 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
588 return ERROR_TARGET_TIMEOUT;
589 }
590
591 return ERROR_OK;
592 }
593
594 int arm7_9_execute_fast_sys_speed(struct target_s *target)
595 {
596 static int set=0;
597 static u8 check_value[4], check_mask[4];
598
599 armv4_5_common_t *armv4_5 = target->arch_info;
600 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
601 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
602 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
603
604 /* set RESTART instruction */
605 jtag_add_end_state(TAP_RTI);
606 arm_jtag_set_instr(jtag_info, 0x4, NULL);
607
608 if (!set)
609 {
610 /* check for DBGACK and SYSCOMP set (others don't care) */
611
612 /* NB! These are constants that must be available until after next jtag_execute() and
613 we evaluate the values upon first execution in lieu of setting up these constants
614 during early setup.
615 */
616 buf_set_u32(check_value, 0, 32, 0x9);
617 buf_set_u32(check_mask, 0, 32, 0x9);
618 set=1;
619 }
620
621 /* read debug status register */
622 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
623
624 return ERROR_OK;
625 }
626
627 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
628 {
629 armv4_5_common_t *armv4_5 = target->arch_info;
630 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
631 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
632 u32 *data;
633 int i;
634
635 data = malloc(size * (sizeof(u32)));
636
637 embeddedice_receive(jtag_info, data, size);
638
639 for (i = 0; i < size; i++)
640 {
641 h_u32_to_le(buffer + (i * 4), data[i]);
642 }
643
644 free(data);
645
646 return ERROR_OK;
647 }
648
649 int arm7_9_handle_target_request(void *priv)
650 {
651 target_t *target = priv;
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
656
657 if (!target->dbg_msg_enabled)
658 return ERROR_OK;
659
660 if (target->state == TARGET_RUNNING)
661 {
662 /* read DCC control register */
663 embeddedice_read_reg(dcc_control);
664 jtag_execute_queue();
665
666 /* check W bit */
667 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
668 {
669 u32 request;
670
671 embeddedice_receive(jtag_info, &request, 1);
672 target_request(target, request);
673 }
674 }
675
676 return ERROR_OK;
677 }
678
679 int arm7_9_poll(target_t *target)
680 {
681 int retval;
682 armv4_5_common_t *armv4_5 = target->arch_info;
683 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
684 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
685
686 if (arm7_9->reinit_embeddedice)
687 {
688 arm7_9_reinit_embeddedice(target);
689 }
690
691 /* read debug status register */
692 embeddedice_read_reg(dbg_stat);
693 if ((retval = jtag_execute_queue()) != ERROR_OK)
694 {
695 return retval;
696 }
697
698 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
699 {
700 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
701 if (target->state == TARGET_UNKNOWN)
702 {
703 target->state = TARGET_RUNNING;
704 WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
705 }
706 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
707 {
708 target->state = TARGET_HALTED;
709 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
710 return retval;
711
712 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
713 }
714 if (target->state == TARGET_DEBUG_RUNNING)
715 {
716 target->state = TARGET_HALTED;
717 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
718 return retval;
719
720 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
721 }
722 if (target->state != TARGET_HALTED)
723 {
724 WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
725 }
726 }
727 else
728 {
729 if (target->state != TARGET_DEBUG_RUNNING)
730 target->state = TARGET_RUNNING;
731 }
732
733 return ERROR_OK;
734 }
735
736 int arm7_9_assert_reset(target_t *target)
737 {
738 int retval;
739
740 DEBUG("target->state: %s", target_state_strings[target->state]);
741
742 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
743 {
744 /* if the target wasn't running, there might be working areas allocated */
745 target_free_all_working_areas(target);
746
747 /* assert SRST and TRST */
748 /* system would get ouf sync if we didn't reset test-logic, too */
749 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
750 {
751 if (retval == ERROR_JTAG_RESET_CANT_SRST)
752 {
753 WARNING("can't assert srst");
754 return retval;
755 }
756 else
757 {
758 ERROR("unknown error");
759 exit(-1);
760 }
761 }
762 jtag_add_sleep(5000);
763 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
764 {
765 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
766 {
767 WARNING("srst resets test logic, too");
768 retval = jtag_add_reset(1, 1);
769 }
770 }
771 }
772 else
773 {
774 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
775 {
776 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
777 {
778 WARNING("srst resets test logic, too");
779 retval = jtag_add_reset(1, 1);
780 }
781
782 if (retval == ERROR_JTAG_RESET_CANT_SRST)
783 {
784 WARNING("can't assert srst");
785 return retval;
786 }
787 else if (retval != ERROR_OK)
788 {
789 ERROR("unknown error");
790 exit(-1);
791 }
792 }
793 }
794
795 target->state = TARGET_RESET;
796 jtag_add_sleep(50000);
797
798 armv4_5_invalidate_core_regs(target);
799
800 return ERROR_OK;
801
802 }
803
804 int arm7_9_deassert_reset(target_t *target)
805 {
806 DEBUG("target->state: %s", target_state_strings[target->state]);
807
808 /* deassert reset lines */
809 jtag_add_reset(0, 0);
810
811 return ERROR_OK;
812 }
813
814 int arm7_9_clear_halt(target_t *target)
815 {
816 armv4_5_common_t *armv4_5 = target->arch_info;
817 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
818 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
819
820 /* we used DBGRQ only if we didn't come out of reset */
821 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
822 {
823 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
824 */
825 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
826 embeddedice_store_reg(dbg_ctrl);
827 }
828 else
829 {
830 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
831 {
832 /* if we came out of reset, and vector catch is supported, we used
833 * vector catch to enter debug state
834 * restore the register in that case
835 */
836 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
837 }
838 else
839 {
840 /* restore registers if watchpoint unit 0 was in use
841 */
842 if (arm7_9->wp0_used)
843 {
844 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
845 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
846 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
847 }
848 /* control value always has to be restored, as it was either disabled,
849 * or enabled with possibly different bits
850 */
851 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
852 }
853 }
854
855 return ERROR_OK;
856 }
857
858 int arm7_9_soft_reset_halt(struct target_s *target)
859 {
860 armv4_5_common_t *armv4_5 = target->arch_info;
861 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
862 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
863 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
864 int i;
865
866 if (target->state == TARGET_RUNNING)
867 {
868 target->type->halt(target);
869 }
870
871 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
872 {
873 embeddedice_read_reg(dbg_stat);
874 jtag_execute_queue();
875 }
876 target->state = TARGET_HALTED;
877
878 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
879 * ensure that DBGRQ is cleared
880 */
881 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
882 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
883 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
884 embeddedice_store_reg(dbg_ctrl);
885
886 arm7_9_clear_halt(target);
887
888 /* if the target is in Thumb state, change to ARM state */
889 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
890 {
891 u32 r0_thumb, pc_thumb;
892 DEBUG("target entered debug from Thumb state, changing to ARM");
893 /* Entered debug from Thumb mode */
894 armv4_5->core_state = ARMV4_5_STATE_THUMB;
895 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
896 }
897
898 /* all register content is now invalid */
899 armv4_5_invalidate_core_regs(target);
900
901 /* SVC, ARM state, IRQ and FIQ disabled */
902 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
903 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
904 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
905
906 /* start fetching from 0x0 */
907 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
908 armv4_5->core_cache->reg_list[15].dirty = 1;
909 armv4_5->core_cache->reg_list[15].valid = 1;
910
911 armv4_5->core_mode = ARMV4_5_MODE_SVC;
912 armv4_5->core_state = ARMV4_5_STATE_ARM;
913
914 /* reset registers */
915 for (i = 0; i <= 14; i++)
916 {
917 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
918 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
919 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
920 }
921
922 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
923
924 return ERROR_OK;
925 }
926
927 int arm7_9_prepare_reset_halt(target_t *target)
928 {
929 armv4_5_common_t *armv4_5 = target->arch_info;
930 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
931
932 /* poll the target, and resume if it was currently halted */
933 arm7_9_poll(target);
934 if (target->state == TARGET_HALTED)
935 {
936 arm7_9_resume(target, 1, 0x0, 0, 1);
937 }
938
939 if (arm7_9->has_vector_catch)
940 {
941 /* program vector catch register to catch reset vector */
942 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
943 }
944 else
945 {
946 /* program watchpoint unit to match on reset vector address */
947 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
948 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
949 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
950 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
951 }
952
953 return ERROR_OK;
954 }
955
956 int arm7_9_halt(target_t *target)
957 {
958 armv4_5_common_t *armv4_5 = target->arch_info;
959 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
960 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
961
962 DEBUG("target->state: %s", target_state_strings[target->state]);
963
964 if (target->state == TARGET_HALTED)
965 {
966 WARNING("target was already halted");
967 return ERROR_TARGET_ALREADY_HALTED;
968 }
969
970 if (target->state == TARGET_UNKNOWN)
971 {
972 WARNING("target was in unknown state when halt was requested");
973 }
974
975 if (target->state == TARGET_RESET)
976 {
977 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
978 {
979 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
980 return ERROR_TARGET_FAILURE;
981 }
982 else
983 {
984 /* we came here in a reset_halt or reset_init sequence
985 * debug entry was already prepared in arm7_9_prepare_reset_halt()
986 */
987 target->debug_reason = DBG_REASON_DBGRQ;
988
989 return ERROR_OK;
990 }
991 }
992
993 if (arm7_9->use_dbgrq)
994 {
995 /* program EmbeddedICE Debug Control Register to assert DBGRQ
996 */
997 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
998 embeddedice_store_reg(dbg_ctrl);
999 }
1000 else
1001 {
1002 /* program watchpoint unit to match on any address
1003 */
1004 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1005 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1006 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1007 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
1008 }
1009
1010 target->debug_reason = DBG_REASON_DBGRQ;
1011
1012 return ERROR_OK;
1013 }
1014
1015 int arm7_9_debug_entry(target_t *target)
1016 {
1017 int i;
1018 u32 context[16];
1019 u32* context_p[16];
1020 u32 r0_thumb, pc_thumb;
1021 u32 cpsr;
1022 int retval;
1023 /* get pointers to arch-specific information */
1024 armv4_5_common_t *armv4_5 = target->arch_info;
1025 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1026 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1027 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1028
1029 #ifdef _DEBUG_ARM7_9_
1030 DEBUG("-");
1031 #endif
1032
1033 if (arm7_9->pre_debug_entry)
1034 arm7_9->pre_debug_entry(target);
1035
1036 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1037 * ensure that DBGRQ is cleared
1038 */
1039 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1040 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1041 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1042 embeddedice_store_reg(dbg_ctrl);
1043
1044 arm7_9_clear_halt(target);
1045
1046 if ((retval = jtag_execute_queue()) != ERROR_OK)
1047 {
1048 switch (retval)
1049 {
1050 case ERROR_JTAG_QUEUE_FAILED:
1051 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1052 exit(-1);
1053 break;
1054 default:
1055 break;
1056 }
1057 }
1058
1059 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1060 return retval;
1061
1062
1063 if (target->state != TARGET_HALTED)
1064 {
1065 WARNING("target not halted");
1066 return ERROR_TARGET_NOT_HALTED;
1067 }
1068
1069 /* if the target is in Thumb state, change to ARM state */
1070 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1071 {
1072 DEBUG("target entered debug from Thumb state");
1073 /* Entered debug from Thumb mode */
1074 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1075 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1076 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1077 }
1078 else
1079 {
1080 DEBUG("target entered debug from ARM state");
1081 /* Entered debug from ARM mode */
1082 armv4_5->core_state = ARMV4_5_STATE_ARM;
1083 }
1084
1085 for (i = 0; i < 16; i++)
1086 context_p[i] = &context[i];
1087 /* save core registers (r0 - r15 of current core mode) */
1088 arm7_9->read_core_regs(target, 0xffff, context_p);
1089
1090 arm7_9->read_xpsr(target, &cpsr, 0);
1091
1092 if ((retval = jtag_execute_queue()) != ERROR_OK)
1093 return retval;
1094
1095 /* if the core has been executing in Thumb state, set the T bit */
1096 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1097 cpsr |= 0x20;
1098
1099 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1100 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1101 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1102
1103 armv4_5->core_mode = cpsr & 0x1f;
1104
1105 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1106 {
1107 target->state = TARGET_UNKNOWN;
1108 ERROR("cpsr contains invalid mode value - communication failure");
1109 return ERROR_TARGET_FAILURE;
1110 }
1111
1112 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1113
1114 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1115 {
1116 DEBUG("thumb state, applying fixups");
1117 context[0] = r0_thumb;
1118 context[15] = pc_thumb;
1119 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1120 {
1121 /* adjust value stored by STM */
1122 context[15] -= 3 * 4;
1123 }
1124
1125 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1126 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1127 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1128 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1129 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1130 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1131 else if (target->debug_reason == DBG_REASON_DBGRQ)
1132 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1133 else
1134 {
1135 ERROR("unknown debug reason: %i", target->debug_reason);
1136 }
1137
1138
1139 for (i=0; i<=15; i++)
1140 {
1141 DEBUG("r%i: 0x%8.8x", i, context[i]);
1142 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1143 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1144 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1145 }
1146
1147 DEBUG("entered debug state at PC 0x%x", context[15]);
1148
1149 /* exceptions other than USR & SYS have a saved program status register */
1150 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1151 {
1152 u32 spsr;
1153 arm7_9->read_xpsr(target, &spsr, 1);
1154 jtag_execute_queue();
1155 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1156 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1157 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1158 }
1159
1160 /* r0 and r15 (pc) have to be restored later */
1161 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1162 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1163
1164 if ((retval = jtag->execute_queue()) != ERROR_OK)
1165 return retval;
1166
1167 if (arm7_9->post_debug_entry)
1168 arm7_9->post_debug_entry(target);
1169
1170 return ERROR_OK;
1171 }
1172
1173 int arm7_9_full_context(target_t *target)
1174 {
1175 int i;
1176 int retval;
1177 armv4_5_common_t *armv4_5 = target->arch_info;
1178 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1179
1180 DEBUG("-");
1181
1182 if (target->state != TARGET_HALTED)
1183 {
1184 WARNING("target not halted");
1185 return ERROR_TARGET_NOT_HALTED;
1186 }
1187
1188 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1189 * SYS shares registers with User, so we don't touch SYS
1190 */
1191 for(i = 0; i < 6; i++)
1192 {
1193 u32 mask = 0;
1194 u32* reg_p[16];
1195 int j;
1196 int valid = 1;
1197
1198 /* check if there are invalid registers in the current mode
1199 */
1200 for (j = 0; j <= 16; j++)
1201 {
1202 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1203 valid = 0;
1204 }
1205
1206 if (!valid)
1207 {
1208 u32 tmp_cpsr;
1209
1210 /* change processor mode (and mask T bit) */
1211 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1212 tmp_cpsr |= armv4_5_number_to_mode(i);
1213 tmp_cpsr &= ~0x20;
1214 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1215
1216 for (j = 0; j < 15; j++)
1217 {
1218 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1219 {
1220 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1221 mask |= 1 << j;
1222 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1223 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1224 }
1225 }
1226
1227 /* if only the PSR is invalid, mask is all zeroes */
1228 if (mask)
1229 arm7_9->read_core_regs(target, mask, reg_p);
1230
1231 /* check if the PSR has to be read */
1232 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1233 {
1234 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1235 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1236 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1237 }
1238 }
1239 }
1240
1241 /* restore processor mode (mask T bit) */
1242 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1243
1244 if ((retval = jtag_execute_queue()) != ERROR_OK)
1245 {
1246 ERROR("JTAG failure");
1247 exit(-1);
1248 }
1249 return ERROR_OK;
1250 }
1251
1252 int arm7_9_restore_context(target_t *target)
1253 {
1254 armv4_5_common_t *armv4_5 = target->arch_info;
1255 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1256 reg_t *reg;
1257 armv4_5_core_reg_t *reg_arch_info;
1258 enum armv4_5_mode current_mode = armv4_5->core_mode;
1259 int i, j;
1260 int dirty;
1261 int mode_change;
1262
1263 DEBUG("-");
1264
1265 if (target->state != TARGET_HALTED)
1266 {
1267 WARNING("target not halted");
1268 return ERROR_TARGET_NOT_HALTED;
1269 }
1270
1271 if (arm7_9->pre_restore_context)
1272 arm7_9->pre_restore_context(target);
1273
1274 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1275 * SYS shares registers with User, so we don't touch SYS
1276 */
1277 for (i = 0; i < 6; i++)
1278 {
1279 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1280 dirty = 0;
1281 mode_change = 0;
1282 /* check if there are dirty registers in the current mode
1283 */
1284 for (j = 0; j <= 16; j++)
1285 {
1286 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1287 reg_arch_info = reg->arch_info;
1288 if (reg->dirty == 1)
1289 {
1290 if (reg->valid == 1)
1291 {
1292 dirty = 1;
1293 DEBUG("examining dirty reg: %s", reg->name);
1294 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1295 && (reg_arch_info->mode != current_mode)
1296 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1297 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1298 {
1299 mode_change = 1;
1300 DEBUG("require mode change");
1301 }
1302 }
1303 else
1304 {
1305 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1306 }
1307 }
1308 }
1309
1310 if (dirty)
1311 {
1312 u32 mask = 0x0;
1313 int num_regs = 0;
1314 u32 regs[16];
1315
1316 if (mode_change)
1317 {
1318 u32 tmp_cpsr;
1319
1320 /* change processor mode (mask T bit) */
1321 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1322 tmp_cpsr |= armv4_5_number_to_mode(i);
1323 tmp_cpsr &= ~0x20;
1324 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1325 current_mode = armv4_5_number_to_mode(i);
1326 }
1327
1328 for (j = 0; j <= 14; j++)
1329 {
1330 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1331 reg_arch_info = reg->arch_info;
1332
1333
1334 if (reg->dirty == 1)
1335 {
1336 regs[j] = buf_get_u32(reg->value, 0, 32);
1337 mask |= 1 << j;
1338 num_regs++;
1339 reg->dirty = 0;
1340 reg->valid = 1;
1341 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1342 }
1343 }
1344
1345 if (mask)
1346 {
1347 arm7_9->write_core_regs(target, mask, regs);
1348 }
1349
1350 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1351 reg_arch_info = reg->arch_info;
1352 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1353 {
1354 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1355 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1356 }
1357 }
1358 }
1359
1360 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1361 {
1362 /* restore processor mode (mask T bit) */
1363 u32 tmp_cpsr;
1364
1365 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1366 tmp_cpsr |= armv4_5_number_to_mode(i);
1367 tmp_cpsr &= ~0x20;
1368 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1369 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1370 }
1371 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1372 {
1373 /* CPSR has been changed, full restore necessary (mask T bit) */
1374 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1375 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1376 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1377 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1378 }
1379
1380 /* restore PC */
1381 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1382 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1383 armv4_5->core_cache->reg_list[15].dirty = 0;
1384
1385 if (arm7_9->post_restore_context)
1386 arm7_9->post_restore_context(target);
1387
1388 return ERROR_OK;
1389 }
1390
1391 int arm7_9_restart_core(struct target_s *target)
1392 {
1393 armv4_5_common_t *armv4_5 = target->arch_info;
1394 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1395 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1396
1397 /* set RESTART instruction */
1398 jtag_add_end_state(TAP_RTI);
1399 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1400
1401 jtag_add_runtest(1, TAP_RTI);
1402 if ((jtag_execute_queue()) != ERROR_OK)
1403 {
1404 exit(-1);
1405 }
1406
1407 return ERROR_OK;
1408 }
1409
1410 void arm7_9_enable_watchpoints(struct target_s *target)
1411 {
1412 watchpoint_t *watchpoint = target->watchpoints;
1413
1414 while (watchpoint)
1415 {
1416 if (watchpoint->set == 0)
1417 arm7_9_set_watchpoint(target, watchpoint);
1418 watchpoint = watchpoint->next;
1419 }
1420 }
1421
1422 void arm7_9_enable_breakpoints(struct target_s *target)
1423 {
1424 breakpoint_t *breakpoint = target->breakpoints;
1425
1426 /* set any pending breakpoints */
1427 while (breakpoint)
1428 {
1429 if (breakpoint->set == 0)
1430 arm7_9_set_breakpoint(target, breakpoint);
1431 breakpoint = breakpoint->next;
1432 }
1433 }
1434
1435 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1436 {
1437 breakpoint_t *breakpoint = target->breakpoints;
1438 watchpoint_t *watchpoint = target->watchpoints;
1439
1440 /* set any pending breakpoints */
1441 while (breakpoint)
1442 {
1443 if (breakpoint->set != 0)
1444 arm7_9_unset_breakpoint(target, breakpoint);
1445 breakpoint = breakpoint->next;
1446 }
1447
1448 while (watchpoint)
1449 {
1450 if (watchpoint->set != 0)
1451 arm7_9_unset_watchpoint(target, watchpoint);
1452 watchpoint = watchpoint->next;
1453 }
1454 }
1455
1456 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1457 {
1458 armv4_5_common_t *armv4_5 = target->arch_info;
1459 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1460 breakpoint_t *breakpoint = target->breakpoints;
1461 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1462 int err;
1463
1464 DEBUG("-");
1465
1466 if (target->state != TARGET_HALTED)
1467 {
1468 WARNING("target not halted");
1469 return ERROR_TARGET_NOT_HALTED;
1470 }
1471
1472 if (!debug_execution)
1473 {
1474 target_free_all_working_areas(target);
1475 }
1476
1477 /* current = 1: continue on current pc, otherwise continue at <address> */
1478 if (!current)
1479 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1480
1481 /* the front-end may request us not to handle breakpoints */
1482 if (handle_breakpoints)
1483 {
1484 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1485 {
1486 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1487 arm7_9_unset_breakpoint(target, breakpoint);
1488
1489 DEBUG("enable single-step");
1490 arm7_9->enable_single_step(target);
1491
1492 target->debug_reason = DBG_REASON_SINGLESTEP;
1493
1494 arm7_9_restore_context(target);
1495
1496 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1497 arm7_9->branch_resume(target);
1498 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1499 {
1500 arm7_9->branch_resume_thumb(target);
1501 }
1502 else
1503 {
1504 ERROR("unhandled core state");
1505 exit(-1);
1506 }
1507
1508 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1509 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1510 err = arm7_9_execute_sys_speed(target);
1511
1512 DEBUG("disable single-step");
1513 arm7_9->disable_single_step(target);
1514
1515 if (err != ERROR_OK)
1516 {
1517 arm7_9_set_breakpoint(target, breakpoint);
1518 target->state = TARGET_UNKNOWN;
1519 return err;
1520 }
1521
1522 arm7_9_debug_entry(target);
1523 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1524
1525 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1526 arm7_9_set_breakpoint(target, breakpoint);
1527 }
1528 }
1529
1530 /* enable any pending breakpoints and watchpoints */
1531 arm7_9_enable_breakpoints(target);
1532 arm7_9_enable_watchpoints(target);
1533
1534 arm7_9_restore_context(target);
1535
1536 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1537 {
1538 arm7_9->branch_resume(target);
1539 }
1540 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1541 {
1542 arm7_9->branch_resume_thumb(target);
1543 }
1544 else
1545 {
1546 ERROR("unhandled core state");
1547 exit(-1);
1548 }
1549
1550 /* deassert DBGACK and INTDIS */
1551 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1552 /* INTDIS only when we really resume, not during debug execution */
1553 if (!debug_execution)
1554 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1555 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1556
1557 arm7_9_restart_core(target);
1558
1559 target->debug_reason = DBG_REASON_NOTHALTED;
1560
1561 if (!debug_execution)
1562 {
1563 /* registers are now invalid */
1564 armv4_5_invalidate_core_regs(target);
1565 target->state = TARGET_RUNNING;
1566 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1567 }
1568 else
1569 {
1570 target->state = TARGET_DEBUG_RUNNING;
1571 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1572 }
1573
1574 DEBUG("target resumed");
1575
1576 return ERROR_OK;
1577 }
1578
1579 void arm7_9_enable_eice_step(target_t *target)
1580 {
1581 armv4_5_common_t *armv4_5 = target->arch_info;
1582 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1583
1584 /* setup an inverse breakpoint on the current PC
1585 * - comparator 1 matches the current address
1586 * - rangeout from comparator 1 is connected to comparator 0 rangein
1587 * - comparator 0 matches any address, as long as rangein is low */
1588 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1589 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1590 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1591 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1592 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1593 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1594 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1595 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1596 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1597 }
1598
1599 void arm7_9_disable_eice_step(target_t *target)
1600 {
1601 armv4_5_common_t *armv4_5 = target->arch_info;
1602 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1603
1604 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1605 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1606 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1607 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1608 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1609 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1610 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1611 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1612 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1613 }
1614
1615 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1616 {
1617 armv4_5_common_t *armv4_5 = target->arch_info;
1618 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1619 breakpoint_t *breakpoint = NULL;
1620 int err;
1621
1622 if (target->state != TARGET_HALTED)
1623 {
1624 WARNING("target not halted");
1625 return ERROR_TARGET_NOT_HALTED;
1626 }
1627
1628 /* current = 1: continue on current pc, otherwise continue at <address> */
1629 if (!current)
1630 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1631
1632 /* the front-end may request us not to handle breakpoints */
1633 if (handle_breakpoints)
1634 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1635 arm7_9_unset_breakpoint(target, breakpoint);
1636
1637 target->debug_reason = DBG_REASON_SINGLESTEP;
1638
1639 arm7_9_restore_context(target);
1640
1641 arm7_9->enable_single_step(target);
1642
1643 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1644 {
1645 arm7_9->branch_resume(target);
1646 }
1647 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1648 {
1649 arm7_9->branch_resume_thumb(target);
1650 }
1651 else
1652 {
1653 ERROR("unhandled core state");
1654 exit(-1);
1655 }
1656
1657 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1658
1659 err = arm7_9_execute_sys_speed(target);
1660 arm7_9->disable_single_step(target);
1661
1662 /* registers are now invalid */
1663 armv4_5_invalidate_core_regs(target);
1664
1665 if (err != ERROR_OK)
1666 {
1667 target->state = TARGET_UNKNOWN;
1668 } else {
1669 arm7_9_debug_entry(target);
1670 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1671 DEBUG("target stepped");
1672 }
1673
1674 if (breakpoint)
1675 arm7_9_set_breakpoint(target, breakpoint);
1676
1677 return err;
1678
1679 }
1680
1681 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1682 {
1683 u32* reg_p[16];
1684 u32 value;
1685 int retval;
1686 armv4_5_common_t *armv4_5 = target->arch_info;
1687 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1688 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1689
1690 if ((num < 0) || (num > 16))
1691 return ERROR_INVALID_ARGUMENTS;
1692
1693 if ((mode != ARMV4_5_MODE_ANY)
1694 && (mode != armv4_5->core_mode)
1695 && (reg_mode != ARMV4_5_MODE_ANY))
1696 {
1697 u32 tmp_cpsr;
1698
1699 /* change processor mode (mask T bit) */
1700 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1701 tmp_cpsr |= mode;
1702 tmp_cpsr &= ~0x20;
1703 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1704 }
1705
1706 if ((num >= 0) && (num <= 15))
1707 {
1708 /* read a normal core register */
1709 reg_p[num] = &value;
1710
1711 arm7_9->read_core_regs(target, 1 << num, reg_p);
1712 }
1713 else
1714 {
1715 /* read a program status register
1716 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1717 */
1718 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1719 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1720
1721 arm7_9->read_xpsr(target, &value, spsr);
1722 }
1723
1724 if ((retval = jtag_execute_queue()) != ERROR_OK)
1725 {
1726 ERROR("JTAG failure");
1727 exit(-1);
1728 }
1729
1730 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1731 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1732 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1733
1734 if ((mode != ARMV4_5_MODE_ANY)
1735 && (mode != armv4_5->core_mode)
1736 && (reg_mode != ARMV4_5_MODE_ANY)) {
1737 /* restore processor mode (mask T bit) */
1738 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1739 }
1740
1741 return ERROR_OK;
1742
1743 }
1744
1745 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1746 {
1747 u32 reg[16];
1748 int retval;
1749 armv4_5_common_t *armv4_5 = target->arch_info;
1750 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1751 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1752
1753 if ((num < 0) || (num > 16))
1754 return ERROR_INVALID_ARGUMENTS;
1755
1756 if ((mode != ARMV4_5_MODE_ANY)
1757 && (mode != armv4_5->core_mode)
1758 && (reg_mode != ARMV4_5_MODE_ANY)) {
1759 u32 tmp_cpsr;
1760
1761 /* change processor mode (mask T bit) */
1762 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1763 tmp_cpsr |= mode;
1764 tmp_cpsr &= ~0x20;
1765 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1766 }
1767
1768 if ((num >= 0) && (num <= 15))
1769 {
1770 /* write a normal core register */
1771 reg[num] = value;
1772
1773 arm7_9->write_core_regs(target, 1 << num, reg);
1774 }
1775 else
1776 {
1777 /* write a program status register
1778 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1779 */
1780 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1781 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1782
1783 /* if we're writing the CPSR, mask the T bit */
1784 if (!spsr)
1785 value &= ~0x20;
1786
1787 arm7_9->write_xpsr(target, value, spsr);
1788 }
1789
1790 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1791 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1792
1793 if ((mode != ARMV4_5_MODE_ANY)
1794 && (mode != armv4_5->core_mode)
1795 && (reg_mode != ARMV4_5_MODE_ANY)) {
1796 /* restore processor mode (mask T bit) */
1797 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1798 }
1799
1800 if ((retval = jtag_execute_queue()) != ERROR_OK)
1801 {
1802 ERROR("JTAG failure");
1803 exit(-1);
1804 }
1805
1806 return ERROR_OK;
1807
1808 }
1809
1810 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1811 {
1812 armv4_5_common_t *armv4_5 = target->arch_info;
1813 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1814
1815 u32 reg[16];
1816 int num_accesses = 0;
1817 int thisrun_accesses;
1818 int i;
1819 u32 cpsr;
1820 int retval;
1821 int last_reg = 0;
1822
1823 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1824
1825 if (target->state != TARGET_HALTED)
1826 {
1827 WARNING("target not halted");
1828 return ERROR_TARGET_NOT_HALTED;
1829 }
1830
1831 /* sanitize arguments */
1832 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1833 return ERROR_INVALID_ARGUMENTS;
1834
1835 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1836 return ERROR_TARGET_UNALIGNED_ACCESS;
1837
1838 /* load the base register with the address of the first word */
1839 reg[0] = address;
1840 arm7_9->write_core_regs(target, 0x1, reg);
1841
1842 switch (size)
1843 {
1844 case 4:
1845 while (num_accesses < count)
1846 {
1847 u32 reg_list;
1848 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1849 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1850
1851 if (last_reg <= thisrun_accesses)
1852 last_reg = thisrun_accesses;
1853
1854 arm7_9->load_word_regs(target, reg_list);
1855
1856 /* fast memory reads are only safe when the target is running
1857 * from a sufficiently high clock (32 kHz is usually too slow)
1858 */
1859 if (arm7_9->fast_memory_access)
1860 arm7_9_execute_fast_sys_speed(target);
1861 else
1862 arm7_9_execute_sys_speed(target);
1863
1864 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1865
1866 /* advance buffer, count number of accesses */
1867 buffer += thisrun_accesses * 4;
1868 num_accesses += thisrun_accesses;
1869 }
1870 break;
1871 case 2:
1872 while (num_accesses < count)
1873 {
1874 u32 reg_list;
1875 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1876 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1877
1878 for (i = 1; i <= thisrun_accesses; i++)
1879 {
1880 if (i > last_reg)
1881 last_reg = i;
1882 arm7_9->load_hword_reg(target, i);
1883 /* fast memory reads are only safe when the target is running
1884 * from a sufficiently high clock (32 kHz is usually too slow)
1885 */
1886 if (arm7_9->fast_memory_access)
1887 arm7_9_execute_fast_sys_speed(target);
1888 else
1889 arm7_9_execute_sys_speed(target);
1890 }
1891
1892 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1893
1894 /* advance buffer, count number of accesses */
1895 buffer += thisrun_accesses * 2;
1896 num_accesses += thisrun_accesses;
1897 }
1898 break;
1899 case 1:
1900 while (num_accesses < count)
1901 {
1902 u32 reg_list;
1903 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1904 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1905
1906 for (i = 1; i <= thisrun_accesses; i++)
1907 {
1908 if (i > last_reg)
1909 last_reg = i;
1910 arm7_9->load_byte_reg(target, i);
1911 /* fast memory reads are only safe when the target is running
1912 * from a sufficiently high clock (32 kHz is usually too slow)
1913 */
1914 if (arm7_9->fast_memory_access)
1915 arm7_9_execute_fast_sys_speed(target);
1916 else
1917 arm7_9_execute_sys_speed(target);
1918 }
1919
1920 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1921
1922 /* advance buffer, count number of accesses */
1923 buffer += thisrun_accesses * 1;
1924 num_accesses += thisrun_accesses;
1925 }
1926 break;
1927 default:
1928 ERROR("BUG: we shouldn't get here");
1929 exit(-1);
1930 break;
1931 }
1932
1933 for (i=0; i<=last_reg; i++)
1934 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1935
1936 arm7_9->read_xpsr(target, &cpsr, 0);
1937 if ((retval = jtag_execute_queue()) != ERROR_OK)
1938 {
1939 ERROR("JTAG error while reading cpsr");
1940 return ERROR_TARGET_DATA_ABORT;
1941 }
1942
1943 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1944 {
1945 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1946
1947 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1948
1949 return ERROR_TARGET_DATA_ABORT;
1950 }
1951
1952 return ERROR_OK;
1953 }
1954
1955 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1956 {
1957 armv4_5_common_t *armv4_5 = target->arch_info;
1958 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1959 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1960
1961 u32 reg[16];
1962 int num_accesses = 0;
1963 int thisrun_accesses;
1964 int i;
1965 u32 cpsr;
1966 int retval;
1967 int last_reg = 0;
1968
1969 #ifdef _DEBUG_ARM7_9_
1970 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1971 #endif
1972
1973 if (target->state != TARGET_HALTED)
1974 {
1975 WARNING("target not halted");
1976 return ERROR_TARGET_NOT_HALTED;
1977 }
1978
1979 /* sanitize arguments */
1980 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1981 return ERROR_INVALID_ARGUMENTS;
1982
1983 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1984 return ERROR_TARGET_UNALIGNED_ACCESS;
1985
1986 /* load the base register with the address of the first word */
1987 reg[0] = address;
1988 arm7_9->write_core_regs(target, 0x1, reg);
1989
1990 /* Clear DBGACK, to make sure memory fetches work as expected */
1991 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1992 embeddedice_store_reg(dbg_ctrl);
1993
1994 switch (size)
1995 {
1996 case 4:
1997 while (num_accesses < count)
1998 {
1999 u32 reg_list;
2000 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2001 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2002
2003 for (i = 1; i <= thisrun_accesses; i++)
2004 {
2005 if (i > last_reg)
2006 last_reg = i;
2007 reg[i] = target_buffer_get_u32(target, buffer);
2008 buffer += 4;
2009 }
2010
2011 arm7_9->write_core_regs(target, reg_list, reg);
2012
2013 arm7_9->store_word_regs(target, reg_list);
2014
2015 /* fast memory writes are only safe when the target is running
2016 * from a sufficiently high clock (32 kHz is usually too slow)
2017 */
2018 if (arm7_9->fast_memory_access)
2019 arm7_9_execute_fast_sys_speed(target);
2020 else
2021 arm7_9_execute_sys_speed(target);
2022
2023 num_accesses += thisrun_accesses;
2024 }
2025 break;
2026 case 2:
2027 while (num_accesses < count)
2028 {
2029 u32 reg_list;
2030 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2031 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2032
2033 for (i = 1; i <= thisrun_accesses; i++)
2034 {
2035 if (i > last_reg)
2036 last_reg = i;
2037 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2038 buffer += 2;
2039 }
2040
2041 arm7_9->write_core_regs(target, reg_list, reg);
2042
2043 for (i = 1; i <= thisrun_accesses; i++)
2044 {
2045 arm7_9->store_hword_reg(target, i);
2046
2047 /* fast memory writes are only safe when the target is running
2048 * from a sufficiently high clock (32 kHz is usually too slow)
2049 */
2050 if (arm7_9->fast_memory_access)
2051 arm7_9_execute_fast_sys_speed(target);
2052 else
2053 arm7_9_execute_sys_speed(target);
2054 }
2055
2056 num_accesses += thisrun_accesses;
2057 }
2058 break;
2059 case 1:
2060 while (num_accesses < count)
2061 {
2062 u32 reg_list;
2063 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2064 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2065
2066 for (i = 1; i <= thisrun_accesses; i++)
2067 {
2068 if (i > last_reg)
2069 last_reg = i;
2070 reg[i] = *buffer++ & 0xff;
2071 }
2072
2073 arm7_9->write_core_regs(target, reg_list, reg);
2074
2075 for (i = 1; i <= thisrun_accesses; i++)
2076 {
2077 arm7_9->store_byte_reg(target, i);
2078 /* fast memory writes are only safe when the target is running
2079 * from a sufficiently high clock (32 kHz is usually too slow)
2080 */
2081 if (arm7_9->fast_memory_access)
2082 arm7_9_execute_fast_sys_speed(target);
2083 else
2084 arm7_9_execute_sys_speed(target);
2085 }
2086
2087 num_accesses += thisrun_accesses;
2088 }
2089 break;
2090 default:
2091 ERROR("BUG: we shouldn't get here");
2092 exit(-1);
2093 break;
2094 }
2095
2096 /* Re-Set DBGACK */
2097 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2098 embeddedice_store_reg(dbg_ctrl);
2099
2100 for (i=0; i<=last_reg; i++)
2101 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2102
2103 arm7_9->read_xpsr(target, &cpsr, 0);
2104 if ((retval = jtag_execute_queue()) != ERROR_OK)
2105 {
2106 ERROR("JTAG error while reading cpsr");
2107 return ERROR_TARGET_DATA_ABORT;
2108 }
2109
2110 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2111 {
2112 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2113
2114 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2115
2116 return ERROR_TARGET_DATA_ABORT;
2117 }
2118
2119 return ERROR_OK;
2120 }
2121
2122 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2123 {
2124 armv4_5_common_t *armv4_5 = target->arch_info;
2125 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2126 enum armv4_5_state core_state = armv4_5->core_state;
2127 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2128 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2129 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2130 int i;
2131
2132 u32 dcc_code[] =
2133 {
2134 /* MRC TST BNE MRC STR B */
2135 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2136 };
2137
2138 if (!arm7_9->dcc_downloads)
2139 return target->type->write_memory(target, address, 4, count, buffer);
2140
2141 /* regrab previously allocated working_area, or allocate a new one */
2142 if (!arm7_9->dcc_working_area)
2143 {
2144 u8 dcc_code_buf[6 * 4];
2145
2146 /* make sure we have a working area */
2147 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2148 {
2149 INFO("no working area available, falling back to memory writes");
2150 return target->type->write_memory(target, address, 4, count, buffer);
2151 }
2152
2153 /* copy target instructions to target endianness */
2154 for (i = 0; i < 6; i++)
2155 {
2156 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2157 }
2158
2159 /* write DCC code to working area */
2160 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2161 }
2162
2163 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2164 armv4_5->core_cache->reg_list[0].valid = 1;
2165 armv4_5->core_cache->reg_list[0].dirty = 1;
2166 armv4_5->core_state = ARMV4_5_STATE_ARM;
2167
2168 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2169
2170 for (i = 0; i < count; i++)
2171 {
2172 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2173 buffer += 4;
2174 }
2175
2176 target->type->halt(target);
2177
2178 while (target->state != TARGET_HALTED)
2179 target->type->poll(target);
2180
2181 /* restore target state */
2182 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2183 armv4_5->core_cache->reg_list[0].valid = 1;
2184 armv4_5->core_cache->reg_list[0].dirty = 1;
2185 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2186 armv4_5->core_cache->reg_list[1].valid = 1;
2187 armv4_5->core_cache->reg_list[1].dirty = 1;
2188 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2189 armv4_5->core_cache->reg_list[15].valid = 1;
2190 armv4_5->core_cache->reg_list[15].dirty = 1;
2191 armv4_5->core_state = core_state;
2192
2193 return ERROR_OK;
2194 }
2195
2196 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2197 {
2198 working_area_t *crc_algorithm;
2199 armv4_5_algorithm_t armv4_5_info;
2200 reg_param_t reg_params[2];
2201 int retval;
2202
2203 u32 arm7_9_crc_code[] = {
2204 0xE1A02000, /* mov r2, r0 */
2205 0xE3E00000, /* mov r0, #0xffffffff */
2206 0xE1A03001, /* mov r3, r1 */
2207 0xE3A04000, /* mov r4, #0 */
2208 0xEA00000B, /* b ncomp */
2209 /* nbyte: */
2210 0xE7D21004, /* ldrb r1, [r2, r4] */
2211 0xE59F7030, /* ldr r7, CRC32XOR */
2212 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2213 0xE3A05000, /* mov r5, #0 */
2214 /* loop: */
2215 0xE3500000, /* cmp r0, #0 */
2216 0xE1A06080, /* mov r6, r0, asl #1 */
2217 0xE2855001, /* add r5, r5, #1 */
2218 0xE1A00006, /* mov r0, r6 */
2219 0xB0260007, /* eorlt r0, r6, r7 */
2220 0xE3550008, /* cmp r5, #8 */
2221 0x1AFFFFF8, /* bne loop */
2222 0xE2844001, /* add r4, r4, #1 */
2223 /* ncomp: */
2224 0xE1540003, /* cmp r4, r3 */
2225 0x1AFFFFF1, /* bne nbyte */
2226 /* end: */
2227 0xEAFFFFFE, /* b end */
2228 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2229 };
2230
2231 int i;
2232
2233 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2234 {
2235 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2236 }
2237
2238 /* convert flash writing code into a buffer in target endianness */
2239 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2240 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2241
2242 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2243 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2244 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2245
2246 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2247 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2248
2249 buf_set_u32(reg_params[0].value, 0, 32, address);
2250 buf_set_u32(reg_params[1].value, 0, 32, count);
2251
2252 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2253 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2254 {
2255 ERROR("error executing arm7_9 crc algorithm");
2256 destroy_reg_param(&reg_params[0]);
2257 destroy_reg_param(&reg_params[1]);
2258 target_free_working_area(target, crc_algorithm);
2259 return retval;
2260 }
2261
2262 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2263
2264 destroy_reg_param(&reg_params[0]);
2265 destroy_reg_param(&reg_params[1]);
2266
2267 target_free_working_area(target, crc_algorithm);
2268
2269 return ERROR_OK;
2270 }
2271
2272 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2273 {
2274 command_t *arm7_9_cmd;
2275
2276 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2277
2278 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2279 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2280
2281 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2282
2283 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2284 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2285 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2286 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2287 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2288 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2289 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2290 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2291 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2292 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2293
2294 armv4_5_register_commands(cmd_ctx);
2295
2296 etm_register_commands(cmd_ctx);
2297
2298 return ERROR_OK;
2299 }
2300
2301 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2302 {
2303 u32 value;
2304 int spsr;
2305 int retval;
2306 target_t *target = get_current_target(cmd_ctx);
2307 armv4_5_common_t *armv4_5;
2308 arm7_9_common_t *arm7_9;
2309
2310 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2311 {
2312 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2313 return ERROR_OK;
2314 }
2315
2316 if (target->state != TARGET_HALTED)
2317 {
2318 command_print(cmd_ctx, "can't write registers while running");
2319 return ERROR_OK;
2320 }
2321
2322 if (argc < 2)
2323 {
2324 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2325 return ERROR_OK;
2326 }
2327
2328 value = strtoul(args[0], NULL, 0);
2329 spsr = strtol(args[1], NULL, 0);
2330
2331 /* if we're writing the CPSR, mask the T bit */
2332 if (!spsr)
2333 value &= ~0x20;
2334
2335 arm7_9->write_xpsr(target, value, spsr);
2336 if ((retval = jtag_execute_queue()) != ERROR_OK)
2337 {
2338 ERROR("JTAG error while writing to xpsr");
2339 exit(-1);
2340 }
2341
2342 return ERROR_OK;
2343 }
2344
2345 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2346 {
2347 u32 value;
2348 int rotate;
2349 int spsr;
2350 int retval;
2351 target_t *target = get_current_target(cmd_ctx);
2352 armv4_5_common_t *armv4_5;
2353 arm7_9_common_t *arm7_9;
2354
2355 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2356 {
2357 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2358 return ERROR_OK;
2359 }
2360
2361 if (target->state != TARGET_HALTED)
2362 {
2363 command_print(cmd_ctx, "can't write registers while running");
2364 return ERROR_OK;
2365 }
2366
2367 if (argc < 3)
2368 {
2369 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2370 return ERROR_OK;
2371 }
2372
2373 value = strtoul(args[0], NULL, 0);
2374 rotate = strtol(args[1], NULL, 0);
2375 spsr = strtol(args[2], NULL, 0);
2376
2377 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2378 if ((retval = jtag_execute_queue()) != ERROR_OK)
2379 {
2380 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2381 exit(-1);
2382 }
2383
2384 return ERROR_OK;
2385 }
2386
2387 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2388 {
2389 u32 value;
2390 u32 mode;
2391 int num;
2392 target_t *target = get_current_target(cmd_ctx);
2393 armv4_5_common_t *armv4_5;
2394 arm7_9_common_t *arm7_9;
2395
2396 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2397 {
2398 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2399 return ERROR_OK;
2400 }
2401
2402 if (target->state != TARGET_HALTED)
2403 {
2404 command_print(cmd_ctx, "can't write registers while running");
2405 return ERROR_OK;
2406 }
2407
2408 if (argc < 3)
2409 {
2410 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2411 return ERROR_OK;
2412 }
2413
2414 num = strtol(args[0], NULL, 0);
2415 mode = strtoul(args[1], NULL, 0);
2416 value = strtoul(args[2], NULL, 0);
2417
2418 arm7_9_write_core_reg(target, num, mode, value);
2419
2420 return ERROR_OK;
2421 }
2422
2423 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2424 {
2425 target_t *target = get_current_target(cmd_ctx);
2426 armv4_5_common_t *armv4_5;
2427 arm7_9_common_t *arm7_9;
2428
2429 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2430 {
2431 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2432 return ERROR_OK;
2433 }
2434
2435 if (argc == 0)
2436 {
2437 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2438 return ERROR_OK;
2439 }
2440
2441 if (strcmp("enable", args[0]) == 0)
2442 {
2443 if (arm7_9->sw_bkpts_use_wp)
2444 {
2445 arm7_9_enable_sw_bkpts(target);
2446 }
2447 else
2448 {
2449 arm7_9->sw_bkpts_enabled = 1;
2450 }
2451 }
2452 else if (strcmp("disable", args[0]) == 0)
2453 {
2454 if (arm7_9->sw_bkpts_use_wp)
2455 {
2456 arm7_9_disable_sw_bkpts(target);
2457 }
2458 else
2459 {
2460 arm7_9->sw_bkpts_enabled = 0;
2461 }
2462 }
2463 else
2464 {
2465 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2466 }
2467
2468 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2469
2470 return ERROR_OK;
2471 }
2472
2473 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2474 {
2475 target_t *target = get_current_target(cmd_ctx);
2476 armv4_5_common_t *armv4_5;
2477 arm7_9_common_t *arm7_9;
2478
2479 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2480 {
2481 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2482 return ERROR_OK;
2483 }
2484
2485 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2486 {
2487 arm7_9->force_hw_bkpts = 1;
2488 if (arm7_9->sw_bkpts_use_wp)
2489 {
2490 arm7_9_disable_sw_bkpts(target);
2491 }
2492 }
2493 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2494 {
2495 arm7_9->force_hw_bkpts = 0;
2496 }
2497 else
2498 {
2499 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2500 }
2501
2502 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2503
2504 return ERROR_OK;
2505 }
2506
2507 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2508 {
2509 target_t *target = get_current_target(cmd_ctx);
2510 armv4_5_common_t *armv4_5;
2511 arm7_9_common_t *arm7_9;
2512
2513 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2514 {
2515 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2516 return ERROR_OK;
2517 }
2518
2519 if (argc > 0)
2520 {
2521 if (strcmp("enable", args[0]) == 0)
2522 {
2523 arm7_9->use_dbgrq = 1;
2524 }
2525 else if (strcmp("disable", args[0]) == 0)
2526 {
2527 arm7_9->use_dbgrq = 0;
2528 }
2529 else
2530 {
2531 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2532 }
2533 }
2534
2535 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2536
2537 return ERROR_OK;
2538 }
2539
2540 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2541 {
2542 target_t *target = get_current_target(cmd_ctx);
2543 armv4_5_common_t *armv4_5;
2544 arm7_9_common_t *arm7_9;
2545
2546 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2547 {
2548 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2549 return ERROR_OK;
2550 }
2551
2552 if (argc > 0)
2553 {
2554 if (strcmp("enable", args[0]) == 0)
2555 {
2556 arm7_9->fast_memory_access = 1;
2557 }
2558 else if (strcmp("disable", args[0]) == 0)
2559 {
2560 arm7_9->fast_memory_access = 0;
2561 }
2562 else
2563 {
2564 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2565 }
2566 }
2567
2568 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2569
2570 return ERROR_OK;
2571 }
2572
2573 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2574 {
2575 target_t *target = get_current_target(cmd_ctx);
2576 armv4_5_common_t *armv4_5;
2577 arm7_9_common_t *arm7_9;
2578
2579 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2580 {
2581 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2582 return ERROR_OK;
2583 }
2584
2585 if (argc > 0)
2586 {
2587 if (strcmp("enable", args[0]) == 0)
2588 {
2589 arm7_9->dcc_downloads = 1;
2590 }
2591 else if (strcmp("disable", args[0]) == 0)
2592 {
2593 arm7_9->dcc_downloads = 0;
2594 }
2595 else
2596 {
2597 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2598 }
2599 }
2600
2601 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2602
2603 return ERROR_OK;
2604 }
2605
2606 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2607 {
2608 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2609
2610 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2611
2612 arm_jtag_setup_connection(&arm7_9->jtag_info);
2613 arm7_9->wp_available = 2;
2614 arm7_9->wp0_used = 0;
2615 arm7_9->wp1_used = 0;
2616 arm7_9->force_hw_bkpts = 0;
2617 arm7_9->use_dbgrq = 0;
2618
2619 arm7_9->etm_ctx = NULL;
2620 arm7_9->has_single_step = 0;
2621 arm7_9->has_monitor_mode = 0;
2622 arm7_9->has_vector_catch = 0;
2623
2624 arm7_9->reinit_embeddedice = 0;
2625
2626 arm7_9->debug_entry_from_reset = 0;
2627
2628 arm7_9->dcc_working_area = NULL;
2629
2630 arm7_9->fast_memory_access = 0;
2631 arm7_9->dcc_downloads = 0;
2632
2633 jtag_register_event_callback(arm7_9_jtag_callback, target);
2634
2635 armv4_5->arch_info = arm7_9;
2636 armv4_5->read_core_reg = arm7_9_read_core_reg;
2637 armv4_5->write_core_reg = arm7_9_write_core_reg;
2638 armv4_5->full_context = arm7_9_full_context;
2639
2640 armv4_5_init_arch_info(target, armv4_5);
2641
2642 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2643
2644 return ERROR_OK;
2645 }
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