1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2008 by Hongtao Zheng *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
33 #include "breakpoints.h"
34 #include "embeddedice.h"
35 #include "target_request.h"
36 #include "arm7_9_common.h"
37 #include "time_support.h"
38 #include "arm_simulator.h"
43 * Hold common code supporting the ARM7 and ARM9 core generations.
45 * While the ARM core implementations evolved substantially during these
46 * two generations, they look quite similar from the JTAG perspective.
47 * Both have similar debug facilities, based on the same two scan chains
48 * providing access to the core and to an EmbeddedICE module. Both can
49 * support similar ETM and ETB modules, for tracing. And both expose
50 * what could be viewed as "ARM Classic", with multiple processor modes,
51 * shadowed registers, and support for the Thumb instruction set.
53 * Processor differences include things like presence or absence of MMU
54 * and cache, pipeline sizes, use of a modified Harvard Architecure
55 * (with separate instruction and data busses from the CPU), support
56 * for cpu clock gating during idle, and more.
59 static int arm7_9_debug_entry(struct target
*target
);
62 * Clear watchpoints for an ARM7/9 target.
64 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
65 * @return JTAG error status after executing queue
67 static int arm7_9_clear_watchpoints(struct arm7_9_common
*arm7_9
)
70 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
71 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
72 arm7_9
->sw_breakpoint_count
= 0;
73 arm7_9
->sw_breakpoints_added
= 0;
75 arm7_9
->wp1_used
= arm7_9
->wp1_used_default
;
76 arm7_9
->wp_available
= arm7_9
->wp_available_max
;
78 return jtag_execute_queue();
82 * Assign a watchpoint to one of the two available hardware comparators in an
83 * ARM7 or ARM9 target.
85 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
86 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
88 static void arm7_9_assign_wp(struct arm7_9_common
*arm7_9
, struct breakpoint
*breakpoint
)
90 if (!arm7_9
->wp0_used
)
94 arm7_9
->wp_available
--;
96 else if (!arm7_9
->wp1_used
)
100 arm7_9
->wp_available
--;
104 LOG_ERROR("BUG: no hardware comparator available");
106 LOG_DEBUG("BPID: %d (0x%08" PRIx32
") using hw wp: %d",
107 breakpoint
->unique_id
,
113 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
115 * @param arm7_9 Pointer to common struct for ARM7/9 targets
116 * @return Error codes if there is a problem finding a watchpoint or the result
117 * of executing the JTAG queue
119 static int arm7_9_set_software_breakpoints(struct arm7_9_common
*arm7_9
)
121 if (arm7_9
->sw_breakpoints_added
)
125 if (arm7_9
->wp_available
< 1)
127 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
128 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
130 arm7_9
->wp_available
--;
132 /* pick a breakpoint unit */
133 if (!arm7_9
->wp0_used
)
135 arm7_9
->sw_breakpoints_added
= 1;
136 arm7_9
->wp0_used
= 3;
137 } else if (!arm7_9
->wp1_used
)
139 arm7_9
->sw_breakpoints_added
= 2;
140 arm7_9
->wp1_used
= 3;
144 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
148 if (arm7_9
->sw_breakpoints_added
== 1)
150 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
151 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
152 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
153 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
154 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
156 else if (arm7_9
->sw_breakpoints_added
== 2)
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
161 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
162 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
166 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
169 LOG_DEBUG("SW BP using hw wp: %d",
170 arm7_9
->sw_breakpoints_added
);
172 return jtag_execute_queue();
176 * Setup the common pieces for an ARM7/9 target after reset or on startup.
178 * @param target Pointer to an ARM7/9 target to setup
179 * @return Result of clearing the watchpoints on the target
181 int arm7_9_setup(struct target
*target
)
183 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
185 return arm7_9_clear_watchpoints(arm7_9
);
189 * Set either a hardware or software breakpoint on an ARM7/9 target. The
190 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
191 * might have erased the values in Embedded ICE.
193 * @param target Pointer to the target device to set the breakpoints on
194 * @param breakpoint Pointer to the breakpoint to be set
195 * @return For hardware breakpoints, this is the result of executing the JTAG
196 * queue. For software breakpoints, this will be the status of the
197 * required memory reads and writes
199 int arm7_9_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
201 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
202 int retval
= ERROR_OK
;
204 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
", Type: %d" ,
205 breakpoint
->unique_id
,
209 if (target
->state
!= TARGET_HALTED
)
211 LOG_WARNING("target not halted");
212 return ERROR_TARGET_NOT_HALTED
;
215 if (breakpoint
->type
== BKPT_HARD
)
217 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
218 uint32_t mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
220 /* reassign a hw breakpoint */
221 if (breakpoint
->set
== 0)
223 arm7_9_assign_wp(arm7_9
, breakpoint
);
226 if (breakpoint
->set
== 1)
228 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
229 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
230 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
231 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
232 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
234 else if (breakpoint
->set
== 2)
236 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
237 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
238 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
239 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
240 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
244 LOG_ERROR("BUG: no hardware comparator available");
248 retval
= jtag_execute_queue();
250 else if (breakpoint
->type
== BKPT_SOFT
)
252 /* did we already set this breakpoint? */
256 if (breakpoint
->length
== 4)
258 uint32_t verify
= 0xffffffff;
259 /* keep the original instruction in target endianness */
260 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
264 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
265 if ((retval
= target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
)) != ERROR_OK
)
270 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
274 if (verify
!= arm7_9
->arm_bkpt
)
276 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
282 uint16_t verify
= 0xffff;
283 /* keep the original instruction in target endianness */
284 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
288 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
289 if ((retval
= target_write_u16(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
)) != ERROR_OK
)
294 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
298 if (verify
!= arm7_9
->thumb_bkpt
)
300 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
305 if ((retval
= arm7_9_set_software_breakpoints(arm7_9
)) != ERROR_OK
)
308 arm7_9
->sw_breakpoint_count
++;
317 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
318 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
319 * will be updated. Otherwise, the software breakpoint will be restored to its
320 * original instruction if it hasn't already been modified.
322 * @param target Pointer to ARM7/9 target to unset the breakpoint from
323 * @param breakpoint Pointer to breakpoint to be unset
324 * @return For hardware breakpoints, this is the result of executing the JTAG
325 * queue. For software breakpoints, this will be the status of the
326 * required memory reads and writes
328 int arm7_9_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
330 int retval
= ERROR_OK
;
331 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
333 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
,
334 breakpoint
->unique_id
,
335 breakpoint
->address
);
337 if (!breakpoint
->set
)
339 LOG_WARNING("breakpoint not set");
343 if (breakpoint
->type
== BKPT_HARD
)
345 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
346 breakpoint
->unique_id
,
348 if (breakpoint
->set
== 1)
350 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
351 arm7_9
->wp0_used
= 0;
352 arm7_9
->wp_available
++;
354 else if (breakpoint
->set
== 2)
356 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
357 arm7_9
->wp1_used
= 0;
358 arm7_9
->wp_available
++;
360 retval
= jtag_execute_queue();
365 /* restore original instruction (kept in target endianness) */
366 if (breakpoint
->length
== 4)
368 uint32_t current_instr
;
369 /* check that user program as not modified breakpoint instruction */
370 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
374 if (current_instr
== arm7_9
->arm_bkpt
)
375 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
382 uint16_t current_instr
;
383 /* check that user program as not modified breakpoint instruction */
384 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
388 if (current_instr
== arm7_9
->thumb_bkpt
)
389 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
395 if (--arm7_9
->sw_breakpoint_count
==0)
397 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
398 if (arm7_9
->sw_breakpoints_added
== 1)
400 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0);
402 else if (arm7_9
->sw_breakpoints_added
== 2)
404 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0);
415 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
416 * dangling breakpoints and that the desired breakpoint can be added.
418 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
419 * @param breakpoint Pointer to the breakpoint to be added
420 * @return An error status if there is a problem adding the breakpoint or the
421 * result of setting the breakpoint
423 int arm7_9_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
425 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
427 if (target
->state
!= TARGET_HALTED
)
429 LOG_WARNING("target not halted");
430 return ERROR_TARGET_NOT_HALTED
;
433 if (arm7_9
->breakpoint_count
== 0)
435 /* make sure we don't have any dangling breakpoints. This is vital upon
436 * GDB connect/disconnect
438 arm7_9_clear_watchpoints(arm7_9
);
441 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
443 LOG_INFO("no watchpoint unit available for hardware breakpoint");
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
447 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
449 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
450 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
453 if (breakpoint
->type
== BKPT_HARD
)
455 arm7_9_assign_wp(arm7_9
, breakpoint
);
458 arm7_9
->breakpoint_count
++;
460 return arm7_9_set_breakpoint(target
, breakpoint
);
464 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
465 * dangling breakpoints and updates available watchpoints if it is a hardware
468 * @param target Pointer to the target to have a breakpoint removed
469 * @param breakpoint Pointer to the breakpoint to be removed
470 * @return Error status if there was a problem unsetting the breakpoint or the
471 * watchpoints could not be cleared
473 int arm7_9_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
475 int retval
= ERROR_OK
;
476 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
478 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
483 if (breakpoint
->type
== BKPT_HARD
)
484 arm7_9
->wp_available
++;
486 arm7_9
->breakpoint_count
--;
487 if (arm7_9
->breakpoint_count
== 0)
489 /* make sure we don't have any dangling breakpoints */
490 if ((retval
= arm7_9_clear_watchpoints(arm7_9
)) != ERROR_OK
)
500 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
501 * considered a bug to call this function when there are no available watchpoint
504 * @param target Pointer to an ARM7/9 target to set a watchpoint on
505 * @param watchpoint Pointer to the watchpoint to be set
506 * @return Error status if watchpoint set fails or the result of executing the
509 int arm7_9_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
511 int retval
= ERROR_OK
;
512 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
516 mask
= watchpoint
->length
- 1;
518 if (target
->state
!= TARGET_HALTED
)
520 LOG_WARNING("target not halted");
521 return ERROR_TARGET_NOT_HALTED
;
524 if (watchpoint
->rw
== WPT_ACCESS
)
529 if (!arm7_9
->wp0_used
)
531 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
532 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
533 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
534 if (watchpoint
->mask
!= 0xffffffffu
)
535 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
536 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
537 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
539 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
544 arm7_9
->wp0_used
= 2;
546 else if (!arm7_9
->wp1_used
)
548 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
549 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
550 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
551 if (watchpoint
->mask
!= 0xffffffffu
)
552 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
553 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
554 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
556 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
561 arm7_9
->wp1_used
= 2;
565 LOG_ERROR("BUG: no hardware comparator available");
573 * Unset an existing watchpoint and clear the used watchpoint unit.
575 * @param target Pointer to the target to have the watchpoint removed
576 * @param watchpoint Pointer to the watchpoint to be removed
577 * @return Error status while trying to unset the watchpoint or the result of
578 * executing the JTAG queue
580 int arm7_9_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
582 int retval
= ERROR_OK
;
583 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
585 if (target
->state
!= TARGET_HALTED
)
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED
;
591 if (!watchpoint
->set
)
593 LOG_WARNING("breakpoint not set");
597 if (watchpoint
->set
== 1)
599 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
600 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
604 arm7_9
->wp0_used
= 0;
606 else if (watchpoint
->set
== 2)
608 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
609 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
613 arm7_9
->wp1_used
= 0;
621 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
622 * available, an error response is returned.
624 * @param target Pointer to the ARM7/9 target to add a watchpoint to
625 * @param watchpoint Pointer to the watchpoint to be added
626 * @return Error status while trying to add the watchpoint
628 int arm7_9_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
630 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
632 if (target
->state
!= TARGET_HALTED
)
634 LOG_WARNING("target not halted");
635 return ERROR_TARGET_NOT_HALTED
;
638 if (arm7_9
->wp_available
< 1)
640 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
643 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
645 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
648 arm7_9
->wp_available
--;
654 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
655 * the used watchpoint unit will be reopened.
657 * @param target Pointer to the target to remove a watchpoint from
658 * @param watchpoint Pointer to the watchpoint to be removed
659 * @return Result of trying to unset the watchpoint
661 int arm7_9_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
663 int retval
= ERROR_OK
;
664 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
668 if ((retval
= arm7_9_unset_watchpoint(target
, watchpoint
)) != ERROR_OK
)
674 arm7_9
->wp_available
++;
680 * Restarts the target by sending a RESTART instruction and moving the JTAG
681 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
682 * asserted by the processor.
684 * @param target Pointer to target to issue commands to
685 * @return Error status if there is a timeout or a problem while executing the
688 int arm7_9_execute_sys_speed(struct target
*target
)
691 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
692 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
693 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
695 /* set RESTART instruction */
696 jtag_set_end_state(TAP_IDLE
);
697 if (arm7_9
->need_bypass_before_restart
) {
698 arm7_9
->need_bypass_before_restart
= 0;
699 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
701 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
703 long long then
= timeval_ms();
705 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
707 /* read debug status register */
708 embeddedice_read_reg(dbg_stat
);
709 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
711 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
712 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
714 if (debug_level
>= 3)
724 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32
"", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
725 return ERROR_TARGET_TIMEOUT
;
732 * Restarts the target by sending a RESTART instruction and moving the JTAG
733 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
734 * waiting until they are.
736 * @param target Pointer to the target to issue commands to
737 * @return Always ERROR_OK
739 int arm7_9_execute_fast_sys_speed(struct target
*target
)
742 static uint8_t check_value
[4], check_mask
[4];
744 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
745 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
746 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
748 /* set RESTART instruction */
749 jtag_set_end_state(TAP_IDLE
);
750 if (arm7_9
->need_bypass_before_restart
) {
751 arm7_9
->need_bypass_before_restart
= 0;
752 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
754 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
758 /* check for DBGACK and SYSCOMP set (others don't care) */
760 /* NB! These are constants that must be available until after next jtag_execute() and
761 * we evaluate the values upon first execution in lieu of setting up these constants
762 * during early setup.
764 buf_set_u32(check_value
, 0, 32, 0x9);
765 buf_set_u32(check_mask
, 0, 32, 0x9);
769 /* read debug status register */
770 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_mask
);
776 * Get some data from the ARM7/9 target.
778 * @param target Pointer to the ARM7/9 target to read data from
779 * @param size The number of 32bit words to be read
780 * @param buffer Pointer to the buffer that will hold the data
781 * @return The result of receiving data from the Embedded ICE unit
783 int arm7_9_target_request_data(struct target
*target
, uint32_t size
, uint8_t *buffer
)
785 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
786 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
788 int retval
= ERROR_OK
;
791 data
= malloc(size
* (sizeof(uint32_t)));
793 retval
= embeddedice_receive(jtag_info
, data
, size
);
795 /* return the 32-bit ints in the 8-bit array */
796 for (i
= 0; i
< size
; i
++)
798 h_u32_to_le(buffer
+ (i
* 4), data
[i
]);
807 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
808 * target is running and the DCC control register has the W bit high, this will
809 * execute the request on the target.
811 * @param priv Void pointer expected to be a struct target pointer
812 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
813 * from the Embedded ICE unit
815 int arm7_9_handle_target_request(void *priv
)
817 int retval
= ERROR_OK
;
818 struct target
*target
= priv
;
819 if (!target_was_examined(target
))
821 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
822 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
823 struct reg
*dcc_control
= &arm7_9
->eice_cache
->reg_list
[EICE_COMMS_CTRL
];
825 if (!target
->dbg_msg_enabled
)
828 if (target
->state
== TARGET_RUNNING
)
830 /* read DCC control register */
831 embeddedice_read_reg(dcc_control
);
832 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
838 if (buf_get_u32(dcc_control
->value
, 1, 1) == 1)
842 if ((retval
= embeddedice_receive(jtag_info
, &request
, 1)) != ERROR_OK
)
846 if ((retval
= target_request(target
, request
)) != ERROR_OK
)
857 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
858 * is manipulated to the right halted state based on its current state. This is
862 * <tr><th > State</th><th > Action</th></tr>
863 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
864 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
865 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
866 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
869 * If the target does not end up in the halted state, a warning is produced. If
870 * DBGACK is cleared, then the target is expected to either be running or
873 * @param target Pointer to the ARM7/9 target to poll
874 * @return ERROR_OK or an error status if a command fails
876 int arm7_9_poll(struct target
*target
)
879 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
880 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
882 /* read debug status register */
883 embeddedice_read_reg(dbg_stat
);
884 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
889 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
891 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
892 if (target
->state
== TARGET_UNKNOWN
)
894 /* Starting OpenOCD with target in debug-halt */
895 target
->state
= TARGET_RUNNING
;
896 LOG_DEBUG("DBGACK already set during server startup.");
898 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
901 if (target
->state
== TARGET_RESET
)
903 if (target
->reset_halt
)
905 enum reset_types jtag_reset_config
= jtag_get_reset_config();
906 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0)
913 target
->state
= TARGET_HALTED
;
915 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
920 struct reg
*reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
921 uint32_t t
=*((uint32_t *)reg
->value
);
924 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
928 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
933 if (target
->state
== TARGET_DEBUG_RUNNING
)
935 target
->state
= TARGET_HALTED
;
936 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
939 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
)) != ERROR_OK
)
944 if (target
->state
!= TARGET_HALTED
)
946 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target
->state
);
951 if (target
->state
!= TARGET_DEBUG_RUNNING
)
952 target
->state
= TARGET_RUNNING
;
959 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
960 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
961 * affected) completely stop the JTAG clock while the core is held in reset
962 * (SRST). It isn't possible to program the halt condition once reset is
963 * asserted, hence a hook that allows the target to set up its reset-halt
964 * condition is setup prior to asserting reset.
966 * @param target Pointer to an ARM7/9 target to assert reset on
967 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
969 int arm7_9_assert_reset(struct target
*target
)
971 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
973 LOG_DEBUG("target->state: %s",
974 target_state_name(target
));
976 enum reset_types jtag_reset_config
= jtag_get_reset_config();
977 if (!(jtag_reset_config
& RESET_HAS_SRST
))
979 LOG_ERROR("Can't assert SRST");
983 /* At this point trst has been asserted/deasserted once. We would
984 * like to program EmbeddedICE while SRST is asserted, instead of
985 * depending on SRST to leave that module alone. However, many CPUs
986 * gate the JTAG clock while SRST is asserted; or JTAG may need
987 * clock stability guarantees (adaptive clocking might help).
989 * So we assume JTAG access during SRST is off the menu unless it's
990 * been specifically enabled.
992 bool srst_asserted
= false;
994 if (((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0)
995 && (jtag_reset_config
& RESET_SRST_NO_GATING
))
997 jtag_add_reset(0, 1);
998 srst_asserted
= true;
1001 if (target
->reset_halt
)
1004 * Some targets do not support communication while SRST is asserted. We need to
1005 * set up the reset vector catch here.
1007 * If TRST is asserted, then these settings will be reset anyway, so setting them
1010 if (arm7_9
->has_vector_catch
)
1012 /* program vector catch register to catch reset vector */
1013 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
], 0x1);
1015 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1016 jtag_add_runtest(1, jtag_get_end_state());
1020 /* program watchpoint unit to match on reset vector address */
1021 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], 0x0);
1022 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0x3);
1023 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1024 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1025 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1029 /* here we should issue an SRST only, but we may have to assert TRST as well */
1030 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1032 jtag_add_reset(1, 1);
1033 } else if (!srst_asserted
)
1035 jtag_add_reset(0, 1);
1038 target
->state
= TARGET_RESET
;
1039 jtag_add_sleep(50000);
1041 armv4_5_invalidate_core_regs(target
);
1043 if ((target
->reset_halt
) && ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0))
1045 /* debug entry was already prepared in arm7_9_assert_reset() */
1046 target
->debug_reason
= DBG_REASON_DBGRQ
;
1053 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1054 * and the target is being reset into a halt, a warning will be triggered
1055 * because it is not possible to reset into a halted mode in this case. The
1056 * target is halted using the target's functions.
1058 * @param target Pointer to the target to have the reset deasserted
1059 * @return ERROR_OK or an error from polling or halting the target
1061 int arm7_9_deassert_reset(struct target
*target
)
1063 int retval
= ERROR_OK
;
1064 LOG_DEBUG("target->state: %s",
1065 target_state_name(target
));
1067 /* deassert reset lines */
1068 jtag_add_reset(0, 0);
1070 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1071 if (target
->reset_halt
&& (jtag_reset_config
& RESET_SRST_PULLS_TRST
) != 0)
1073 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1074 /* set up embedded ice registers again */
1075 if ((retval
= target_examine_one(target
)) != ERROR_OK
)
1078 if ((retval
= target_poll(target
)) != ERROR_OK
)
1083 if ((retval
= target_halt(target
)) != ERROR_OK
)
1093 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1094 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1095 * vector catch was used, it is restored. Otherwise, the control value is
1096 * restored and the watchpoint unit is restored if it was in use.
1098 * @param target Pointer to the ARM7/9 target to have halt cleared
1099 * @return Always ERROR_OK
1101 int arm7_9_clear_halt(struct target
*target
)
1103 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1104 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1106 /* we used DBGRQ only if we didn't come out of reset */
1107 if (!arm7_9
->debug_entry_from_reset
&& arm7_9
->use_dbgrq
)
1109 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1111 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1112 embeddedice_store_reg(dbg_ctrl
);
1116 if (arm7_9
->debug_entry_from_reset
&& arm7_9
->has_vector_catch
)
1118 /* if we came out of reset, and vector catch is supported, we used
1119 * vector catch to enter debug state
1120 * restore the register in that case
1122 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
]);
1126 /* restore registers if watchpoint unit 0 was in use
1128 if (arm7_9
->wp0_used
)
1130 if (arm7_9
->debug_entry_from_reset
)
1132 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
]);
1134 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1135 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1136 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1138 /* control value always has to be restored, as it was either disabled,
1139 * or enabled with possibly different bits
1141 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1149 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1150 * and then there is a wait until the processor shows the halt. This wait can
1151 * timeout and results in an error being returned. The software reset involves
1152 * clearing the halt, updating the debug control register, changing to ARM mode,
1153 * reset of the program counter, and reset of all of the registers.
1155 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1156 * @return Error status if any of the commands fail, otherwise ERROR_OK
1158 int arm7_9_soft_reset_halt(struct target
*target
)
1160 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1161 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1162 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1163 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1167 /* FIX!!! replace some of this code with tcl commands
1169 * halt # the halt command is synchronous
1170 * armv4_5 core_state arm
1174 if ((retval
= target_halt(target
)) != ERROR_OK
)
1177 long long then
= timeval_ms();
1179 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
1181 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) != 0)
1183 embeddedice_read_reg(dbg_stat
);
1184 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1186 if (debug_level
>= 3)
1196 LOG_ERROR("Failed to halt CPU after 1 sec");
1197 return ERROR_TARGET_TIMEOUT
;
1199 target
->state
= TARGET_HALTED
;
1201 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1202 * ensure that DBGRQ is cleared
1204 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1205 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1206 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1207 embeddedice_store_reg(dbg_ctrl
);
1209 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1214 /* if the target is in Thumb state, change to ARM state */
1215 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1217 uint32_t r0_thumb
, pc_thumb
;
1218 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1219 /* Entered debug from Thumb mode */
1220 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1221 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1224 /* all register content is now invalid */
1225 if ((retval
= armv4_5_invalidate_core_regs(target
)) != ERROR_OK
)
1230 /* SVC, ARM state, IRQ and FIQ disabled */
1231 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
1232 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1233 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1235 /* start fetching from 0x0 */
1236 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
1237 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1238 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1240 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
1241 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1243 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1246 /* reset registers */
1247 for (i
= 0; i
<= 14; i
++)
1249 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
1250 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1251 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1254 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
1263 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1264 * line or by programming a watchpoint to trigger on any address. It is
1265 * considered a bug to call this function while the target is in the
1266 * TARGET_RESET state.
1268 * @param target Pointer to the ARM7/9 target to be halted
1269 * @return Always ERROR_OK
1271 int arm7_9_halt(struct target
*target
)
1273 if (target
->state
== TARGET_RESET
)
1275 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1279 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1280 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1282 LOG_DEBUG("target->state: %s",
1283 target_state_name(target
));
1285 if (target
->state
== TARGET_HALTED
)
1287 LOG_DEBUG("target was already halted");
1291 if (target
->state
== TARGET_UNKNOWN
)
1293 LOG_WARNING("target was in unknown state when halt was requested");
1296 if (arm7_9
->use_dbgrq
)
1298 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1300 if (arm7_9
->set_special_dbgrq
) {
1301 arm7_9
->set_special_dbgrq(target
);
1303 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
1304 embeddedice_store_reg(dbg_ctrl
);
1309 /* program watchpoint unit to match on any address
1311 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1312 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1313 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1314 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1317 target
->debug_reason
= DBG_REASON_DBGRQ
;
1323 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1324 * ARM. The JTAG queue is then executed and the reason for debug entry is
1325 * examined. Once done, the target is verified to be halted and the processor
1326 * is forced into ARM mode. The core registers are saved for the current core
1327 * mode and the program counter (register 15) is updated as needed. The core
1328 * registers and CPSR and SPSR are saved for restoration later.
1330 * @param target Pointer to target that is entering debug mode
1331 * @return Error code if anything fails, otherwise ERROR_OK
1333 static int arm7_9_debug_entry(struct target
*target
)
1336 uint32_t context
[16];
1337 uint32_t* context_p
[16];
1338 uint32_t r0_thumb
, pc_thumb
;
1341 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1342 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1343 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1344 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1346 #ifdef _DEBUG_ARM7_9_
1350 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1351 * ensure that DBGRQ is cleared
1353 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1354 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1355 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1356 embeddedice_store_reg(dbg_ctrl
);
1358 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1363 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1368 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
1372 if (target
->state
!= TARGET_HALTED
)
1374 LOG_WARNING("target not halted");
1375 return ERROR_TARGET_NOT_HALTED
;
1378 /* if the target is in Thumb state, change to ARM state */
1379 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1381 LOG_DEBUG("target entered debug from Thumb state");
1382 /* Entered debug from Thumb mode */
1383 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1384 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1385 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
", pc_thumb: 0x%8.8" PRIx32
"", r0_thumb
, pc_thumb
);
1389 LOG_DEBUG("target entered debug from ARM state");
1390 /* Entered debug from ARM mode */
1391 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1394 for (i
= 0; i
< 16; i
++)
1395 context_p
[i
] = &context
[i
];
1396 /* save core registers (r0 - r15 of current core mode) */
1397 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
1399 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1401 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1404 /* if the core has been executing in Thumb state, set the T bit */
1405 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1408 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
1409 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1410 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1412 armv4_5
->core_mode
= cpsr
& 0x1f;
1414 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1416 target
->state
= TARGET_UNKNOWN
;
1417 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1418 return ERROR_TARGET_FAILURE
;
1421 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1423 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1425 LOG_DEBUG("thumb state, applying fixups");
1426 context
[0] = r0_thumb
;
1427 context
[15] = pc_thumb
;
1428 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1430 /* adjust value stored by STM */
1431 context
[15] -= 3 * 4;
1434 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
) || (!arm7_9
->use_dbgrq
))
1435 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1437 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1439 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1442 for (i
= 0; i
<= 15; i
++)
1444 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, context
[i
]);
1445 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1446 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1447 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1450 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
"", context
[15]);
1452 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1455 /* exceptions other than USR & SYS have a saved program status register */
1456 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1459 arm7_9
->read_xpsr(target
, &spsr
, 1);
1460 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1464 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1465 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1466 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1469 /* r0 and r15 (pc) have to be restored later */
1470 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1471 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).valid
;
1473 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1476 if (arm7_9
->post_debug_entry
)
1477 arm7_9
->post_debug_entry(target
);
1483 * Validate the full context for an ARM7/9 target in all processor modes. If
1484 * there are any invalid registers for the target, they will all be read. This
1487 * @param target Pointer to the ARM7/9 target to capture the full context from
1488 * @return Error if the target is not halted, has an invalid core mode, or if
1489 * the JTAG queue fails to execute
1491 int arm7_9_full_context(struct target
*target
)
1495 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1496 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1500 if (target
->state
!= TARGET_HALTED
)
1502 LOG_WARNING("target not halted");
1503 return ERROR_TARGET_NOT_HALTED
;
1506 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1509 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1510 * SYS shares registers with User, so we don't touch SYS
1512 for (i
= 0; i
< 6; i
++)
1515 uint32_t* reg_p
[16];
1519 /* check if there are invalid registers in the current mode
1521 for (j
= 0; j
<= 16; j
++)
1523 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1531 /* change processor mode (and mask T bit) */
1532 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1533 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1535 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1537 for (j
= 0; j
< 15; j
++)
1539 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1541 reg_p
[j
] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1543 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1544 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1548 /* if only the PSR is invalid, mask is all zeroes */
1550 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1552 /* check if the PSR has to be read */
1553 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1555 arm7_9
->read_xpsr(target
, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1556 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1557 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1562 /* restore processor mode (mask T bit) */
1563 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1565 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1573 * Restore the processor context on an ARM7/9 target. The full processor
1574 * context is analyzed to see if any of the registers are dirty on this end, but
1575 * have a valid new value. If this is the case, the processor is changed to the
1576 * appropriate mode and the new register values are written out to the
1577 * processor. If there happens to be a dirty register with an invalid value, an
1578 * error will be logged.
1580 * @param target Pointer to the ARM7/9 target to have its context restored
1581 * @return Error status if the target is not halted or the core mode in the
1582 * armv4_5 struct is invalid.
1584 int arm7_9_restore_context(struct target
*target
)
1586 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1587 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1589 struct armv4_5_core_reg
*reg_arch_info
;
1590 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1597 if (target
->state
!= TARGET_HALTED
)
1599 LOG_WARNING("target not halted");
1600 return ERROR_TARGET_NOT_HALTED
;
1603 if (arm7_9
->pre_restore_context
)
1604 arm7_9
->pre_restore_context(target
);
1606 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1609 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1610 * SYS shares registers with User, so we don't touch SYS
1612 for (i
= 0; i
< 6; i
++)
1614 LOG_DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1617 /* check if there are dirty registers in the current mode
1619 for (j
= 0; j
<= 16; j
++)
1621 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1622 reg_arch_info
= reg
->arch_info
;
1623 if (reg
->dirty
== 1)
1625 if (reg
->valid
== 1)
1628 LOG_DEBUG("examining dirty reg: %s", reg
->name
);
1629 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1630 && (reg_arch_info
->mode
!= current_mode
)
1631 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1632 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1635 LOG_DEBUG("require mode change");
1640 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1647 uint32_t mask
= 0x0;
1655 /* change processor mode (mask T bit) */
1656 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1657 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1659 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1660 current_mode
= armv4_5_number_to_mode(i
);
1663 for (j
= 0; j
<= 14; j
++)
1665 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1666 reg_arch_info
= reg
->arch_info
;
1669 if (reg
->dirty
== 1)
1671 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1676 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32
"", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1682 arm7_9
->write_core_regs(target
, mask
, regs
);
1685 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1686 reg_arch_info
= reg
->arch_info
;
1687 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1689 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(reg
->value
, 0, 32));
1690 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1695 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1697 /* restore processor mode (mask T bit) */
1700 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1701 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1703 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr
));
1704 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1706 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1708 /* CPSR has been changed, full restore necessary (mask T bit) */
1709 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1710 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1711 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1712 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1716 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1717 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1718 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1720 if (arm7_9
->post_restore_context
)
1721 arm7_9
->post_restore_context(target
);
1727 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1728 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1731 * @param target Pointer to the ARM7/9 target to be restarted
1732 * @return Result of executing the JTAG queue
1734 int arm7_9_restart_core(struct target
*target
)
1736 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1737 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
1739 /* set RESTART instruction */
1740 jtag_set_end_state(TAP_IDLE
);
1741 if (arm7_9
->need_bypass_before_restart
) {
1742 arm7_9
->need_bypass_before_restart
= 0;
1743 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
1745 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
1747 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE
));
1748 return jtag_execute_queue();
1752 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1753 * iterated through and are set on the target if they aren't already set.
1755 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1757 void arm7_9_enable_watchpoints(struct target
*target
)
1759 struct watchpoint
*watchpoint
= target
->watchpoints
;
1763 if (watchpoint
->set
== 0)
1764 arm7_9_set_watchpoint(target
, watchpoint
);
1765 watchpoint
= watchpoint
->next
;
1770 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1771 * iterated through and are set on the target.
1773 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1775 void arm7_9_enable_breakpoints(struct target
*target
)
1777 struct breakpoint
*breakpoint
= target
->breakpoints
;
1779 /* set any pending breakpoints */
1782 arm7_9_set_breakpoint(target
, breakpoint
);
1783 breakpoint
= breakpoint
->next
;
1787 int arm7_9_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1789 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1790 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1791 struct breakpoint
*breakpoint
= target
->breakpoints
;
1792 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1793 int err
, retval
= ERROR_OK
;
1797 if (target
->state
!= TARGET_HALTED
)
1799 LOG_WARNING("target not halted");
1800 return ERROR_TARGET_NOT_HALTED
;
1803 if (!debug_execution
)
1805 target_free_all_working_areas(target
);
1808 /* current = 1: continue on current pc, otherwise continue at <address> */
1810 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1812 uint32_t current_pc
;
1813 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1815 /* the front-end may request us not to handle breakpoints */
1816 if (handle_breakpoints
)
1818 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1820 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (id: %d)", breakpoint
->address
, breakpoint
->unique_id
);
1821 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1826 /* calculate PC of next instruction */
1828 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1830 uint32_t current_opcode
;
1831 target_read_u32(target
, current_pc
, ¤t_opcode
);
1832 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1836 LOG_DEBUG("enable single-step");
1837 arm7_9
->enable_single_step(target
, next_pc
);
1839 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1841 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1846 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1847 arm7_9
->branch_resume(target
);
1848 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1850 arm7_9
->branch_resume_thumb(target
);
1854 LOG_ERROR("unhandled core state");
1858 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1859 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1860 err
= arm7_9_execute_sys_speed(target
);
1862 LOG_DEBUG("disable single-step");
1863 arm7_9
->disable_single_step(target
);
1865 if (err
!= ERROR_OK
)
1867 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1871 target
->state
= TARGET_UNKNOWN
;
1875 arm7_9_debug_entry(target
);
1876 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1878 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1879 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1886 /* enable any pending breakpoints and watchpoints */
1887 arm7_9_enable_breakpoints(target
);
1888 arm7_9_enable_watchpoints(target
);
1890 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1895 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1897 arm7_9
->branch_resume(target
);
1899 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1901 arm7_9
->branch_resume_thumb(target
);
1905 LOG_ERROR("unhandled core state");
1909 /* deassert DBGACK and INTDIS */
1910 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1911 /* INTDIS only when we really resume, not during debug execution */
1912 if (!debug_execution
)
1913 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1914 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1916 if ((retval
= arm7_9_restart_core(target
)) != ERROR_OK
)
1921 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1923 if (!debug_execution
)
1925 /* registers are now invalid */
1926 armv4_5_invalidate_core_regs(target
);
1927 target
->state
= TARGET_RUNNING
;
1928 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
1935 target
->state
= TARGET_DEBUG_RUNNING
;
1936 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
)) != ERROR_OK
)
1942 LOG_DEBUG("target resumed");
1947 void arm7_9_enable_eice_step(struct target
*target
, uint32_t next_pc
)
1949 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1950 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1951 uint32_t current_pc
;
1952 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1954 if (next_pc
!= current_pc
)
1956 /* setup an inverse breakpoint on the current PC
1957 * - comparator 1 matches the current address
1958 * - rangeout from comparator 1 is connected to comparator 0 rangein
1959 * - comparator 0 matches any address, as long as rangein is low */
1960 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1961 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1962 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1963 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~(EICE_W_CTRL_RANGE
| EICE_W_CTRL_nOPC
) & 0xff);
1964 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], current_pc
);
1965 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1966 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1967 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1968 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1972 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1974 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
1975 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff);
1976 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], next_pc
);
1977 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1978 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1979 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1980 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1984 void arm7_9_disable_eice_step(struct target
*target
)
1986 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1988 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1989 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1990 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1991 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1992 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1993 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1994 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1995 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1996 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1999 int arm7_9_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
2001 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2002 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2003 struct breakpoint
*breakpoint
= NULL
;
2006 if (target
->state
!= TARGET_HALTED
)
2008 LOG_WARNING("target not halted");
2009 return ERROR_TARGET_NOT_HALTED
;
2012 /* current = 1: continue on current pc, otherwise continue at <address> */
2014 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
2016 uint32_t current_pc
;
2017 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2019 /* the front-end may request us not to handle breakpoints */
2020 if (handle_breakpoints
)
2021 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
2022 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2027 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2029 /* calculate PC of next instruction */
2031 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
2033 uint32_t current_opcode
;
2034 target_read_u32(target
, current_pc
, ¤t_opcode
);
2035 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
2039 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
2044 arm7_9
->enable_single_step(target
, next_pc
);
2046 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
2048 arm7_9
->branch_resume(target
);
2050 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
2052 arm7_9
->branch_resume_thumb(target
);
2056 LOG_ERROR("unhandled core state");
2060 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
2065 err
= arm7_9_execute_sys_speed(target
);
2066 arm7_9
->disable_single_step(target
);
2068 /* registers are now invalid */
2069 armv4_5_invalidate_core_regs(target
);
2071 if (err
!= ERROR_OK
)
2073 target
->state
= TARGET_UNKNOWN
;
2075 arm7_9_debug_entry(target
);
2076 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
2080 LOG_DEBUG("target stepped");
2084 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2092 int arm7_9_read_core_reg(struct target
*target
, int num
, enum armv4_5_mode mode
)
2094 uint32_t* reg_p
[16];
2097 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2098 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2100 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2103 enum armv4_5_mode reg_mode
= ((struct armv4_5_core_reg
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
2105 if ((num
< 0) || (num
> 16))
2106 return ERROR_INVALID_ARGUMENTS
;
2108 if ((mode
!= ARMV4_5_MODE_ANY
)
2109 && (mode
!= armv4_5
->core_mode
)
2110 && (reg_mode
!= ARMV4_5_MODE_ANY
))
2114 /* change processor mode (mask T bit) */
2115 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
2118 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2121 if ((num
>= 0) && (num
<= 15))
2123 /* read a normal core register */
2124 reg_p
[num
] = &value
;
2126 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
2130 /* read a program status register
2131 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2133 struct armv4_5_core_reg
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
2134 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
2136 arm7_9
->read_xpsr(target
, &value
, spsr
);
2139 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2144 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
2145 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
2146 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
2148 if ((mode
!= ARMV4_5_MODE_ANY
)
2149 && (mode
!= armv4_5
->core_mode
)
2150 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2151 /* restore processor mode (mask T bit) */
2152 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2158 int arm7_9_write_core_reg(struct target
*target
, int num
, enum armv4_5_mode mode
, uint32_t value
)
2161 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2162 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2164 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2167 enum armv4_5_mode reg_mode
= ((struct armv4_5_core_reg
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
2169 if ((num
< 0) || (num
> 16))
2170 return ERROR_INVALID_ARGUMENTS
;
2172 if ((mode
!= ARMV4_5_MODE_ANY
)
2173 && (mode
!= armv4_5
->core_mode
)
2174 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2177 /* change processor mode (mask T bit) */
2178 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
2181 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2184 if ((num
>= 0) && (num
<= 15))
2186 /* write a normal core register */
2189 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
2193 /* write a program status register
2194 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2196 struct armv4_5_core_reg
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
2197 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
2199 /* if we're writing the CPSR, mask the T bit */
2203 arm7_9
->write_xpsr(target
, value
, spsr
);
2206 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
2207 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
2209 if ((mode
!= ARMV4_5_MODE_ANY
)
2210 && (mode
!= armv4_5
->core_mode
)
2211 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2212 /* restore processor mode (mask T bit) */
2213 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2216 return jtag_execute_queue();
2219 int arm7_9_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2221 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2222 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2224 uint32_t num_accesses
= 0;
2225 int thisrun_accesses
;
2231 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
2233 if (target
->state
!= TARGET_HALTED
)
2235 LOG_WARNING("target not halted");
2236 return ERROR_TARGET_NOT_HALTED
;
2239 /* sanitize arguments */
2240 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2241 return ERROR_INVALID_ARGUMENTS
;
2243 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2244 return ERROR_TARGET_UNALIGNED_ACCESS
;
2246 /* load the base register with the address of the first word */
2248 arm7_9
->write_core_regs(target
, 0x1, reg
);
2255 while (num_accesses
< count
)
2258 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2259 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2261 if (last_reg
<= thisrun_accesses
)
2262 last_reg
= thisrun_accesses
;
2264 arm7_9
->load_word_regs(target
, reg_list
);
2266 /* fast memory reads are only safe when the target is running
2267 * from a sufficiently high clock (32 kHz is usually too slow)
2269 if (arm7_9
->fast_memory_access
)
2270 retval
= arm7_9_execute_fast_sys_speed(target
);
2272 retval
= arm7_9_execute_sys_speed(target
);
2273 if (retval
!= ERROR_OK
)
2276 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
2278 /* advance buffer, count number of accesses */
2279 buffer
+= thisrun_accesses
* 4;
2280 num_accesses
+= thisrun_accesses
;
2282 if ((j
++%1024) == 0)
2289 while (num_accesses
< count
)
2292 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2293 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2295 for (i
= 1; i
<= thisrun_accesses
; i
++)
2299 arm7_9
->load_hword_reg(target
, i
);
2300 /* fast memory reads are only safe when the target is running
2301 * from a sufficiently high clock (32 kHz is usually too slow)
2303 if (arm7_9
->fast_memory_access
)
2304 retval
= arm7_9_execute_fast_sys_speed(target
);
2306 retval
= arm7_9_execute_sys_speed(target
);
2307 if (retval
!= ERROR_OK
)
2314 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
2316 /* advance buffer, count number of accesses */
2317 buffer
+= thisrun_accesses
* 2;
2318 num_accesses
+= thisrun_accesses
;
2320 if ((j
++%1024) == 0)
2327 while (num_accesses
< count
)
2330 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2331 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2333 for (i
= 1; i
<= thisrun_accesses
; i
++)
2337 arm7_9
->load_byte_reg(target
, i
);
2338 /* fast memory reads are only safe when the target is running
2339 * from a sufficiently high clock (32 kHz is usually too slow)
2341 if (arm7_9
->fast_memory_access
)
2342 retval
= arm7_9_execute_fast_sys_speed(target
);
2344 retval
= arm7_9_execute_sys_speed(target
);
2345 if (retval
!= ERROR_OK
)
2351 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
2353 /* advance buffer, count number of accesses */
2354 buffer
+= thisrun_accesses
* 1;
2355 num_accesses
+= thisrun_accesses
;
2357 if ((j
++%1024) == 0)
2364 LOG_ERROR("BUG: we shouldn't get here");
2369 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2372 for (i
= 0; i
<= last_reg
; i
++)
2373 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2375 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2376 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2378 LOG_ERROR("JTAG error while reading cpsr");
2379 return ERROR_TARGET_DATA_ABORT
;
2382 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2384 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2386 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2388 return ERROR_TARGET_DATA_ABORT
;
2394 int arm7_9_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2396 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2397 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2398 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
2401 uint32_t num_accesses
= 0;
2402 int thisrun_accesses
;
2408 #ifdef _DEBUG_ARM7_9_
2409 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
2412 if (target
->state
!= TARGET_HALTED
)
2414 LOG_WARNING("target not halted");
2415 return ERROR_TARGET_NOT_HALTED
;
2418 /* sanitize arguments */
2419 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2420 return ERROR_INVALID_ARGUMENTS
;
2422 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2423 return ERROR_TARGET_UNALIGNED_ACCESS
;
2425 /* load the base register with the address of the first word */
2427 arm7_9
->write_core_regs(target
, 0x1, reg
);
2429 /* Clear DBGACK, to make sure memory fetches work as expected */
2430 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
2431 embeddedice_store_reg(dbg_ctrl
);
2436 while (num_accesses
< count
)
2439 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2440 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2442 for (i
= 1; i
<= thisrun_accesses
; i
++)
2446 reg
[i
] = target_buffer_get_u32(target
, buffer
);
2450 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2452 arm7_9
->store_word_regs(target
, reg_list
);
2454 /* fast memory writes are only safe when the target is running
2455 * from a sufficiently high clock (32 kHz is usually too slow)
2457 if (arm7_9
->fast_memory_access
)
2458 retval
= arm7_9_execute_fast_sys_speed(target
);
2460 retval
= arm7_9_execute_sys_speed(target
);
2461 if (retval
!= ERROR_OK
)
2466 num_accesses
+= thisrun_accesses
;
2470 while (num_accesses
< count
)
2473 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2474 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2476 for (i
= 1; i
<= thisrun_accesses
; i
++)
2480 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
2484 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2486 for (i
= 1; i
<= thisrun_accesses
; i
++)
2488 arm7_9
->store_hword_reg(target
, i
);
2490 /* fast memory writes are only safe when the target is running
2491 * from a sufficiently high clock (32 kHz is usually too slow)
2493 if (arm7_9
->fast_memory_access
)
2494 retval
= arm7_9_execute_fast_sys_speed(target
);
2496 retval
= arm7_9_execute_sys_speed(target
);
2497 if (retval
!= ERROR_OK
)
2503 num_accesses
+= thisrun_accesses
;
2507 while (num_accesses
< count
)
2510 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2511 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2513 for (i
= 1; i
<= thisrun_accesses
; i
++)
2517 reg
[i
] = *buffer
++ & 0xff;
2520 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2522 for (i
= 1; i
<= thisrun_accesses
; i
++)
2524 arm7_9
->store_byte_reg(target
, i
);
2525 /* fast memory writes are only safe when the target is running
2526 * from a sufficiently high clock (32 kHz is usually too slow)
2528 if (arm7_9
->fast_memory_access
)
2529 retval
= arm7_9_execute_fast_sys_speed(target
);
2531 retval
= arm7_9_execute_sys_speed(target
);
2532 if (retval
!= ERROR_OK
)
2539 num_accesses
+= thisrun_accesses
;
2543 LOG_ERROR("BUG: we shouldn't get here");
2549 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
2550 embeddedice_store_reg(dbg_ctrl
);
2552 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2555 for (i
= 0; i
<= last_reg
; i
++)
2556 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2558 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2559 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2561 LOG_ERROR("JTAG error while reading cpsr");
2562 return ERROR_TARGET_DATA_ABORT
;
2565 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2567 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2569 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2571 return ERROR_TARGET_DATA_ABORT
;
2577 static int dcc_count
;
2578 static uint8_t *dcc_buffer
;
2580 static int arm7_9_dcc_completion(struct target
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
2582 int retval
= ERROR_OK
;
2583 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2585 if ((retval
= target_wait_state(target
, TARGET_DEBUG_RUNNING
, 500)) != ERROR_OK
)
2588 int little
= target
->endianness
== TARGET_LITTLE_ENDIAN
;
2589 int count
= dcc_count
;
2590 uint8_t *buffer
= dcc_buffer
;
2593 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2594 * core function repeated. */
2595 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2598 struct embeddedice_reg
*ice_reg
= arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
].arch_info
;
2599 uint8_t reg_addr
= ice_reg
->addr
& 0x1f;
2600 struct jtag_tap
*tap
;
2601 tap
= ice_reg
->jtag_info
->tap
;
2603 embeddedice_write_dcc(tap
, reg_addr
, buffer
, little
, count
-2);
2604 buffer
+= (count
-2)*4;
2606 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2610 for (i
= 0; i
< count
; i
++)
2612 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2617 if ((retval
= target_halt(target
))!= ERROR_OK
)
2621 return target_wait_state(target
, TARGET_HALTED
, 500);
2624 static const uint32_t dcc_code
[] =
2626 /* r0 == input, points to memory buffer
2630 /* spin until DCC control (c0) reports data arrived */
2631 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2632 0xe3110001, /* tst r1, #1 */
2633 0x0afffffc, /* bne w */
2635 /* read word from DCC (c1), write to memory */
2636 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2637 0xe4801004, /* str r1, [r0], #4 */
2640 0xeafffff9 /* b w */
2643 int armv4_5_run_algorithm_inner(struct target
*target
, int num_mem_params
, struct mem_param
*mem_params
, int num_reg_params
, struct reg_param
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
, int (*run_it
)(struct target
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
));
2645 int arm7_9_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
2648 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2651 if (!arm7_9
->dcc_downloads
)
2652 return target_write_memory(target
, address
, 4, count
, buffer
);
2654 /* regrab previously allocated working_area, or allocate a new one */
2655 if (!arm7_9
->dcc_working_area
)
2657 uint8_t dcc_code_buf
[6 * 4];
2659 /* make sure we have a working area */
2660 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2662 LOG_INFO("no working area available, falling back to memory writes");
2663 return target_write_memory(target
, address
, 4, count
, buffer
);
2666 /* copy target instructions to target endianness */
2667 for (i
= 0; i
< 6; i
++)
2669 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2672 /* write DCC code to working area */
2673 if ((retval
= target_write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
)) != ERROR_OK
)
2679 struct armv4_5_algorithm armv4_5_info
;
2680 struct reg_param reg_params
[1];
2682 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2683 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2684 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2686 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2688 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2691 dcc_buffer
= buffer
;
2692 retval
= armv4_5_run_algorithm_inner(target
, 0, NULL
, 1, reg_params
,
2693 arm7_9
->dcc_working_area
->address
, arm7_9
->dcc_working_area
->address
+ 6*4, 20*1000, &armv4_5_info
, arm7_9_dcc_completion
);
2695 if (retval
== ERROR_OK
)
2697 uint32_t endaddress
= buf_get_u32(reg_params
[0].value
, 0, 32);
2698 if (endaddress
!= (address
+ count
*4))
2700 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32
" got 0x%0" PRIx32
"", (address
+ count
*4), endaddress
);
2701 retval
= ERROR_FAIL
;
2705 destroy_reg_param(®_params
[0]);
2711 * Perform per-target setup that requires JTAG access.
2713 int arm7_9_examine(struct target
*target
)
2715 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2718 if (!target_was_examined(target
)) {
2719 struct reg_cache
*t
, **cache_p
;
2721 t
= embeddedice_build_reg_cache(target
, arm7_9
);
2725 cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2727 arm7_9
->eice_cache
= (*cache_p
);
2729 if (arm7_9
->armv4_5_common
.etm
)
2730 (*cache_p
)->next
= etm_build_reg_cache(target
,
2732 arm7_9
->armv4_5_common
.etm
);
2734 target_set_examined(target
);
2737 retval
= embeddedice_setup(target
);
2738 if (retval
== ERROR_OK
)
2739 retval
= arm7_9_setup(target
);
2740 if (retval
== ERROR_OK
&& arm7_9
->armv4_5_common
.etm
)
2741 retval
= etm_setup(target
);
2746 COMMAND_HANDLER(handle_arm7_9_write_xpsr_command
)
2751 struct target
*target
= get_current_target(cmd_ctx
);
2752 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2754 if (!is_arm7_9(arm7_9
))
2756 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2757 return ERROR_TARGET_INVALID
;
2760 if (target
->state
!= TARGET_HALTED
)
2762 command_print(cmd_ctx
, "can't write registers while running");
2768 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr | spsr>");
2772 COMMAND_PARSE_NUMBER(u32
, args
[0], value
);
2773 COMMAND_PARSE_NUMBER(int, args
[1], spsr
);
2775 /* if we're writing the CPSR, mask the T bit */
2779 arm7_9
->write_xpsr(target
, value
, spsr
);
2780 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2782 LOG_ERROR("JTAG error while writing to xpsr");
2789 COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command
)
2795 struct target
*target
= get_current_target(cmd_ctx
);
2796 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2798 if (!is_arm7_9(arm7_9
))
2800 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2801 return ERROR_TARGET_INVALID
;
2804 if (target
->state
!= TARGET_HALTED
)
2806 command_print(cmd_ctx
, "can't write registers while running");
2812 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
2816 COMMAND_PARSE_NUMBER(u32
, args
[0], value
);
2817 COMMAND_PARSE_NUMBER(int, args
[1], rotate
);
2818 COMMAND_PARSE_NUMBER(int, args
[2], spsr
);
2820 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2821 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2823 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2830 COMMAND_HANDLER(handle_arm7_9_write_core_reg_command
)
2835 struct target
*target
= get_current_target(cmd_ctx
);
2836 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2838 if (!is_arm7_9(arm7_9
))
2840 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2841 return ERROR_TARGET_INVALID
;
2844 if (target
->state
!= TARGET_HALTED
)
2846 command_print(cmd_ctx
, "can't write registers while running");
2852 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
2856 COMMAND_PARSE_NUMBER(int, args
[0], num
);
2857 COMMAND_PARSE_NUMBER(u32
, args
[1], mode
);
2858 COMMAND_PARSE_NUMBER(u32
, args
[2], value
);
2860 return arm7_9_write_core_reg(target
, num
, mode
, value
);
2863 COMMAND_HANDLER(handle_arm7_9_dbgrq_command
)
2865 struct target
*target
= get_current_target(cmd_ctx
);
2866 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2868 if (!is_arm7_9(arm7_9
))
2870 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2871 return ERROR_TARGET_INVALID
;
2876 if (strcmp("enable", args
[0]) == 0)
2878 arm7_9
->use_dbgrq
= 1;
2880 else if (strcmp("disable", args
[0]) == 0)
2882 arm7_9
->use_dbgrq
= 0;
2886 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable | disable>");
2890 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2895 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command
)
2897 struct target
*target
= get_current_target(cmd_ctx
);
2898 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2900 if (!is_arm7_9(arm7_9
))
2902 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2903 return ERROR_TARGET_INVALID
;
2908 if (strcmp("enable", args
[0]) == 0)
2910 arm7_9
->fast_memory_access
= 1;
2912 else if (strcmp("disable", args
[0]) == 0)
2914 arm7_9
->fast_memory_access
= 0;
2918 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable | disable>");
2922 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2927 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command
)
2929 struct target
*target
= get_current_target(cmd_ctx
);
2930 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2932 if (!is_arm7_9(arm7_9
))
2934 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2935 return ERROR_TARGET_INVALID
;
2940 if (strcmp("enable", args
[0]) == 0)
2942 arm7_9
->dcc_downloads
= 1;
2944 else if (strcmp("disable", args
[0]) == 0)
2946 arm7_9
->dcc_downloads
= 0;
2950 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable | disable>");
2954 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2959 int arm7_9_init_arch_info(struct target
*target
, struct arm7_9_common
*arm7_9
)
2961 int retval
= ERROR_OK
;
2962 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
2964 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2966 if ((retval
= arm_jtag_setup_connection(&arm7_9
->jtag_info
)) != ERROR_OK
)
2969 /* caller must have allocated via calloc(), so everything's zeroed */
2971 arm7_9
->wp_available_max
= 2;
2973 arm7_9
->fast_memory_access
= fast_and_dangerous
;
2974 arm7_9
->dcc_downloads
= fast_and_dangerous
;
2976 armv4_5
->arch_info
= arm7_9
;
2977 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2978 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2979 armv4_5
->full_context
= arm7_9_full_context
;
2981 if ((retval
= armv4_5_init_arch_info(target
, armv4_5
)) != ERROR_OK
)
2984 return target_register_timer_callback(arm7_9_handle_target_request
,
2988 int arm7_9_register_commands(struct command_context
*cmd_ctx
)
2990 struct command
*arm7_9_cmd
;
2992 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9",
2993 NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2995 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr",
2996 handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
,
2997 "write program status register <value> <not cpsr | spsr>");
2998 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8",
2999 handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
,
3000 "write program status register "
3001 "<8bit immediate> <rotate> <not cpsr | spsr>");
3003 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg",
3004 handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
,
3005 "write core register <num> <mode> <value>");
3007 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq",
3008 handle_arm7_9_dbgrq_command
, COMMAND_ANY
,
3009 "use EmbeddedICE dbgrq instead of breakpoint "
3010 "for target halt requests <enable | disable>");
3011 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access",
3012 handle_arm7_9_fast_memory_access_command
, COMMAND_ANY
,
3013 "use fast memory accesses instead of slower "
3014 "but potentially safer accesses <enable | disable>");
3015 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads",
3016 handle_arm7_9_dcc_downloads_command
, COMMAND_ANY
,
3017 "use DCC downloads for larger memory writes <enable | disable>");
3019 armv4_5_register_commands(cmd_ctx
);
3021 etm_register_commands(cmd_ctx
);
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