1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
28 #include "target_request.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
40 #include <sys/types.h>
45 int arm7_9_debug_entry(target_t
*target
);
46 int arm7_9_enable_sw_bkpts(struct target_s
*target
);
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
55 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
60 int arm7_9_reinit_embeddedice(target_t
*target
)
62 armv4_5_common_t
*armv4_5
= target
->arch_info
;
63 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
65 breakpoint_t
*breakpoint
= target
->breakpoints
;
67 arm7_9
->wp_available
= 2;
71 /* mark all hardware breakpoints as unset */
74 if (breakpoint
->type
== BKPT_HARD
)
78 breakpoint
= breakpoint
->next
;
81 if (arm7_9
->sw_bkpts_enabled
&& arm7_9
->sw_bkpts_use_wp
)
83 arm7_9
->sw_bkpts_enabled
= 0;
84 arm7_9_enable_sw_bkpts(target
);
87 arm7_9
->reinit_embeddedice
= 0;
92 int arm7_9_jtag_callback(enum jtag_event event
, void *priv
)
94 target_t
*target
= priv
;
95 armv4_5_common_t
*armv4_5
= target
->arch_info
;
96 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
102 if (event
== JTAG_TRST_ASSERTED
)
104 arm7_9
->reinit_embeddedice
= 1;
110 int arm7_9_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
)
112 armv4_5_common_t
*armv4_5
= target
->arch_info
;
113 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
115 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
120 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
125 *armv4_5_p
= armv4_5
;
131 int arm7_9_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
133 armv4_5_common_t
*armv4_5
= target
->arch_info
;
134 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
136 if (target
->state
!= TARGET_HALTED
)
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED
;
142 if (arm7_9
->force_hw_bkpts
)
143 breakpoint
->type
= BKPT_HARD
;
147 WARNING("breakpoint already set");
151 if (breakpoint
->type
== BKPT_HARD
)
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
155 if (!arm7_9
->wp0_used
)
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
161 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
163 jtag_execute_queue();
164 arm7_9
->wp0_used
= 1;
167 else if (!arm7_9
->wp1_used
)
169 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
170 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
171 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
172 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
173 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
175 jtag_execute_queue();
176 arm7_9
->wp1_used
= 1;
181 ERROR("BUG: no hardware comparator available");
185 else if (breakpoint
->type
== BKPT_SOFT
)
187 if (breakpoint
->length
== 4)
189 u32 verify
= 0xffffffff;
190 /* keep the original instruction in target endianness */
191 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
192 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
193 target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
);
195 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, (u8
*)&verify
);
196 if (verify
!= arm7_9
->arm_bkpt
)
198 ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint
->address
);
205 /* keep the original instruction in target endianness */
206 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
207 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
208 target_write_u16(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
);
210 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, (u8
*)&verify
);
211 if (verify
!= arm7_9
->thumb_bkpt
)
213 ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint
->address
);
224 int arm7_9_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
226 armv4_5_common_t
*armv4_5
= target
->arch_info
;
227 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
229 if (target
->state
!= TARGET_HALTED
)
231 WARNING("target not halted");
232 return ERROR_TARGET_NOT_HALTED
;
235 if (!breakpoint
->set
)
237 WARNING("breakpoint not set");
241 if (breakpoint
->type
== BKPT_HARD
)
243 if (breakpoint
->set
== 1)
245 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
246 jtag_execute_queue();
247 arm7_9
->wp0_used
= 0;
249 else if (breakpoint
->set
== 2)
251 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
252 jtag_execute_queue();
253 arm7_9
->wp1_used
= 0;
259 /* restore original instruction (kept in target endianness) */
260 if (breakpoint
->length
== 4)
263 /* check that user program as not modified breakpoint instruction */
264 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, (u8
*)¤t_instr
);
265 if (current_instr
==arm7_9
->arm_bkpt
)
266 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
271 /* check that user program as not modified breakpoint instruction */
272 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, (u8
*)¤t_instr
);
273 if (current_instr
==arm7_9
->thumb_bkpt
)
274 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
282 int arm7_9_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
284 armv4_5_common_t
*armv4_5
= target
->arch_info
;
285 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
287 if (target
->state
!= TARGET_HALTED
)
289 WARNING("target not halted");
290 return ERROR_TARGET_NOT_HALTED
;
293 if (arm7_9
->force_hw_bkpts
)
295 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
296 breakpoint
->type
= BKPT_HARD
;
299 if ((breakpoint
->type
== BKPT_SOFT
) && (arm7_9
->sw_bkpts_enabled
== 0))
301 INFO("sw breakpoint requested, but software breakpoints not enabled");
302 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
305 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
307 INFO("no watchpoint unit available for hardware breakpoint");
308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
311 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
313 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
317 if (breakpoint
->type
== BKPT_HARD
)
318 arm7_9
->wp_available
--;
323 int arm7_9_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
325 armv4_5_common_t
*armv4_5
= target
->arch_info
;
326 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
328 if (target
->state
!= TARGET_HALTED
)
330 WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED
;
336 arm7_9_unset_breakpoint(target
, breakpoint
);
339 if (breakpoint
->type
== BKPT_HARD
)
340 arm7_9
->wp_available
++;
345 int arm7_9_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
347 armv4_5_common_t
*armv4_5
= target
->arch_info
;
348 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
352 mask
= watchpoint
->length
- 1;
354 if (target
->state
!= TARGET_HALTED
)
356 WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED
;
360 if (watchpoint
->rw
== WPT_ACCESS
)
365 if (!arm7_9
->wp0_used
)
367 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
368 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
369 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
370 if( watchpoint
->mask
!= 0xffffffffu
)
371 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
372 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
373 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
375 jtag_execute_queue();
377 arm7_9
->wp0_used
= 2;
379 else if (!arm7_9
->wp1_used
)
381 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
382 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
383 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
384 if( watchpoint
->mask
!= 0xffffffffu
)
385 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
386 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
387 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
389 jtag_execute_queue();
391 arm7_9
->wp1_used
= 2;
395 ERROR("BUG: no hardware comparator available");
402 int arm7_9_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
404 armv4_5_common_t
*armv4_5
= target
->arch_info
;
405 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
407 if (target
->state
!= TARGET_HALTED
)
409 WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED
;
413 if (!watchpoint
->set
)
415 WARNING("breakpoint not set");
419 if (watchpoint
->set
== 1)
421 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
422 jtag_execute_queue();
423 arm7_9
->wp0_used
= 0;
425 else if (watchpoint
->set
== 2)
427 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
428 jtag_execute_queue();
429 arm7_9
->wp1_used
= 0;
436 int arm7_9_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
438 armv4_5_common_t
*armv4_5
= target
->arch_info
;
439 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
441 if (target
->state
!= TARGET_HALTED
)
443 WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED
;
447 if (arm7_9
->wp_available
< 1)
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
452 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
457 arm7_9
->wp_available
--;
462 int arm7_9_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
464 armv4_5_common_t
*armv4_5
= target
->arch_info
;
465 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
467 if (target
->state
!= TARGET_HALTED
)
469 WARNING("target not halted");
470 return ERROR_TARGET_NOT_HALTED
;
475 arm7_9_unset_watchpoint(target
, watchpoint
);
478 arm7_9
->wp_available
++;
483 int arm7_9_enable_sw_bkpts(struct target_s
*target
)
485 armv4_5_common_t
*armv4_5
= target
->arch_info
;
486 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
489 if (arm7_9
->sw_bkpts_enabled
)
492 if (arm7_9
->wp_available
< 1)
494 WARNING("can't enable sw breakpoints with no watchpoint unit available");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
497 arm7_9
->wp_available
--;
499 if (!arm7_9
->wp0_used
)
501 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
502 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
503 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
504 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
505 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
506 arm7_9
->sw_bkpts_enabled
= 1;
507 arm7_9
->wp0_used
= 3;
509 else if (!arm7_9
->wp1_used
)
511 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
512 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
513 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
514 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
515 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
516 arm7_9
->sw_bkpts_enabled
= 2;
517 arm7_9
->wp1_used
= 3;
521 ERROR("BUG: both watchpoints used, but wp_available >= 1");
525 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
527 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
534 int arm7_9_disable_sw_bkpts(struct target_s
*target
)
536 armv4_5_common_t
*armv4_5
= target
->arch_info
;
537 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
539 if (!arm7_9
->sw_bkpts_enabled
)
542 if (arm7_9
->sw_bkpts_enabled
== 1)
544 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
545 arm7_9
->sw_bkpts_enabled
= 0;
546 arm7_9
->wp0_used
= 0;
547 arm7_9
->wp_available
++;
549 else if (arm7_9
->sw_bkpts_enabled
== 2)
551 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
552 arm7_9
->sw_bkpts_enabled
= 0;
553 arm7_9
->wp1_used
= 0;
554 arm7_9
->wp_available
++;
560 int arm7_9_execute_sys_speed(struct target_s
*target
)
565 armv4_5_common_t
*armv4_5
= target
->arch_info
;
566 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
567 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
568 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
570 /* set RESTART instruction */
571 jtag_add_end_state(TAP_RTI
);
572 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
574 for (timeout
=0; timeout
<50; timeout
++)
576 /* read debug status register */
577 embeddedice_read_reg(dbg_stat
);
578 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
580 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
581 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
587 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
588 return ERROR_TARGET_TIMEOUT
;
594 int arm7_9_execute_fast_sys_speed(struct target_s
*target
)
597 static u8 check_value
[4], check_mask
[4];
599 armv4_5_common_t
*armv4_5
= target
->arch_info
;
600 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
601 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
602 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
604 /* set RESTART instruction */
605 jtag_add_end_state(TAP_RTI
);
606 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
610 /* check for DBGACK and SYSCOMP set (others don't care) */
612 /* NB! These are constants that must be available until after next jtag_execute() and
613 we evaluate the values upon first execution in lieu of setting up these constants
616 buf_set_u32(check_value
, 0, 32, 0x9);
617 buf_set_u32(check_mask
, 0, 32, 0x9);
621 /* read debug status register */
622 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_value
);
627 int arm7_9_target_request_data(target_t
*target
, u32 size
, u8
*buffer
)
629 armv4_5_common_t
*armv4_5
= target
->arch_info
;
630 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
631 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
635 data
= malloc(size
* (sizeof(u32
)));
637 embeddedice_receive(jtag_info
, data
, size
);
639 for (i
= 0; i
< size
; i
++)
641 h_u32_to_le(buffer
+ (i
* 4), data
[i
]);
649 int arm7_9_handle_target_request(void *priv
)
651 target_t
*target
= priv
;
652 armv4_5_common_t
*armv4_5
= target
->arch_info
;
653 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
654 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
655 reg_t
*dcc_control
= &arm7_9
->eice_cache
->reg_list
[EICE_COMMS_CTRL
];
657 if (!target
->dbg_msg_enabled
)
660 if (target
->state
== TARGET_RUNNING
)
662 /* read DCC control register */
663 embeddedice_read_reg(dcc_control
);
664 jtag_execute_queue();
667 if (buf_get_u32(dcc_control
->value
, 1, 1) == 1)
671 embeddedice_receive(jtag_info
, &request
, 1);
672 target_request(target
, request
);
679 int arm7_9_poll(target_t
*target
)
682 armv4_5_common_t
*armv4_5
= target
->arch_info
;
683 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
684 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
686 if (arm7_9
->reinit_embeddedice
)
688 arm7_9_reinit_embeddedice(target
);
691 /* read debug status register */
692 embeddedice_read_reg(dbg_stat
);
693 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
698 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
700 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat
->value
, 0, 32));
701 if (target
->state
== TARGET_UNKNOWN
)
703 WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
705 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
707 target
->state
= TARGET_HALTED
;
708 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
711 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
713 if (target
->state
== TARGET_DEBUG_RUNNING
)
715 target
->state
= TARGET_HALTED
;
716 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
719 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
721 if (target
->state
!= TARGET_HALTED
)
723 WARNING("DBGACK set, but the target did not end up in the halted stated %d", target
->state
);
728 if (target
->state
!= TARGET_DEBUG_RUNNING
)
729 target
->state
= TARGET_RUNNING
;
735 int arm7_9_assert_reset(target_t
*target
)
739 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
741 if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_UNKNOWN
)
743 /* if the target wasn't running, there might be working areas allocated */
744 target_free_all_working_areas(target
);
746 /* assert SRST and TRST */
747 /* system would get ouf sync if we didn't reset test-logic, too */
748 if ((retval
= jtag_add_reset(1, 1)) != ERROR_OK
)
750 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
752 WARNING("can't assert srst");
757 ERROR("unknown error");
761 jtag_add_sleep(5000);
762 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
764 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
766 WARNING("srst resets test logic, too");
767 retval
= jtag_add_reset(1, 1);
773 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
775 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
777 WARNING("srst resets test logic, too");
778 retval
= jtag_add_reset(1, 1);
781 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
783 WARNING("can't assert srst");
786 else if (retval
!= ERROR_OK
)
788 ERROR("unknown error");
794 target
->state
= TARGET_RESET
;
795 jtag_add_sleep(50000);
797 armv4_5_invalidate_core_regs(target
);
803 int arm7_9_deassert_reset(target_t
*target
)
805 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
807 /* deassert reset lines */
808 jtag_add_reset(0, 0);
813 int arm7_9_clear_halt(target_t
*target
)
815 armv4_5_common_t
*armv4_5
= target
->arch_info
;
816 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
817 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
819 /* we used DBGRQ only if we didn't come out of reset */
820 if (!arm7_9
->debug_entry_from_reset
&& arm7_9
->use_dbgrq
)
822 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
824 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
825 embeddedice_store_reg(dbg_ctrl
);
829 if (arm7_9
->debug_entry_from_reset
&& arm7_9
->has_vector_catch
)
831 /* if we came out of reset, and vector catch is supported, we used
832 * vector catch to enter debug state
833 * restore the register in that case
835 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
]);
839 /* restore registers if watchpoint unit 0 was in use
841 if (arm7_9
->wp0_used
)
843 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
844 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
845 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
847 /* control value always has to be restored, as it was either disabled,
848 * or enabled with possibly different bits
850 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
857 int arm7_9_soft_reset_halt(struct target_s
*target
)
859 armv4_5_common_t
*armv4_5
= target
->arch_info
;
860 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
861 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
862 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
865 if (target
->state
== TARGET_RUNNING
)
867 target
->type
->halt(target
);
870 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
872 embeddedice_read_reg(dbg_stat
);
873 jtag_execute_queue();
875 target
->state
= TARGET_HALTED
;
877 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
878 * ensure that DBGRQ is cleared
880 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
881 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
882 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
883 embeddedice_store_reg(dbg_ctrl
);
885 arm7_9_clear_halt(target
);
887 /* if the target is in Thumb state, change to ARM state */
888 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
890 u32 r0_thumb
, pc_thumb
;
891 DEBUG("target entered debug from Thumb state, changing to ARM");
892 /* Entered debug from Thumb mode */
893 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
894 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
897 /* all register content is now invalid */
898 armv4_5_invalidate_core_regs(target
);
900 /* SVC, ARM state, IRQ and FIQ disabled */
901 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
902 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
903 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
905 /* start fetching from 0x0 */
906 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
907 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
908 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
910 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
911 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
913 /* reset registers */
914 for (i
= 0; i
<= 14; i
++)
916 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
917 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
918 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
921 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
926 int arm7_9_prepare_reset_halt(target_t
*target
)
928 armv4_5_common_t
*armv4_5
= target
->arch_info
;
929 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
931 /* poll the target, and resume if it was currently halted */
933 if (target
->state
== TARGET_HALTED
)
935 arm7_9_resume(target
, 1, 0x0, 0, 1);
938 if (arm7_9
->has_vector_catch
)
940 /* program vector catch register to catch reset vector */
941 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
], 0x1);
945 /* program watchpoint unit to match on reset vector address */
946 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0x3);
947 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
948 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
949 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
955 int arm7_9_halt(target_t
*target
)
957 armv4_5_common_t
*armv4_5
= target
->arch_info
;
958 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
959 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
961 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
963 if (target
->state
== TARGET_HALTED
)
965 WARNING("target was already halted");
966 return ERROR_TARGET_ALREADY_HALTED
;
969 if (target
->state
== TARGET_UNKNOWN
)
971 WARNING("target was in unknown state when halt was requested");
974 if (target
->state
== TARGET_RESET
)
976 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
978 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
979 return ERROR_TARGET_FAILURE
;
983 /* we came here in a reset_halt or reset_init sequence
984 * debug entry was already prepared in arm7_9_prepare_reset_halt()
986 target
->debug_reason
= DBG_REASON_DBGRQ
;
992 if (arm7_9
->use_dbgrq
)
994 /* program EmbeddedICE Debug Control Register to assert DBGRQ
996 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
997 embeddedice_store_reg(dbg_ctrl
);
1001 /* program watchpoint unit to match on any address
1003 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1004 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1005 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1006 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
1009 target
->debug_reason
= DBG_REASON_DBGRQ
;
1014 int arm7_9_debug_entry(target_t
*target
)
1019 u32 r0_thumb
, pc_thumb
;
1022 /* get pointers to arch-specific information */
1023 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1024 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1025 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1026 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1028 #ifdef _DEBUG_ARM7_9_
1032 if (arm7_9
->pre_debug_entry
)
1033 arm7_9
->pre_debug_entry(target
);
1035 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1036 * ensure that DBGRQ is cleared
1038 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1039 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1040 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1041 embeddedice_store_reg(dbg_ctrl
);
1043 arm7_9_clear_halt(target
);
1045 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1049 case ERROR_JTAG_QUEUE_FAILED
:
1050 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1058 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
1062 if (target
->state
!= TARGET_HALTED
)
1064 WARNING("target not halted");
1065 return ERROR_TARGET_NOT_HALTED
;
1068 /* if the target is in Thumb state, change to ARM state */
1069 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1071 DEBUG("target entered debug from Thumb state");
1072 /* Entered debug from Thumb mode */
1073 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1074 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1075 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb
, pc_thumb
);
1079 DEBUG("target entered debug from ARM state");
1080 /* Entered debug from ARM mode */
1081 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1084 for (i
= 0; i
< 16; i
++)
1085 context_p
[i
] = &context
[i
];
1086 /* save core registers (r0 - r15 of current core mode) */
1087 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
1089 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1091 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1094 /* if the core has been executing in Thumb state, set the T bit */
1095 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1098 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
1099 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1100 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1102 armv4_5
->core_mode
= cpsr
& 0x1f;
1104 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1106 target
->state
= TARGET_UNKNOWN
;
1107 ERROR("cpsr contains invalid mode value - communication failure");
1108 return ERROR_TARGET_FAILURE
;
1111 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1113 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1115 DEBUG("thumb state, applying fixups");
1116 context
[0] = r0_thumb
;
1117 context
[15] = pc_thumb
;
1118 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1120 /* adjust value stored by STM */
1121 context
[15] -= 3 * 4;
1124 if ((target
->debug_reason
== DBG_REASON_BREAKPOINT
)
1125 || (target
->debug_reason
== DBG_REASON_SINGLESTEP
)
1126 || (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
1127 || (target
->debug_reason
== DBG_REASON_WPTANDBKPT
)
1128 || ((target
->debug_reason
== DBG_REASON_DBGRQ
) && (arm7_9
->use_dbgrq
== 0)))
1129 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1130 else if (target
->debug_reason
== DBG_REASON_DBGRQ
)
1131 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1134 ERROR("unknown debug reason: %i", target
->debug_reason
);
1138 for (i
=0; i
<=15; i
++)
1140 DEBUG("r%i: 0x%8.8x", i
, context
[i
]);
1141 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1142 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1143 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1146 DEBUG("entered debug state at PC 0x%x", context
[15]);
1148 /* exceptions other than USR & SYS have a saved program status register */
1149 if ((armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_USR
) && (armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_SYS
))
1152 arm7_9
->read_xpsr(target
, &spsr
, 1);
1153 jtag_execute_queue();
1154 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1155 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1156 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1159 /* r0 and r15 (pc) have to be restored later */
1160 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1161 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).valid
;
1163 if ((retval
= jtag
->execute_queue()) != ERROR_OK
)
1166 if (arm7_9
->post_debug_entry
)
1167 arm7_9
->post_debug_entry(target
);
1172 int arm7_9_full_context(target_t
*target
)
1176 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1177 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1181 if (target
->state
!= TARGET_HALTED
)
1183 WARNING("target not halted");
1184 return ERROR_TARGET_NOT_HALTED
;
1187 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1188 * SYS shares registers with User, so we don't touch SYS
1190 for(i
= 0; i
< 6; i
++)
1197 /* check if there are invalid registers in the current mode
1199 for (j
= 0; j
<= 16; j
++)
1201 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1209 /* change processor mode (and mask T bit) */
1210 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1211 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1213 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1215 for (j
= 0; j
< 15; j
++)
1217 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1219 reg_p
[j
] = (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1221 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1222 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1226 /* if only the PSR is invalid, mask is all zeroes */
1228 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1230 /* check if the PSR has to be read */
1231 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1233 arm7_9
->read_xpsr(target
, (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1234 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1235 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1240 /* restore processor mode (mask T bit) */
1241 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1243 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1245 ERROR("JTAG failure");
1251 int arm7_9_restore_context(target_t
*target
)
1253 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1254 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1256 armv4_5_core_reg_t
*reg_arch_info
;
1257 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1264 if (target
->state
!= TARGET_HALTED
)
1266 WARNING("target not halted");
1267 return ERROR_TARGET_NOT_HALTED
;
1270 if (arm7_9
->pre_restore_context
)
1271 arm7_9
->pre_restore_context(target
);
1273 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1274 * SYS shares registers with User, so we don't touch SYS
1276 for (i
= 0; i
< 6; i
++)
1278 DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1281 /* check if there are dirty registers in the current mode
1283 for (j
= 0; j
<= 16; j
++)
1285 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1286 reg_arch_info
= reg
->arch_info
;
1287 if (reg
->dirty
== 1)
1289 if (reg
->valid
== 1)
1292 DEBUG("examining dirty reg: %s", reg
->name
);
1293 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1294 && (reg_arch_info
->mode
!= current_mode
)
1295 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1296 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1299 DEBUG("require mode change");
1304 ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1319 /* change processor mode (mask T bit) */
1320 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1321 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1323 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1324 current_mode
= armv4_5_number_to_mode(i
);
1327 for (j
= 0; j
<= 14; j
++)
1329 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1330 reg_arch_info
= reg
->arch_info
;
1333 if (reg
->dirty
== 1)
1335 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1340 DEBUG("writing register %i of mode %s with value 0x%8.8x", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1346 arm7_9
->write_core_regs(target
, mask
, regs
);
1349 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1350 reg_arch_info
= reg
->arch_info
;
1351 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1353 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i
, buf_get_u32(reg
->value
, 0, 32));
1354 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1359 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1361 /* restore processor mode (mask T bit) */
1364 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1365 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1367 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr
);
1368 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1370 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1372 /* CPSR has been changed, full restore necessary (mask T bit) */
1373 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1374 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1375 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1376 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1380 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1381 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1382 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1384 if (arm7_9
->post_restore_context
)
1385 arm7_9
->post_restore_context(target
);
1390 int arm7_9_restart_core(struct target_s
*target
)
1392 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1393 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1394 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
1396 /* set RESTART instruction */
1397 jtag_add_end_state(TAP_RTI
);
1398 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
1400 jtag_add_runtest(1, TAP_RTI
);
1401 if ((jtag_execute_queue()) != ERROR_OK
)
1409 void arm7_9_enable_watchpoints(struct target_s
*target
)
1411 watchpoint_t
*watchpoint
= target
->watchpoints
;
1415 if (watchpoint
->set
== 0)
1416 arm7_9_set_watchpoint(target
, watchpoint
);
1417 watchpoint
= watchpoint
->next
;
1421 void arm7_9_enable_breakpoints(struct target_s
*target
)
1423 breakpoint_t
*breakpoint
= target
->breakpoints
;
1425 /* set any pending breakpoints */
1428 if (breakpoint
->set
== 0)
1429 arm7_9_set_breakpoint(target
, breakpoint
);
1430 breakpoint
= breakpoint
->next
;
1434 void arm7_9_disable_bkpts_and_wpts(struct target_s
*target
)
1436 breakpoint_t
*breakpoint
= target
->breakpoints
;
1437 watchpoint_t
*watchpoint
= target
->watchpoints
;
1439 /* set any pending breakpoints */
1442 if (breakpoint
->set
!= 0)
1443 arm7_9_unset_breakpoint(target
, breakpoint
);
1444 breakpoint
= breakpoint
->next
;
1449 if (watchpoint
->set
!= 0)
1450 arm7_9_unset_watchpoint(target
, watchpoint
);
1451 watchpoint
= watchpoint
->next
;
1455 int arm7_9_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1457 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1458 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1459 breakpoint_t
*breakpoint
= target
->breakpoints
;
1460 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1465 if (target
->state
!= TARGET_HALTED
)
1467 WARNING("target not halted");
1468 return ERROR_TARGET_NOT_HALTED
;
1471 if (!debug_execution
)
1473 target_free_all_working_areas(target
);
1476 /* current = 1: continue on current pc, otherwise continue at <address> */
1478 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1480 /* the front-end may request us not to handle breakpoints */
1481 if (handle_breakpoints
)
1483 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1485 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1486 arm7_9_unset_breakpoint(target
, breakpoint
);
1488 DEBUG("enable single-step");
1489 arm7_9
->enable_single_step(target
);
1491 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1493 arm7_9_restore_context(target
);
1495 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1496 arm7_9
->branch_resume(target
);
1497 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1499 arm7_9
->branch_resume_thumb(target
);
1503 ERROR("unhandled core state");
1507 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1508 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1509 err
= arm7_9_execute_sys_speed(target
);
1511 DEBUG("disable single-step");
1512 arm7_9
->disable_single_step(target
);
1514 if (err
!= ERROR_OK
)
1516 arm7_9_set_breakpoint(target
, breakpoint
);
1517 target
->state
= TARGET_UNKNOWN
;
1521 arm7_9_debug_entry(target
);
1522 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1524 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1525 arm7_9_set_breakpoint(target
, breakpoint
);
1529 /* enable any pending breakpoints and watchpoints */
1530 arm7_9_enable_breakpoints(target
);
1531 arm7_9_enable_watchpoints(target
);
1533 arm7_9_restore_context(target
);
1535 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1537 arm7_9
->branch_resume(target
);
1539 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1541 arm7_9
->branch_resume_thumb(target
);
1545 ERROR("unhandled core state");
1549 /* deassert DBGACK and INTDIS */
1550 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1551 /* INTDIS only when we really resume, not during debug execution */
1552 if (!debug_execution
)
1553 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1554 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1556 arm7_9_restart_core(target
);
1558 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1560 if (!debug_execution
)
1562 /* registers are now invalid */
1563 armv4_5_invalidate_core_regs(target
);
1564 target
->state
= TARGET_RUNNING
;
1565 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1569 target
->state
= TARGET_DEBUG_RUNNING
;
1570 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1573 DEBUG("target resumed");
1578 void arm7_9_enable_eice_step(target_t
*target
)
1580 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1581 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1583 /* setup an inverse breakpoint on the current PC
1584 * - comparator 1 matches the current address
1585 * - rangeout from comparator 1 is connected to comparator 0 rangein
1586 * - comparator 0 matches any address, as long as rangein is low */
1587 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1588 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1589 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1590 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0x77);
1591 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1592 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1593 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1594 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1595 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xf7);
1598 void arm7_9_disable_eice_step(target_t
*target
)
1600 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1601 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1603 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1604 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1605 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1606 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1607 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1608 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1609 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1610 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1611 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1614 int arm7_9_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1616 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1617 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1618 breakpoint_t
*breakpoint
= NULL
;
1621 if (target
->state
!= TARGET_HALTED
)
1623 WARNING("target not halted");
1624 return ERROR_TARGET_NOT_HALTED
;
1627 /* current = 1: continue on current pc, otherwise continue at <address> */
1629 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1631 /* the front-end may request us not to handle breakpoints */
1632 if (handle_breakpoints
)
1633 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1634 arm7_9_unset_breakpoint(target
, breakpoint
);
1636 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1638 arm7_9_restore_context(target
);
1640 arm7_9
->enable_single_step(target
);
1642 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1644 arm7_9
->branch_resume(target
);
1646 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1648 arm7_9
->branch_resume_thumb(target
);
1652 ERROR("unhandled core state");
1656 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1658 err
= arm7_9_execute_sys_speed(target
);
1659 arm7_9
->disable_single_step(target
);
1661 /* registers are now invalid */
1662 armv4_5_invalidate_core_regs(target
);
1664 if (err
!= ERROR_OK
)
1666 target
->state
= TARGET_UNKNOWN
;
1668 arm7_9_debug_entry(target
);
1669 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1670 DEBUG("target stepped");
1674 arm7_9_set_breakpoint(target
, breakpoint
);
1680 int arm7_9_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1685 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1686 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1687 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1689 if ((num
< 0) || (num
> 16))
1690 return ERROR_INVALID_ARGUMENTS
;
1692 if ((mode
!= ARMV4_5_MODE_ANY
)
1693 && (mode
!= armv4_5
->core_mode
)
1694 && (reg_mode
!= ARMV4_5_MODE_ANY
))
1698 /* change processor mode (mask T bit) */
1699 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1702 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1705 if ((num
>= 0) && (num
<= 15))
1707 /* read a normal core register */
1708 reg_p
[num
] = &value
;
1710 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
1714 /* read a program status register
1715 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1717 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1718 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1720 arm7_9
->read_xpsr(target
, &value
, spsr
);
1723 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1725 ERROR("JTAG failure");
1729 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1730 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1731 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
1733 if ((mode
!= ARMV4_5_MODE_ANY
)
1734 && (mode
!= armv4_5
->core_mode
)
1735 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1736 /* restore processor mode (mask T bit) */
1737 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1744 int arm7_9_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1748 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1749 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1750 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1752 if ((num
< 0) || (num
> 16))
1753 return ERROR_INVALID_ARGUMENTS
;
1755 if ((mode
!= ARMV4_5_MODE_ANY
)
1756 && (mode
!= armv4_5
->core_mode
)
1757 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1760 /* change processor mode (mask T bit) */
1761 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1764 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1767 if ((num
>= 0) && (num
<= 15))
1769 /* write a normal core register */
1772 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
1776 /* write a program status register
1777 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1779 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1780 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1782 /* if we're writing the CPSR, mask the T bit */
1786 arm7_9
->write_xpsr(target
, value
, spsr
);
1789 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1790 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1792 if ((mode
!= ARMV4_5_MODE_ANY
)
1793 && (mode
!= armv4_5
->core_mode
)
1794 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1795 /* restore processor mode (mask T bit) */
1796 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1799 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1801 ERROR("JTAG failure");
1809 int arm7_9_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1811 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1812 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1815 int num_accesses
= 0;
1816 int thisrun_accesses
;
1822 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1824 if (target
->state
!= TARGET_HALTED
)
1826 WARNING("target not halted");
1827 return ERROR_TARGET_NOT_HALTED
;
1830 /* sanitize arguments */
1831 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1832 return ERROR_INVALID_ARGUMENTS
;
1834 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1835 return ERROR_TARGET_UNALIGNED_ACCESS
;
1837 /* load the base register with the address of the first word */
1839 arm7_9
->write_core_regs(target
, 0x1, reg
);
1844 while (num_accesses
< count
)
1847 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1848 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1850 if (last_reg
<= thisrun_accesses
)
1851 last_reg
= thisrun_accesses
;
1853 arm7_9
->load_word_regs(target
, reg_list
);
1855 /* fast memory reads are only safe when the target is running
1856 * from a sufficiently high clock (32 kHz is usually too slow)
1858 if (arm7_9
->fast_memory_access
)
1859 arm7_9_execute_fast_sys_speed(target
);
1861 arm7_9_execute_sys_speed(target
);
1863 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
1865 /* advance buffer, count number of accesses */
1866 buffer
+= thisrun_accesses
* 4;
1867 num_accesses
+= thisrun_accesses
;
1871 while (num_accesses
< count
)
1874 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1875 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1877 for (i
= 1; i
<= thisrun_accesses
; i
++)
1881 arm7_9
->load_hword_reg(target
, i
);
1882 /* fast memory reads are only safe when the target is running
1883 * from a sufficiently high clock (32 kHz is usually too slow)
1885 if (arm7_9
->fast_memory_access
)
1886 arm7_9_execute_fast_sys_speed(target
);
1888 arm7_9_execute_sys_speed(target
);
1891 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
1893 /* advance buffer, count number of accesses */
1894 buffer
+= thisrun_accesses
* 2;
1895 num_accesses
+= thisrun_accesses
;
1899 while (num_accesses
< count
)
1902 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1903 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1905 for (i
= 1; i
<= thisrun_accesses
; i
++)
1909 arm7_9
->load_byte_reg(target
, i
);
1910 /* fast memory reads are only safe when the target is running
1911 * from a sufficiently high clock (32 kHz is usually too slow)
1913 if (arm7_9
->fast_memory_access
)
1914 arm7_9_execute_fast_sys_speed(target
);
1916 arm7_9_execute_sys_speed(target
);
1919 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
1921 /* advance buffer, count number of accesses */
1922 buffer
+= thisrun_accesses
* 1;
1923 num_accesses
+= thisrun_accesses
;
1927 ERROR("BUG: we shouldn't get here");
1932 for (i
=0; i
<=last_reg
; i
++)
1933 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
1935 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1936 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1938 ERROR("JTAG error while reading cpsr");
1939 return ERROR_TARGET_DATA_ABORT
;
1942 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1944 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1946 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1948 return ERROR_TARGET_DATA_ABORT
;
1954 int arm7_9_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1956 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1957 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1958 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1961 int num_accesses
= 0;
1962 int thisrun_accesses
;
1968 #ifdef _DEBUG_ARM7_9_
1969 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1972 if (target
->state
!= TARGET_HALTED
)
1974 WARNING("target not halted");
1975 return ERROR_TARGET_NOT_HALTED
;
1978 /* sanitize arguments */
1979 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1980 return ERROR_INVALID_ARGUMENTS
;
1982 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1983 return ERROR_TARGET_UNALIGNED_ACCESS
;
1985 /* load the base register with the address of the first word */
1987 arm7_9
->write_core_regs(target
, 0x1, reg
);
1989 /* Clear DBGACK, to make sure memory fetches work as expected */
1990 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1991 embeddedice_store_reg(dbg_ctrl
);
1996 while (num_accesses
< count
)
1999 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2000 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2002 for (i
= 1; i
<= thisrun_accesses
; i
++)
2006 reg
[i
] = target_buffer_get_u32(target
, buffer
);
2010 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2012 arm7_9
->store_word_regs(target
, reg_list
);
2014 /* fast memory writes are only safe when the target is running
2015 * from a sufficiently high clock (32 kHz is usually too slow)
2017 if (arm7_9
->fast_memory_access
)
2018 arm7_9_execute_fast_sys_speed(target
);
2020 arm7_9_execute_sys_speed(target
);
2022 num_accesses
+= thisrun_accesses
;
2026 while (num_accesses
< count
)
2029 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2030 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2032 for (i
= 1; i
<= thisrun_accesses
; i
++)
2036 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
2040 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2042 for (i
= 1; i
<= thisrun_accesses
; i
++)
2044 arm7_9
->store_hword_reg(target
, i
);
2046 /* fast memory writes are only safe when the target is running
2047 * from a sufficiently high clock (32 kHz is usually too slow)
2049 if (arm7_9
->fast_memory_access
)
2050 arm7_9_execute_fast_sys_speed(target
);
2052 arm7_9_execute_sys_speed(target
);
2055 num_accesses
+= thisrun_accesses
;
2059 while (num_accesses
< count
)
2062 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2063 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2065 for (i
= 1; i
<= thisrun_accesses
; i
++)
2069 reg
[i
] = *buffer
++ & 0xff;
2072 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2074 for (i
= 1; i
<= thisrun_accesses
; i
++)
2076 arm7_9
->store_byte_reg(target
, i
);
2077 /* fast memory writes are only safe when the target is running
2078 * from a sufficiently high clock (32 kHz is usually too slow)
2080 if (arm7_9
->fast_memory_access
)
2081 arm7_9_execute_fast_sys_speed(target
);
2083 arm7_9_execute_sys_speed(target
);
2086 num_accesses
+= thisrun_accesses
;
2090 ERROR("BUG: we shouldn't get here");
2096 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
2097 embeddedice_store_reg(dbg_ctrl
);
2099 for (i
=0; i
<=last_reg
; i
++)
2100 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2102 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2103 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2105 ERROR("JTAG error while reading cpsr");
2106 return ERROR_TARGET_DATA_ABORT
;
2109 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2111 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
2113 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2115 return ERROR_TARGET_DATA_ABORT
;
2121 int arm7_9_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2123 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2124 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2125 enum armv4_5_state core_state
= armv4_5
->core_state
;
2126 u32 r0
= buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32);
2127 u32 r1
= buf_get_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32);
2128 u32 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2133 /* MRC TST BNE MRC STR B */
2134 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2137 if (!arm7_9
->dcc_downloads
)
2138 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2140 /* regrab previously allocated working_area, or allocate a new one */
2141 if (!arm7_9
->dcc_working_area
)
2143 u8 dcc_code_buf
[6 * 4];
2145 /* make sure we have a working area */
2146 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2148 INFO("no working area available, falling back to memory writes");
2149 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2152 /* copy target instructions to target endianness */
2153 for (i
= 0; i
< 6; i
++)
2155 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2158 /* write DCC code to working area */
2159 target
->type
->write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
);
2162 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, address
);
2163 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2164 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2165 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
2167 arm7_9_resume(target
, 0, arm7_9
->dcc_working_area
->address
, 1, 1);
2169 for (i
= 0; i
< count
; i
++)
2171 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], target_buffer_get_u32(target
, buffer
));
2175 target
->type
->halt(target
);
2177 while (target
->state
!= TARGET_HALTED
)
2178 target
->type
->poll(target
);
2180 /* restore target state */
2181 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, r0
);
2182 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2183 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2184 buf_set_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32, r1
);
2185 armv4_5
->core_cache
->reg_list
[1].valid
= 1;
2186 armv4_5
->core_cache
->reg_list
[1].dirty
= 1;
2187 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
2188 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
2189 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
2190 armv4_5
->core_state
= core_state
;
2195 int arm7_9_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
2197 working_area_t
*crc_algorithm
;
2198 armv4_5_algorithm_t armv4_5_info
;
2199 reg_param_t reg_params
[2];
2202 u32 arm7_9_crc_code
[] = {
2203 0xE1A02000, /* mov r2, r0 */
2204 0xE3E00000, /* mov r0, #0xffffffff */
2205 0xE1A03001, /* mov r3, r1 */
2206 0xE3A04000, /* mov r4, #0 */
2207 0xEA00000B, /* b ncomp */
2209 0xE7D21004, /* ldrb r1, [r2, r4] */
2210 0xE59F7030, /* ldr r7, CRC32XOR */
2211 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2212 0xE3A05000, /* mov r5, #0 */
2214 0xE3500000, /* cmp r0, #0 */
2215 0xE1A06080, /* mov r6, r0, asl #1 */
2216 0xE2855001, /* add r5, r5, #1 */
2217 0xE1A00006, /* mov r0, r6 */
2218 0xB0260007, /* eorlt r0, r6, r7 */
2219 0xE3550008, /* cmp r5, #8 */
2220 0x1AFFFFF8, /* bne loop */
2221 0xE2844001, /* add r4, r4, #1 */
2223 0xE1540003, /* cmp r4, r3 */
2224 0x1AFFFFF1, /* bne nbyte */
2226 0xEAFFFFFE, /* b end */
2227 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2232 if (target_alloc_working_area(target
, sizeof(arm7_9_crc_code
), &crc_algorithm
) != ERROR_OK
)
2234 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2237 /* convert flash writing code into a buffer in target endianness */
2238 for (i
= 0; i
< (sizeof(arm7_9_crc_code
)/sizeof(u32
)); i
++)
2239 target_write_u32(target
, crc_algorithm
->address
+ i
*sizeof(u32
), arm7_9_crc_code
[i
]);
2241 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2242 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2243 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2245 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2246 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2248 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2249 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
2251 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
2252 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(arm7_9_crc_code
) - 8), 20000, &armv4_5_info
)) != ERROR_OK
)
2254 ERROR("error executing arm7_9 crc algorithm");
2255 destroy_reg_param(®_params
[0]);
2256 destroy_reg_param(®_params
[1]);
2257 target_free_working_area(target
, crc_algorithm
);
2261 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
2263 destroy_reg_param(®_params
[0]);
2264 destroy_reg_param(®_params
[1]);
2266 target_free_working_area(target
, crc_algorithm
);
2271 int arm7_9_register_commands(struct command_context_s
*cmd_ctx
)
2273 command_t
*arm7_9_cmd
;
2275 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9", NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2277 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr", handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
, "write program status register <value> <not cpsr|spsr>");
2278 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2280 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg", handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
, "write core register <num> <mode> <value>");
2282 register_command(cmd_ctx
, arm7_9_cmd
, "sw_bkpts", handle_arm7_9_sw_bkpts_command
, COMMAND_EXEC
, "support for software breakpoints <enable|disable>");
2283 register_command(cmd_ctx
, arm7_9_cmd
, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command
, COMMAND_EXEC
, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2284 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq", handle_arm7_9_dbgrq_command
,
2285 COMMAND_ANY
, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2286 register_command(cmd_ctx
, arm7_9_cmd
, "fast_writes", handle_arm7_9_fast_memory_access_command
,
2287 COMMAND_ANY
, "(deprecated, see: arm7_9 fast_memory_access)");
2288 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access", handle_arm7_9_fast_memory_access_command
,
2289 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2290 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads", handle_arm7_9_dcc_downloads_command
,
2291 COMMAND_ANY
, "use DCC downloads for larger memory writes <enable|disable>");
2293 armv4_5_register_commands(cmd_ctx
);
2295 etm_register_commands(cmd_ctx
);
2300 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2305 target_t
*target
= get_current_target(cmd_ctx
);
2306 armv4_5_common_t
*armv4_5
;
2307 arm7_9_common_t
*arm7_9
;
2309 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2311 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2315 if (target
->state
!= TARGET_HALTED
)
2317 command_print(cmd_ctx
, "can't write registers while running");
2323 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr|spsr>");
2327 value
= strtoul(args
[0], NULL
, 0);
2328 spsr
= strtol(args
[1], NULL
, 0);
2330 /* if we're writing the CPSR, mask the T bit */
2334 arm7_9
->write_xpsr(target
, value
, spsr
);
2335 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2337 ERROR("JTAG error while writing to xpsr");
2344 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2350 target_t
*target
= get_current_target(cmd_ctx
);
2351 armv4_5_common_t
*armv4_5
;
2352 arm7_9_common_t
*arm7_9
;
2354 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2356 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2360 if (target
->state
!= TARGET_HALTED
)
2362 command_print(cmd_ctx
, "can't write registers while running");
2368 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2372 value
= strtoul(args
[0], NULL
, 0);
2373 rotate
= strtol(args
[1], NULL
, 0);
2374 spsr
= strtol(args
[2], NULL
, 0);
2376 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2377 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2379 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2386 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2391 target_t
*target
= get_current_target(cmd_ctx
);
2392 armv4_5_common_t
*armv4_5
;
2393 arm7_9_common_t
*arm7_9
;
2395 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2397 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2401 if (target
->state
!= TARGET_HALTED
)
2403 command_print(cmd_ctx
, "can't write registers while running");
2409 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
2413 num
= strtol(args
[0], NULL
, 0);
2414 mode
= strtoul(args
[1], NULL
, 0);
2415 value
= strtoul(args
[2], NULL
, 0);
2417 arm7_9_write_core_reg(target
, num
, mode
, value
);
2422 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2424 target_t
*target
= get_current_target(cmd_ctx
);
2425 armv4_5_common_t
*armv4_5
;
2426 arm7_9_common_t
*arm7_9
;
2428 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2430 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2436 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2440 if (strcmp("enable", args
[0]) == 0)
2442 if (arm7_9
->sw_bkpts_use_wp
)
2444 arm7_9_enable_sw_bkpts(target
);
2448 arm7_9
->sw_bkpts_enabled
= 1;
2451 else if (strcmp("disable", args
[0]) == 0)
2453 if (arm7_9
->sw_bkpts_use_wp
)
2455 arm7_9_disable_sw_bkpts(target
);
2459 arm7_9
->sw_bkpts_enabled
= 0;
2464 command_print(cmd_ctx
, "usage: arm7_9 sw_bkpts <enable|disable>");
2467 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2472 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2474 target_t
*target
= get_current_target(cmd_ctx
);
2475 armv4_5_common_t
*armv4_5
;
2476 arm7_9_common_t
*arm7_9
;
2478 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2480 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2484 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
2486 arm7_9
->force_hw_bkpts
= 1;
2487 if (arm7_9
->sw_bkpts_use_wp
)
2489 arm7_9_disable_sw_bkpts(target
);
2492 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
2494 arm7_9
->force_hw_bkpts
= 0;
2498 command_print(cmd_ctx
, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2501 command_print(cmd_ctx
, "force hardware breakpoints %s", (arm7_9
->force_hw_bkpts
) ? "enabled" : "disabled");
2506 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2508 target_t
*target
= get_current_target(cmd_ctx
);
2509 armv4_5_common_t
*armv4_5
;
2510 arm7_9_common_t
*arm7_9
;
2512 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2514 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2520 if (strcmp("enable", args
[0]) == 0)
2522 arm7_9
->use_dbgrq
= 1;
2524 else if (strcmp("disable", args
[0]) == 0)
2526 arm7_9
->use_dbgrq
= 0;
2530 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable|disable>");
2534 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2539 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2541 target_t
*target
= get_current_target(cmd_ctx
);
2542 armv4_5_common_t
*armv4_5
;
2543 arm7_9_common_t
*arm7_9
;
2545 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2547 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2553 if (strcmp("enable", args
[0]) == 0)
2555 arm7_9
->fast_memory_access
= 1;
2557 else if (strcmp("disable", args
[0]) == 0)
2559 arm7_9
->fast_memory_access
= 0;
2563 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable|disable>");
2567 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2572 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2574 target_t
*target
= get_current_target(cmd_ctx
);
2575 armv4_5_common_t
*armv4_5
;
2576 arm7_9_common_t
*arm7_9
;
2578 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2580 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2586 if (strcmp("enable", args
[0]) == 0)
2588 arm7_9
->dcc_downloads
= 1;
2590 else if (strcmp("disable", args
[0]) == 0)
2592 arm7_9
->dcc_downloads
= 0;
2596 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable|disable>");
2600 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2605 int arm7_9_init_arch_info(target_t
*target
, arm7_9_common_t
*arm7_9
)
2607 armv4_5_common_t
*armv4_5
= &arm7_9
->armv4_5_common
;
2609 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2611 arm_jtag_setup_connection(&arm7_9
->jtag_info
);
2612 arm7_9
->wp_available
= 2;
2613 arm7_9
->wp0_used
= 0;
2614 arm7_9
->wp1_used
= 0;
2615 arm7_9
->force_hw_bkpts
= 0;
2616 arm7_9
->use_dbgrq
= 0;
2618 arm7_9
->etm_ctx
= NULL
;
2619 arm7_9
->has_single_step
= 0;
2620 arm7_9
->has_monitor_mode
= 0;
2621 arm7_9
->has_vector_catch
= 0;
2623 arm7_9
->reinit_embeddedice
= 0;
2625 arm7_9
->debug_entry_from_reset
= 0;
2627 arm7_9
->dcc_working_area
= NULL
;
2629 arm7_9
->fast_memory_access
= 0;
2630 arm7_9
->dcc_downloads
= 0;
2632 jtag_register_event_callback(arm7_9_jtag_callback
, target
);
2634 armv4_5
->arch_info
= arm7_9
;
2635 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2636 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2637 armv4_5
->full_context
= arm7_9_full_context
;
2639 armv4_5_init_arch_info(target
, armv4_5
);
2641 target_register_timer_callback(arm7_9_handle_target_request
, 1, 1, target
);
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