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- reverted some of the changes that possibly broke arm926ejs. Waiting
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "target_request.h"
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "jtag.h"
32 #include "log.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 #include <sys/types.h>
41 #include <sys/stat.h>
42 #include <sys/time.h>
43 #include <errno.h>
44
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
47
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 arm7_9->reinit_embeddedice = 0;
88
89 return ERROR_OK;
90 }
91
92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 {
94 target_t *target = priv;
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
101 */
102 if (event == JTAG_TRST_ASSERTED)
103 {
104 arm7_9->reinit_embeddedice = 1;
105 }
106
107 return ERROR_OK;
108 }
109
110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 {
112 armv4_5_common_t *armv4_5 = target->arch_info;
113 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114
115 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
116 {
117 return -1;
118 }
119
120 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
121 {
122 return -1;
123 }
124
125 *armv4_5_p = armv4_5;
126 *arm7_9_p = arm7_9;
127
128 return ERROR_OK;
129 }
130
131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 {
133 armv4_5_common_t *armv4_5 = target->arch_info;
134 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135
136 if (target->state != TARGET_HALTED)
137 {
138 LOG_WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED;
140 }
141
142 if (arm7_9->force_hw_bkpts)
143 breakpoint->type = BKPT_HARD;
144
145 if (breakpoint->set)
146 {
147 LOG_WARNING("breakpoint already set");
148 return ERROR_OK;
149 }
150
151 if (breakpoint->type == BKPT_HARD)
152 {
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
155 if (!arm7_9->wp0_used)
156 {
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162
163 jtag_execute_queue();
164 arm7_9->wp0_used = 1;
165 breakpoint->set = 1;
166 }
167 else if (!arm7_9->wp1_used)
168 {
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
173 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174
175 jtag_execute_queue();
176 arm7_9->wp1_used = 1;
177 breakpoint->set = 2;
178 }
179 else
180 {
181 LOG_ERROR("BUG: no hardware comparator available");
182 return ERROR_OK;
183 }
184 }
185 else if (breakpoint->type == BKPT_SOFT)
186 {
187 if (breakpoint->length == 4)
188 {
189 u32 verify = 0xffffffff;
190 /* keep the original instruction in target endianness */
191 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
192 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
193 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
194
195 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
196 if (verify != arm7_9->arm_bkpt)
197 {
198 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
199 return ERROR_OK;
200 }
201 }
202 else
203 {
204 u16 verify = 0xffff;
205 /* keep the original instruction in target endianness */
206 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
207 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
208 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
209
210 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
211 if (verify != arm7_9->thumb_bkpt)
212 {
213 LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
214 return ERROR_OK;
215 }
216 }
217 breakpoint->set = 1;
218 }
219
220 return ERROR_OK;
221
222 }
223
224 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
225 {
226 armv4_5_common_t *armv4_5 = target->arch_info;
227 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
228
229 if (target->state != TARGET_HALTED)
230 {
231 LOG_WARNING("target not halted");
232 return ERROR_TARGET_NOT_HALTED;
233 }
234
235 if (!breakpoint->set)
236 {
237 LOG_WARNING("breakpoint not set");
238 return ERROR_OK;
239 }
240
241 if (breakpoint->type == BKPT_HARD)
242 {
243 if (breakpoint->set == 1)
244 {
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
246 jtag_execute_queue();
247 arm7_9->wp0_used = 0;
248 }
249 else if (breakpoint->set == 2)
250 {
251 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
252 jtag_execute_queue();
253 arm7_9->wp1_used = 0;
254 }
255 breakpoint->set = 0;
256 }
257 else
258 {
259 /* restore original instruction (kept in target endianness) */
260 if (breakpoint->length == 4)
261 {
262 u32 current_instr;
263 /* check that user program as not modified breakpoint instruction */
264 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
265 if (current_instr==arm7_9->arm_bkpt)
266 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
267 }
268 else
269 {
270 u16 current_instr;
271 /* check that user program as not modified breakpoint instruction */
272 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
273 if (current_instr==arm7_9->thumb_bkpt)
274 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
275 }
276 breakpoint->set = 0;
277 }
278
279 return ERROR_OK;
280 }
281
282 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
283 {
284 armv4_5_common_t *armv4_5 = target->arch_info;
285 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
286
287 if (target->state != TARGET_HALTED)
288 {
289 LOG_WARNING("target not halted");
290 return ERROR_TARGET_NOT_HALTED;
291 }
292
293 if (arm7_9->force_hw_bkpts)
294 {
295 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
296 breakpoint->type = BKPT_HARD;
297 }
298
299 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
300 {
301 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
302 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
303 }
304
305 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
306 {
307 LOG_INFO("no watchpoint unit available for hardware breakpoint");
308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
309 }
310
311 if ((breakpoint->length != 2) && (breakpoint->length != 4))
312 {
313 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
315 }
316
317 if (breakpoint->type == BKPT_HARD)
318 arm7_9->wp_available--;
319
320 return ERROR_OK;
321 }
322
323 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
324 {
325 armv4_5_common_t *armv4_5 = target->arch_info;
326 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327
328 if (target->state != TARGET_HALTED)
329 {
330 LOG_WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED;
332 }
333
334 if (breakpoint->set)
335 {
336 arm7_9_unset_breakpoint(target, breakpoint);
337 }
338
339 if (breakpoint->type == BKPT_HARD)
340 arm7_9->wp_available++;
341
342 return ERROR_OK;
343 }
344
345 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
346 {
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
349 int rw_mask = 1;
350 u32 mask;
351
352 mask = watchpoint->length - 1;
353
354 if (target->state != TARGET_HALTED)
355 {
356 LOG_WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED;
358 }
359
360 if (watchpoint->rw == WPT_ACCESS)
361 rw_mask = 0;
362 else
363 rw_mask = 1;
364
365 if (!arm7_9->wp0_used)
366 {
367 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
368 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
369 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
370 if( watchpoint->mask != 0xffffffffu )
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
374
375 jtag_execute_queue();
376 watchpoint->set = 1;
377 arm7_9->wp0_used = 2;
378 }
379 else if (!arm7_9->wp1_used)
380 {
381 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
382 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
383 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
384 if( watchpoint->mask != 0xffffffffu )
385 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
386 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
387 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
388
389 jtag_execute_queue();
390 watchpoint->set = 2;
391 arm7_9->wp1_used = 2;
392 }
393 else
394 {
395 LOG_ERROR("BUG: no hardware comparator available");
396 return ERROR_OK;
397 }
398
399 return ERROR_OK;
400 }
401
402 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
403 {
404 armv4_5_common_t *armv4_5 = target->arch_info;
405 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
406
407 if (target->state != TARGET_HALTED)
408 {
409 LOG_WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED;
411 }
412
413 if (!watchpoint->set)
414 {
415 LOG_WARNING("breakpoint not set");
416 return ERROR_OK;
417 }
418
419 if (watchpoint->set == 1)
420 {
421 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
422 jtag_execute_queue();
423 arm7_9->wp0_used = 0;
424 }
425 else if (watchpoint->set == 2)
426 {
427 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
428 jtag_execute_queue();
429 arm7_9->wp1_used = 0;
430 }
431 watchpoint->set = 0;
432
433 return ERROR_OK;
434 }
435
436 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
437 {
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440
441 if (target->state != TARGET_HALTED)
442 {
443 LOG_WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED;
445 }
446
447 if (arm7_9->wp_available < 1)
448 {
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
450 }
451
452 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
453 {
454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
455 }
456
457 arm7_9->wp_available--;
458
459 return ERROR_OK;
460 }
461
462 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
463 {
464 armv4_5_common_t *armv4_5 = target->arch_info;
465 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
466
467 if (target->state != TARGET_HALTED)
468 {
469 LOG_WARNING("target not halted");
470 return ERROR_TARGET_NOT_HALTED;
471 }
472
473 if (watchpoint->set)
474 {
475 arm7_9_unset_watchpoint(target, watchpoint);
476 }
477
478 arm7_9->wp_available++;
479
480 return ERROR_OK;
481 }
482
483 int arm7_9_enable_sw_bkpts(struct target_s *target)
484 {
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 int retval;
488
489 if (arm7_9->sw_bkpts_enabled)
490 return ERROR_OK;
491
492 if (arm7_9->wp_available < 1)
493 {
494 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
496 }
497 arm7_9->wp_available--;
498
499 if (!arm7_9->wp0_used)
500 {
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 1;
507 arm7_9->wp0_used = 3;
508 }
509 else if (!arm7_9->wp1_used)
510 {
511 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
512 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
513 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
514 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
515 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
516 arm7_9->sw_bkpts_enabled = 2;
517 arm7_9->wp1_used = 3;
518 }
519 else
520 {
521 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
522 return ERROR_FAIL;
523 }
524
525 if ((retval = jtag_execute_queue()) != ERROR_OK)
526 {
527 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
528 return ERROR_FAIL;
529 };
530
531 return ERROR_OK;
532 }
533
534 int arm7_9_disable_sw_bkpts(struct target_s *target)
535 {
536 armv4_5_common_t *armv4_5 = target->arch_info;
537 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
538
539 if (!arm7_9->sw_bkpts_enabled)
540 return ERROR_OK;
541
542 if (arm7_9->sw_bkpts_enabled == 1)
543 {
544 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
545 arm7_9->sw_bkpts_enabled = 0;
546 arm7_9->wp0_used = 0;
547 arm7_9->wp_available++;
548 }
549 else if (arm7_9->sw_bkpts_enabled == 2)
550 {
551 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
552 arm7_9->sw_bkpts_enabled = 0;
553 arm7_9->wp1_used = 0;
554 arm7_9->wp_available++;
555 }
556
557 return ERROR_OK;
558 }
559
560 int arm7_9_execute_sys_speed(struct target_s *target)
561 {
562 int timeout;
563 int retval;
564
565 armv4_5_common_t *armv4_5 = target->arch_info;
566 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
567 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
568 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
569
570 /* set RESTART instruction */
571 jtag_add_end_state(TAP_RTI);
572 arm_jtag_set_instr(jtag_info, 0x4, NULL);
573
574 for (timeout=0; timeout<50; timeout++)
575 {
576 /* read debug status register */
577 embeddedice_read_reg(dbg_stat);
578 if ((retval = jtag_execute_queue()) != ERROR_OK)
579 return retval;
580 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
581 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
582 break;
583 usleep(100000);
584 }
585 if (timeout == 50)
586 {
587 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
588 return ERROR_TARGET_TIMEOUT;
589 }
590
591 return ERROR_OK;
592 }
593
594 int arm7_9_execute_fast_sys_speed(struct target_s *target)
595 {
596 static int set=0;
597 static u8 check_value[4], check_mask[4];
598
599 armv4_5_common_t *armv4_5 = target->arch_info;
600 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
601 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
602 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
603
604 /* set RESTART instruction */
605 jtag_add_end_state(TAP_RTI);
606 arm_jtag_set_instr(jtag_info, 0x4, NULL);
607
608 if (!set)
609 {
610 /* check for DBGACK and SYSCOMP set (others don't care) */
611
612 /* NB! These are constants that must be available until after next jtag_execute() and
613 we evaluate the values upon first execution in lieu of setting up these constants
614 during early setup.
615 */
616 buf_set_u32(check_value, 0, 32, 0x9);
617 buf_set_u32(check_mask, 0, 32, 0x9);
618 set=1;
619 }
620
621 /* read debug status register */
622 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
623
624 return ERROR_OK;
625 }
626
627 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
628 {
629 armv4_5_common_t *armv4_5 = target->arch_info;
630 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
631 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
632 u32 *data;
633 int i;
634
635 data = malloc(size * (sizeof(u32)));
636
637 embeddedice_receive(jtag_info, data, size);
638
639 for (i = 0; i < size; i++)
640 {
641 h_u32_to_le(buffer + (i * 4), data[i]);
642 }
643
644 free(data);
645
646 return ERROR_OK;
647 }
648
649 int arm7_9_handle_target_request(void *priv)
650 {
651 target_t *target = priv;
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
656
657 if (!target->dbg_msg_enabled)
658 return ERROR_OK;
659
660 if (target->state == TARGET_RUNNING)
661 {
662 /* read DCC control register */
663 embeddedice_read_reg(dcc_control);
664 jtag_execute_queue();
665
666 /* check W bit */
667 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
668 {
669 u32 request;
670
671 embeddedice_receive(jtag_info, &request, 1);
672 target_request(target, request);
673 }
674 }
675
676 return ERROR_OK;
677 }
678
679 int arm7_9_poll(target_t *target)
680 {
681 int retval;
682 armv4_5_common_t *armv4_5 = target->arch_info;
683 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
684 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
685
686 if (arm7_9->reinit_embeddedice)
687 {
688 arm7_9_reinit_embeddedice(target);
689 }
690
691 /* read debug status register */
692 embeddedice_read_reg(dbg_stat);
693 if ((retval = jtag_execute_queue()) != ERROR_OK)
694 {
695 return retval;
696 }
697
698 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
699 {
700 LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
701 if (target->state == TARGET_UNKNOWN)
702 {
703 target->state = TARGET_RUNNING;
704 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
705 }
706 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
707 {
708 target->state = TARGET_HALTED;
709 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
710 return retval;
711
712 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
713 }
714 if (target->state == TARGET_DEBUG_RUNNING)
715 {
716 target->state = TARGET_HALTED;
717 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
718 return retval;
719
720 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
721 }
722 if (target->state != TARGET_HALTED)
723 {
724 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
725 }
726 }
727 else
728 {
729 if (target->state != TARGET_DEBUG_RUNNING)
730 target->state = TARGET_RUNNING;
731 }
732
733 return ERROR_OK;
734 }
735
736 /*
737 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
738 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
739 while the core is held in reset. It isn't possible to program the halt
740 condition once reset was asserted, hence a hook that allows the target to set
741 up its reset-halt condition prior to asserting reset.
742 */
743
744 int arm7_9_assert_reset(target_t *target)
745 {
746 armv4_5_common_t *armv4_5 = target->arch_info;
747 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
748 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
749
750 if (!(jtag_reset_config & RESET_HAS_SRST))
751 {
752 LOG_ERROR("Can't assert SRST");
753 return ERROR_FAIL;
754 }
755
756 /*
757 * Some targets do not support communication while TRST is asserted. We need to
758 * set up the reset vector catch here.
759 *
760 * If TRST is in use, then these settings will be reset anyway, so setting them
761 * here is harmless.
762 */
763 if (arm7_9->has_vector_catch)
764 {
765 /* program vector catch register to catch reset vector */
766 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
767 }
768 else
769 {
770 /* program watchpoint unit to match on reset vector address */
771 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
772 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
773 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
774 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
775 }
776
777 /* we can't know what state the target is in as we might e.g.
778 * be resetting after a power dropout, so we need to issue a tms/srst
779 */
780
781
782 /* assert SRST and TRST */
783 /* system would get ouf sync if we didn't reset test-logic, too */
784 jtag_add_reset(1, 1);
785
786 jtag_add_sleep(5000);
787
788 /* here we should issue a srst only, but we may have to assert trst as well */
789 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
790 {
791 jtag_add_reset(1, 1);
792 } else
793 {
794 jtag_add_reset(0, 1);
795 }
796
797
798 target->state = TARGET_RESET;
799 jtag_add_sleep(50000);
800
801 armv4_5_invalidate_core_regs(target);
802
803 return ERROR_OK;
804
805 }
806
807 int arm7_9_deassert_reset(target_t *target)
808 {
809 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
810
811 /* deassert reset lines */
812 jtag_add_reset(0, 0);
813
814 return ERROR_OK;
815 }
816
817 int arm7_9_clear_halt(target_t *target)
818 {
819 armv4_5_common_t *armv4_5 = target->arch_info;
820 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
821 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
822
823 /* we used DBGRQ only if we didn't come out of reset */
824 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
825 {
826 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
827 */
828 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
829 embeddedice_store_reg(dbg_ctrl);
830 }
831 else
832 {
833 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
834 {
835 /* if we came out of reset, and vector catch is supported, we used
836 * vector catch to enter debug state
837 * restore the register in that case
838 */
839 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
840 }
841 else
842 {
843 /* restore registers if watchpoint unit 0 was in use
844 */
845 if (arm7_9->wp0_used)
846 {
847 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
848 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
849 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
850 }
851 /* control value always has to be restored, as it was either disabled,
852 * or enabled with possibly different bits
853 */
854 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
855 }
856 }
857
858 return ERROR_OK;
859 }
860
861 int arm7_9_soft_reset_halt(struct target_s *target)
862 {
863 armv4_5_common_t *armv4_5 = target->arch_info;
864 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
865 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
866 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
867 int i;
868 int retval;
869
870 if ((retval=target->type->halt(target))!=ERROR_OK)
871 return retval;
872
873 for (i=0; i<10; i++)
874 {
875 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
876 break;
877 embeddedice_read_reg(dbg_stat);
878 if ((retval=jtag_execute_queue())!=ERROR_OK)
879 return retval;
880 /* do not eat all CPU, time out after 1 se*/
881 usleep(100*1000);
882
883 }
884 if (i==10)
885 {
886 LOG_ERROR("Failed to halt CPU after 1 sec");
887 return ERROR_TARGET_TIMEOUT;
888 }
889 target->state = TARGET_HALTED;
890
891 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
892 * ensure that DBGRQ is cleared
893 */
894 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
895 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
896 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
897 embeddedice_store_reg(dbg_ctrl);
898
899 arm7_9_clear_halt(target);
900
901 /* if the target is in Thumb state, change to ARM state */
902 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
903 {
904 u32 r0_thumb, pc_thumb;
905 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
906 /* Entered debug from Thumb mode */
907 armv4_5->core_state = ARMV4_5_STATE_THUMB;
908 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
909 }
910
911 /* all register content is now invalid */
912 armv4_5_invalidate_core_regs(target);
913
914 /* SVC, ARM state, IRQ and FIQ disabled */
915 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
916 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
917 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
918
919 /* start fetching from 0x0 */
920 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
921 armv4_5->core_cache->reg_list[15].dirty = 1;
922 armv4_5->core_cache->reg_list[15].valid = 1;
923
924 armv4_5->core_mode = ARMV4_5_MODE_SVC;
925 armv4_5->core_state = ARMV4_5_STATE_ARM;
926
927 /* reset registers */
928 for (i = 0; i <= 14; i++)
929 {
930 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
931 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
932 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
933 }
934
935 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
936
937 return ERROR_OK;
938 }
939
940 int arm7_9_halt(target_t *target)
941 {
942 armv4_5_common_t *armv4_5 = target->arch_info;
943 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
944 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
945
946 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
947
948 if (target->state == TARGET_HALTED)
949 {
950 LOG_DEBUG("target was already halted");
951 return ERROR_OK;
952 }
953
954 if (target->state == TARGET_UNKNOWN)
955 {
956 LOG_WARNING("target was in unknown state when halt was requested");
957 }
958
959 if (target->state == TARGET_RESET)
960 {
961 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
962 {
963 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
964 return ERROR_TARGET_FAILURE;
965 }
966 }
967
968 if (arm7_9->use_dbgrq)
969 {
970 /* program EmbeddedICE Debug Control Register to assert DBGRQ
971 */
972 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
973 embeddedice_store_reg(dbg_ctrl);
974 }
975 else
976 {
977 /* program watchpoint unit to match on any address
978 */
979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
980 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
981 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
982 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
983 }
984
985 target->debug_reason = DBG_REASON_DBGRQ;
986
987 return ERROR_OK;
988 }
989
990 int arm7_9_debug_entry(target_t *target)
991 {
992 int i;
993 u32 context[16];
994 u32* context_p[16];
995 u32 r0_thumb, pc_thumb;
996 u32 cpsr;
997 int retval;
998 /* get pointers to arch-specific information */
999 armv4_5_common_t *armv4_5 = target->arch_info;
1000 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1001 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1002 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1003
1004 #ifdef _DEBUG_ARM7_9_
1005 LOG_DEBUG("-");
1006 #endif
1007
1008 if (arm7_9->pre_debug_entry)
1009 arm7_9->pre_debug_entry(target);
1010
1011 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1012 * ensure that DBGRQ is cleared
1013 */
1014 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1015 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1016 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1017 embeddedice_store_reg(dbg_ctrl);
1018
1019 arm7_9_clear_halt(target);
1020
1021 if ((retval = jtag_execute_queue()) != ERROR_OK)
1022 {
1023 switch (retval)
1024 {
1025 case ERROR_JTAG_QUEUE_FAILED:
1026 LOG_ERROR("JTAG queue failed while writing EmbeddedICE control register");
1027 exit(-1);
1028 break;
1029 default:
1030 break;
1031 }
1032 }
1033
1034 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1035 return retval;
1036
1037
1038 if (target->state != TARGET_HALTED)
1039 {
1040 LOG_WARNING("target not halted");
1041 return ERROR_TARGET_NOT_HALTED;
1042 }
1043
1044 /* if the target is in Thumb state, change to ARM state */
1045 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1046 {
1047 LOG_DEBUG("target entered debug from Thumb state");
1048 /* Entered debug from Thumb mode */
1049 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1050 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1051 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1052 }
1053 else
1054 {
1055 LOG_DEBUG("target entered debug from ARM state");
1056 /* Entered debug from ARM mode */
1057 armv4_5->core_state = ARMV4_5_STATE_ARM;
1058 }
1059
1060 for (i = 0; i < 16; i++)
1061 context_p[i] = &context[i];
1062 /* save core registers (r0 - r15 of current core mode) */
1063 arm7_9->read_core_regs(target, 0xffff, context_p);
1064
1065 arm7_9->read_xpsr(target, &cpsr, 0);
1066
1067 if ((retval = jtag_execute_queue()) != ERROR_OK)
1068 return retval;
1069
1070 /* if the core has been executing in Thumb state, set the T bit */
1071 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1072 cpsr |= 0x20;
1073
1074 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1075 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1076 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1077
1078 armv4_5->core_mode = cpsr & 0x1f;
1079
1080 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1081 {
1082 target->state = TARGET_UNKNOWN;
1083 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1084 return ERROR_TARGET_FAILURE;
1085 }
1086
1087 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1088
1089 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1090 {
1091 LOG_DEBUG("thumb state, applying fixups");
1092 context[0] = r0_thumb;
1093 context[15] = pc_thumb;
1094 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1095 {
1096 /* adjust value stored by STM */
1097 context[15] -= 3 * 4;
1098 }
1099
1100 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1101 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1102 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1103 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1104 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1105 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1106 else if (target->debug_reason == DBG_REASON_DBGRQ)
1107 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1108 else
1109 {
1110 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1111 }
1112
1113
1114 for (i=0; i<=15; i++)
1115 {
1116 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1117 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1118 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1119 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1120 }
1121
1122 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1123
1124 /* exceptions other than USR & SYS have a saved program status register */
1125 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1126 {
1127 u32 spsr;
1128 arm7_9->read_xpsr(target, &spsr, 1);
1129 jtag_execute_queue();
1130 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1131 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1132 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1133 }
1134
1135 /* r0 and r15 (pc) have to be restored later */
1136 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1137 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1138
1139 if ((retval = jtag_execute_queue()) != ERROR_OK)
1140 return retval;
1141
1142 if (arm7_9->post_debug_entry)
1143 arm7_9->post_debug_entry(target);
1144
1145 return ERROR_OK;
1146 }
1147
1148 int arm7_9_full_context(target_t *target)
1149 {
1150 int i;
1151 int retval;
1152 armv4_5_common_t *armv4_5 = target->arch_info;
1153 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1154
1155 LOG_DEBUG("-");
1156
1157 if (target->state != TARGET_HALTED)
1158 {
1159 LOG_WARNING("target not halted");
1160 return ERROR_TARGET_NOT_HALTED;
1161 }
1162
1163 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1164 * SYS shares registers with User, so we don't touch SYS
1165 */
1166 for(i = 0; i < 6; i++)
1167 {
1168 u32 mask = 0;
1169 u32* reg_p[16];
1170 int j;
1171 int valid = 1;
1172
1173 /* check if there are invalid registers in the current mode
1174 */
1175 for (j = 0; j <= 16; j++)
1176 {
1177 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1178 valid = 0;
1179 }
1180
1181 if (!valid)
1182 {
1183 u32 tmp_cpsr;
1184
1185 /* change processor mode (and mask T bit) */
1186 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1187 tmp_cpsr |= armv4_5_number_to_mode(i);
1188 tmp_cpsr &= ~0x20;
1189 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1190
1191 for (j = 0; j < 15; j++)
1192 {
1193 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1194 {
1195 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1196 mask |= 1 << j;
1197 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1198 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1199 }
1200 }
1201
1202 /* if only the PSR is invalid, mask is all zeroes */
1203 if (mask)
1204 arm7_9->read_core_regs(target, mask, reg_p);
1205
1206 /* check if the PSR has to be read */
1207 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1208 {
1209 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1210 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1211 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1212 }
1213 }
1214 }
1215
1216 /* restore processor mode (mask T bit) */
1217 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1218
1219 if ((retval = jtag_execute_queue()) != ERROR_OK)
1220 {
1221 return retval;
1222 }
1223 return ERROR_OK;
1224 }
1225
1226 int arm7_9_restore_context(target_t *target)
1227 {
1228 armv4_5_common_t *armv4_5 = target->arch_info;
1229 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1230 reg_t *reg;
1231 armv4_5_core_reg_t *reg_arch_info;
1232 enum armv4_5_mode current_mode = armv4_5->core_mode;
1233 int i, j;
1234 int dirty;
1235 int mode_change;
1236
1237 LOG_DEBUG("-");
1238
1239 if (target->state != TARGET_HALTED)
1240 {
1241 LOG_WARNING("target not halted");
1242 return ERROR_TARGET_NOT_HALTED;
1243 }
1244
1245 if (arm7_9->pre_restore_context)
1246 arm7_9->pre_restore_context(target);
1247
1248 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1249 * SYS shares registers with User, so we don't touch SYS
1250 */
1251 for (i = 0; i < 6; i++)
1252 {
1253 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1254 dirty = 0;
1255 mode_change = 0;
1256 /* check if there are dirty registers in the current mode
1257 */
1258 for (j = 0; j <= 16; j++)
1259 {
1260 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1261 reg_arch_info = reg->arch_info;
1262 if (reg->dirty == 1)
1263 {
1264 if (reg->valid == 1)
1265 {
1266 dirty = 1;
1267 LOG_DEBUG("examining dirty reg: %s", reg->name);
1268 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1269 && (reg_arch_info->mode != current_mode)
1270 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1271 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1272 {
1273 mode_change = 1;
1274 LOG_DEBUG("require mode change");
1275 }
1276 }
1277 else
1278 {
1279 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1280 }
1281 }
1282 }
1283
1284 if (dirty)
1285 {
1286 u32 mask = 0x0;
1287 int num_regs = 0;
1288 u32 regs[16];
1289
1290 if (mode_change)
1291 {
1292 u32 tmp_cpsr;
1293
1294 /* change processor mode (mask T bit) */
1295 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1296 tmp_cpsr |= armv4_5_number_to_mode(i);
1297 tmp_cpsr &= ~0x20;
1298 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1299 current_mode = armv4_5_number_to_mode(i);
1300 }
1301
1302 for (j = 0; j <= 14; j++)
1303 {
1304 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1305 reg_arch_info = reg->arch_info;
1306
1307
1308 if (reg->dirty == 1)
1309 {
1310 regs[j] = buf_get_u32(reg->value, 0, 32);
1311 mask |= 1 << j;
1312 num_regs++;
1313 reg->dirty = 0;
1314 reg->valid = 1;
1315 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1316 }
1317 }
1318
1319 if (mask)
1320 {
1321 arm7_9->write_core_regs(target, mask, regs);
1322 }
1323
1324 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1325 reg_arch_info = reg->arch_info;
1326 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1327 {
1328 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1329 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1330 }
1331 }
1332 }
1333
1334 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1335 {
1336 /* restore processor mode (mask T bit) */
1337 u32 tmp_cpsr;
1338
1339 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1340 tmp_cpsr |= armv4_5_number_to_mode(i);
1341 tmp_cpsr &= ~0x20;
1342 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1343 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1344 }
1345 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1346 {
1347 /* CPSR has been changed, full restore necessary (mask T bit) */
1348 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1349 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1350 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1351 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1352 }
1353
1354 /* restore PC */
1355 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1356 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1357 armv4_5->core_cache->reg_list[15].dirty = 0;
1358
1359 if (arm7_9->post_restore_context)
1360 arm7_9->post_restore_context(target);
1361
1362 return ERROR_OK;
1363 }
1364
1365 int arm7_9_restart_core(struct target_s *target)
1366 {
1367 armv4_5_common_t *armv4_5 = target->arch_info;
1368 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1369 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1370
1371 /* set RESTART instruction */
1372 jtag_add_end_state(TAP_RTI);
1373 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1374
1375 jtag_add_runtest(1, TAP_RTI);
1376 return jtag_execute_queue();
1377 }
1378
1379 void arm7_9_enable_watchpoints(struct target_s *target)
1380 {
1381 watchpoint_t *watchpoint = target->watchpoints;
1382
1383 while (watchpoint)
1384 {
1385 if (watchpoint->set == 0)
1386 arm7_9_set_watchpoint(target, watchpoint);
1387 watchpoint = watchpoint->next;
1388 }
1389 }
1390
1391 void arm7_9_enable_breakpoints(struct target_s *target)
1392 {
1393 breakpoint_t *breakpoint = target->breakpoints;
1394
1395 /* set any pending breakpoints */
1396 while (breakpoint)
1397 {
1398 if (breakpoint->set == 0)
1399 arm7_9_set_breakpoint(target, breakpoint);
1400 breakpoint = breakpoint->next;
1401 }
1402 }
1403
1404 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1405 {
1406 breakpoint_t *breakpoint = target->breakpoints;
1407 watchpoint_t *watchpoint = target->watchpoints;
1408
1409 /* set any pending breakpoints */
1410 while (breakpoint)
1411 {
1412 if (breakpoint->set != 0)
1413 arm7_9_unset_breakpoint(target, breakpoint);
1414 breakpoint = breakpoint->next;
1415 }
1416
1417 while (watchpoint)
1418 {
1419 if (watchpoint->set != 0)
1420 arm7_9_unset_watchpoint(target, watchpoint);
1421 watchpoint = watchpoint->next;
1422 }
1423 }
1424
1425 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1426 {
1427 armv4_5_common_t *armv4_5 = target->arch_info;
1428 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1429 breakpoint_t *breakpoint = target->breakpoints;
1430 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1431 int err;
1432
1433 LOG_DEBUG("-");
1434
1435 if (target->state != TARGET_HALTED)
1436 {
1437 LOG_WARNING("target not halted");
1438 return ERROR_TARGET_NOT_HALTED;
1439 }
1440
1441 if (!debug_execution)
1442 {
1443 target_free_all_working_areas(target);
1444 }
1445
1446 /* current = 1: continue on current pc, otherwise continue at <address> */
1447 if (!current)
1448 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1449
1450 /* the front-end may request us not to handle breakpoints */
1451 if (handle_breakpoints)
1452 {
1453 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1454 {
1455 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1456 arm7_9_unset_breakpoint(target, breakpoint);
1457
1458 LOG_DEBUG("enable single-step");
1459 arm7_9->enable_single_step(target);
1460
1461 target->debug_reason = DBG_REASON_SINGLESTEP;
1462
1463 arm7_9_restore_context(target);
1464
1465 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1466 arm7_9->branch_resume(target);
1467 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1468 {
1469 arm7_9->branch_resume_thumb(target);
1470 }
1471 else
1472 {
1473 LOG_ERROR("unhandled core state");
1474 return ERROR_FAIL;
1475 }
1476
1477 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1478 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1479 err = arm7_9_execute_sys_speed(target);
1480
1481 LOG_DEBUG("disable single-step");
1482 arm7_9->disable_single_step(target);
1483
1484 if (err != ERROR_OK)
1485 {
1486 arm7_9_set_breakpoint(target, breakpoint);
1487 target->state = TARGET_UNKNOWN;
1488 return err;
1489 }
1490
1491 arm7_9_debug_entry(target);
1492 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1493
1494 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1495 arm7_9_set_breakpoint(target, breakpoint);
1496 }
1497 }
1498
1499 /* enable any pending breakpoints and watchpoints */
1500 arm7_9_enable_breakpoints(target);
1501 arm7_9_enable_watchpoints(target);
1502
1503 arm7_9_restore_context(target);
1504
1505 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1506 {
1507 arm7_9->branch_resume(target);
1508 }
1509 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1510 {
1511 arm7_9->branch_resume_thumb(target);
1512 }
1513 else
1514 {
1515 LOG_ERROR("unhandled core state");
1516 return ERROR_FAIL;
1517 }
1518
1519 /* deassert DBGACK and INTDIS */
1520 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1521 /* INTDIS only when we really resume, not during debug execution */
1522 if (!debug_execution)
1523 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1524 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1525
1526 arm7_9_restart_core(target);
1527
1528 target->debug_reason = DBG_REASON_NOTHALTED;
1529
1530 if (!debug_execution)
1531 {
1532 /* registers are now invalid */
1533 armv4_5_invalidate_core_regs(target);
1534 target->state = TARGET_RUNNING;
1535 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1536 }
1537 else
1538 {
1539 target->state = TARGET_DEBUG_RUNNING;
1540 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1541 }
1542
1543 LOG_DEBUG("target resumed");
1544
1545 return ERROR_OK;
1546 }
1547
1548 void arm7_9_enable_eice_step(target_t *target)
1549 {
1550 armv4_5_common_t *armv4_5 = target->arch_info;
1551 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1552
1553 /* setup an inverse breakpoint on the current PC
1554 * - comparator 1 matches the current address
1555 * - rangeout from comparator 1 is connected to comparator 0 rangein
1556 * - comparator 0 matches any address, as long as rangein is low */
1557 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1558 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1559 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1560 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1561 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1562 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1563 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1564 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1565 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1566 }
1567
1568 void arm7_9_disable_eice_step(target_t *target)
1569 {
1570 armv4_5_common_t *armv4_5 = target->arch_info;
1571 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1572
1573 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1574 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1575 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1576 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1577 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1578 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1579 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1580 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1581 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1582 }
1583
1584 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1585 {
1586 armv4_5_common_t *armv4_5 = target->arch_info;
1587 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1588 breakpoint_t *breakpoint = NULL;
1589 int err;
1590
1591 if (target->state != TARGET_HALTED)
1592 {
1593 LOG_WARNING("target not halted");
1594 return ERROR_TARGET_NOT_HALTED;
1595 }
1596
1597 /* current = 1: continue on current pc, otherwise continue at <address> */
1598 if (!current)
1599 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1600
1601 /* the front-end may request us not to handle breakpoints */
1602 if (handle_breakpoints)
1603 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1604 arm7_9_unset_breakpoint(target, breakpoint);
1605
1606 target->debug_reason = DBG_REASON_SINGLESTEP;
1607
1608 arm7_9_restore_context(target);
1609
1610 arm7_9->enable_single_step(target);
1611
1612 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1613 {
1614 arm7_9->branch_resume(target);
1615 }
1616 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1617 {
1618 arm7_9->branch_resume_thumb(target);
1619 }
1620 else
1621 {
1622 LOG_ERROR("unhandled core state");
1623 return ERROR_FAIL;
1624 }
1625
1626 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1627
1628 err = arm7_9_execute_sys_speed(target);
1629 arm7_9->disable_single_step(target);
1630
1631 /* registers are now invalid */
1632 armv4_5_invalidate_core_regs(target);
1633
1634 if (err != ERROR_OK)
1635 {
1636 target->state = TARGET_UNKNOWN;
1637 } else {
1638 arm7_9_debug_entry(target);
1639 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1640 LOG_DEBUG("target stepped");
1641 }
1642
1643 if (breakpoint)
1644 arm7_9_set_breakpoint(target, breakpoint);
1645
1646 return err;
1647
1648 }
1649
1650 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1651 {
1652 u32* reg_p[16];
1653 u32 value;
1654 int retval;
1655 armv4_5_common_t *armv4_5 = target->arch_info;
1656 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1657 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1658
1659 if ((num < 0) || (num > 16))
1660 return ERROR_INVALID_ARGUMENTS;
1661
1662 if ((mode != ARMV4_5_MODE_ANY)
1663 && (mode != armv4_5->core_mode)
1664 && (reg_mode != ARMV4_5_MODE_ANY))
1665 {
1666 u32 tmp_cpsr;
1667
1668 /* change processor mode (mask T bit) */
1669 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1670 tmp_cpsr |= mode;
1671 tmp_cpsr &= ~0x20;
1672 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1673 }
1674
1675 if ((num >= 0) && (num <= 15))
1676 {
1677 /* read a normal core register */
1678 reg_p[num] = &value;
1679
1680 arm7_9->read_core_regs(target, 1 << num, reg_p);
1681 }
1682 else
1683 {
1684 /* read a program status register
1685 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1686 */
1687 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1688 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1689
1690 arm7_9->read_xpsr(target, &value, spsr);
1691 }
1692
1693 if ((retval = jtag_execute_queue()) != ERROR_OK)
1694 {
1695 return retval;
1696 }
1697
1698 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1699 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1700 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1701
1702 if ((mode != ARMV4_5_MODE_ANY)
1703 && (mode != armv4_5->core_mode)
1704 && (reg_mode != ARMV4_5_MODE_ANY)) {
1705 /* restore processor mode (mask T bit) */
1706 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1707 }
1708
1709 return ERROR_OK;
1710
1711 }
1712
1713 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1714 {
1715 u32 reg[16];
1716 armv4_5_common_t *armv4_5 = target->arch_info;
1717 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1718 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1719
1720 if ((num < 0) || (num > 16))
1721 return ERROR_INVALID_ARGUMENTS;
1722
1723 if ((mode != ARMV4_5_MODE_ANY)
1724 && (mode != armv4_5->core_mode)
1725 && (reg_mode != ARMV4_5_MODE_ANY)) {
1726 u32 tmp_cpsr;
1727
1728 /* change processor mode (mask T bit) */
1729 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1730 tmp_cpsr |= mode;
1731 tmp_cpsr &= ~0x20;
1732 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1733 }
1734
1735 if ((num >= 0) && (num <= 15))
1736 {
1737 /* write a normal core register */
1738 reg[num] = value;
1739
1740 arm7_9->write_core_regs(target, 1 << num, reg);
1741 }
1742 else
1743 {
1744 /* write a program status register
1745 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1746 */
1747 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1748 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1749
1750 /* if we're writing the CPSR, mask the T bit */
1751 if (!spsr)
1752 value &= ~0x20;
1753
1754 arm7_9->write_xpsr(target, value, spsr);
1755 }
1756
1757 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1758 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1759
1760 if ((mode != ARMV4_5_MODE_ANY)
1761 && (mode != armv4_5->core_mode)
1762 && (reg_mode != ARMV4_5_MODE_ANY)) {
1763 /* restore processor mode (mask T bit) */
1764 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1765 }
1766
1767 return jtag_execute_queue();
1768 }
1769
1770 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1771 {
1772 armv4_5_common_t *armv4_5 = target->arch_info;
1773 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1774
1775 u32 reg[16];
1776 int num_accesses = 0;
1777 int thisrun_accesses;
1778 int i;
1779 u32 cpsr;
1780 int retval;
1781 int last_reg = 0;
1782
1783 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1784
1785 if (target->state != TARGET_HALTED)
1786 {
1787 LOG_WARNING("target not halted");
1788 return ERROR_TARGET_NOT_HALTED;
1789 }
1790
1791 /* sanitize arguments */
1792 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1793 return ERROR_INVALID_ARGUMENTS;
1794
1795 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1796 return ERROR_TARGET_UNALIGNED_ACCESS;
1797
1798 /* load the base register with the address of the first word */
1799 reg[0] = address;
1800 arm7_9->write_core_regs(target, 0x1, reg);
1801
1802 switch (size)
1803 {
1804 case 4:
1805 while (num_accesses < count)
1806 {
1807 u32 reg_list;
1808 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1809 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1810
1811 if (last_reg <= thisrun_accesses)
1812 last_reg = thisrun_accesses;
1813
1814 arm7_9->load_word_regs(target, reg_list);
1815
1816 /* fast memory reads are only safe when the target is running
1817 * from a sufficiently high clock (32 kHz is usually too slow)
1818 */
1819 if (arm7_9->fast_memory_access)
1820 arm7_9_execute_fast_sys_speed(target);
1821 else
1822 arm7_9_execute_sys_speed(target);
1823
1824 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1825
1826 /* advance buffer, count number of accesses */
1827 buffer += thisrun_accesses * 4;
1828 num_accesses += thisrun_accesses;
1829 }
1830 break;
1831 case 2:
1832 while (num_accesses < count)
1833 {
1834 u32 reg_list;
1835 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1836 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1837
1838 for (i = 1; i <= thisrun_accesses; i++)
1839 {
1840 if (i > last_reg)
1841 last_reg = i;
1842 arm7_9->load_hword_reg(target, i);
1843 /* fast memory reads are only safe when the target is running
1844 * from a sufficiently high clock (32 kHz is usually too slow)
1845 */
1846 if (arm7_9->fast_memory_access)
1847 arm7_9_execute_fast_sys_speed(target);
1848 else
1849 arm7_9_execute_sys_speed(target);
1850 }
1851
1852 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1853
1854 /* advance buffer, count number of accesses */
1855 buffer += thisrun_accesses * 2;
1856 num_accesses += thisrun_accesses;
1857 }
1858 break;
1859 case 1:
1860 while (num_accesses < count)
1861 {
1862 u32 reg_list;
1863 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1864 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1865
1866 for (i = 1; i <= thisrun_accesses; i++)
1867 {
1868 if (i > last_reg)
1869 last_reg = i;
1870 arm7_9->load_byte_reg(target, i);
1871 /* fast memory reads are only safe when the target is running
1872 * from a sufficiently high clock (32 kHz is usually too slow)
1873 */
1874 if (arm7_9->fast_memory_access)
1875 arm7_9_execute_fast_sys_speed(target);
1876 else
1877 arm7_9_execute_sys_speed(target);
1878 }
1879
1880 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1881
1882 /* advance buffer, count number of accesses */
1883 buffer += thisrun_accesses * 1;
1884 num_accesses += thisrun_accesses;
1885 }
1886 break;
1887 default:
1888 LOG_ERROR("BUG: we shouldn't get here");
1889 exit(-1);
1890 break;
1891 }
1892
1893 for (i=0; i<=last_reg; i++)
1894 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1895
1896 arm7_9->read_xpsr(target, &cpsr, 0);
1897 if ((retval = jtag_execute_queue()) != ERROR_OK)
1898 {
1899 LOG_ERROR("JTAG error while reading cpsr");
1900 return ERROR_TARGET_DATA_ABORT;
1901 }
1902
1903 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1904 {
1905 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1906
1907 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1908
1909 return ERROR_TARGET_DATA_ABORT;
1910 }
1911
1912 return ERROR_OK;
1913 }
1914
1915 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1916 {
1917 armv4_5_common_t *armv4_5 = target->arch_info;
1918 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1919 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1920
1921 u32 reg[16];
1922 int num_accesses = 0;
1923 int thisrun_accesses;
1924 int i;
1925 u32 cpsr;
1926 int retval;
1927 int last_reg = 0;
1928
1929 #ifdef _DEBUG_ARM7_9_
1930 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1931 #endif
1932
1933 if (target->state != TARGET_HALTED)
1934 {
1935 LOG_WARNING("target not halted");
1936 return ERROR_TARGET_NOT_HALTED;
1937 }
1938
1939 /* sanitize arguments */
1940 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1941 return ERROR_INVALID_ARGUMENTS;
1942
1943 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1944 return ERROR_TARGET_UNALIGNED_ACCESS;
1945
1946 /* load the base register with the address of the first word */
1947 reg[0] = address;
1948 arm7_9->write_core_regs(target, 0x1, reg);
1949
1950 /* Clear DBGACK, to make sure memory fetches work as expected */
1951 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1952 embeddedice_store_reg(dbg_ctrl);
1953
1954 switch (size)
1955 {
1956 case 4:
1957 while (num_accesses < count)
1958 {
1959 u32 reg_list;
1960 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1961 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1962
1963 for (i = 1; i <= thisrun_accesses; i++)
1964 {
1965 if (i > last_reg)
1966 last_reg = i;
1967 reg[i] = target_buffer_get_u32(target, buffer);
1968 buffer += 4;
1969 }
1970
1971 arm7_9->write_core_regs(target, reg_list, reg);
1972
1973 arm7_9->store_word_regs(target, reg_list);
1974
1975 /* fast memory writes are only safe when the target is running
1976 * from a sufficiently high clock (32 kHz is usually too slow)
1977 */
1978 if (arm7_9->fast_memory_access)
1979 arm7_9_execute_fast_sys_speed(target);
1980 else
1981 arm7_9_execute_sys_speed(target);
1982
1983 num_accesses += thisrun_accesses;
1984 }
1985 break;
1986 case 2:
1987 while (num_accesses < count)
1988 {
1989 u32 reg_list;
1990 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1991 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1992
1993 for (i = 1; i <= thisrun_accesses; i++)
1994 {
1995 if (i > last_reg)
1996 last_reg = i;
1997 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1998 buffer += 2;
1999 }
2000
2001 arm7_9->write_core_regs(target, reg_list, reg);
2002
2003 for (i = 1; i <= thisrun_accesses; i++)
2004 {
2005 arm7_9->store_hword_reg(target, i);
2006
2007 /* fast memory writes are only safe when the target is running
2008 * from a sufficiently high clock (32 kHz is usually too slow)
2009 */
2010 if (arm7_9->fast_memory_access)
2011 arm7_9_execute_fast_sys_speed(target);
2012 else
2013 arm7_9_execute_sys_speed(target);
2014 }
2015
2016 num_accesses += thisrun_accesses;
2017 }
2018 break;
2019 case 1:
2020 while (num_accesses < count)
2021 {
2022 u32 reg_list;
2023 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2024 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2025
2026 for (i = 1; i <= thisrun_accesses; i++)
2027 {
2028 if (i > last_reg)
2029 last_reg = i;
2030 reg[i] = *buffer++ & 0xff;
2031 }
2032
2033 arm7_9->write_core_regs(target, reg_list, reg);
2034
2035 for (i = 1; i <= thisrun_accesses; i++)
2036 {
2037 arm7_9->store_byte_reg(target, i);
2038 /* fast memory writes are only safe when the target is running
2039 * from a sufficiently high clock (32 kHz is usually too slow)
2040 */
2041 if (arm7_9->fast_memory_access)
2042 arm7_9_execute_fast_sys_speed(target);
2043 else
2044 arm7_9_execute_sys_speed(target);
2045 }
2046
2047 num_accesses += thisrun_accesses;
2048 }
2049 break;
2050 default:
2051 LOG_ERROR("BUG: we shouldn't get here");
2052 exit(-1);
2053 break;
2054 }
2055
2056 /* Re-Set DBGACK */
2057 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2058 embeddedice_store_reg(dbg_ctrl);
2059
2060 for (i=0; i<=last_reg; i++)
2061 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2062
2063 arm7_9->read_xpsr(target, &cpsr, 0);
2064 if ((retval = jtag_execute_queue()) != ERROR_OK)
2065 {
2066 LOG_ERROR("JTAG error while reading cpsr");
2067 return ERROR_TARGET_DATA_ABORT;
2068 }
2069
2070 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2071 {
2072 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2073
2074 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2075
2076 return ERROR_TARGET_DATA_ABORT;
2077 }
2078
2079 return ERROR_OK;
2080 }
2081
2082 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2083 {
2084 armv4_5_common_t *armv4_5 = target->arch_info;
2085 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2086 enum armv4_5_state core_state = armv4_5->core_state;
2087 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2088 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2089 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2090 int i;
2091
2092 u32 dcc_code[] =
2093 {
2094 /* MRC TST BNE MRC STR B */
2095 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2096 };
2097
2098 if (!arm7_9->dcc_downloads)
2099 return target->type->write_memory(target, address, 4, count, buffer);
2100
2101 /* regrab previously allocated working_area, or allocate a new one */
2102 if (!arm7_9->dcc_working_area)
2103 {
2104 u8 dcc_code_buf[6 * 4];
2105
2106 /* make sure we have a working area */
2107 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2108 {
2109 LOG_INFO("no working area available, falling back to memory writes");
2110 return target->type->write_memory(target, address, 4, count, buffer);
2111 }
2112
2113 /* copy target instructions to target endianness */
2114 for (i = 0; i < 6; i++)
2115 {
2116 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2117 }
2118
2119 /* write DCC code to working area */
2120 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2121 }
2122
2123 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2124 armv4_5->core_cache->reg_list[0].valid = 1;
2125 armv4_5->core_cache->reg_list[0].dirty = 1;
2126 armv4_5->core_state = ARMV4_5_STATE_ARM;
2127
2128 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2129
2130 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2131 if (count>2)
2132 {
2133 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2134 core function repeated.
2135 */
2136 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2137 buffer+=4;
2138
2139 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2140 u8 reg_addr = ice_reg->addr & 0x1f;
2141 int chain_pos = ice_reg->jtag_info->chain_pos;
2142 /* we want the compiler to duplicate the code, which it does not
2143 * do automatically.
2144 */
2145 if (little)
2146 {
2147 for (i = 1; i < count - 1; i++)
2148 {
2149 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2150 buffer += 4;
2151 }
2152 } else
2153 {
2154 for (i = 1; i < count - 1; i++)
2155 {
2156 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2157 buffer += 4;
2158 }
2159 }
2160 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2161 } else
2162 {
2163 for (i = 0; i < count; i++)
2164 {
2165 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2166 buffer += 4;
2167 }
2168 }
2169
2170 target->type->halt(target);
2171
2172 for (i=0; i<100; i++)
2173 {
2174 target->type->poll(target);
2175 if (target->state == TARGET_HALTED)
2176 break;
2177 usleep(1000); /* sleep 1ms */
2178 }
2179 if (i == 100)
2180 {
2181 LOG_ERROR("bulk write timed out, target not halted");
2182 return ERROR_TARGET_TIMEOUT;
2183 }
2184
2185 /* restore target state */
2186 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2187 armv4_5->core_cache->reg_list[0].valid = 1;
2188 armv4_5->core_cache->reg_list[0].dirty = 1;
2189 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2190 armv4_5->core_cache->reg_list[1].valid = 1;
2191 armv4_5->core_cache->reg_list[1].dirty = 1;
2192 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2193 armv4_5->core_cache->reg_list[15].valid = 1;
2194 armv4_5->core_cache->reg_list[15].dirty = 1;
2195 armv4_5->core_state = core_state;
2196
2197 return ERROR_OK;
2198 }
2199
2200 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2201 {
2202 working_area_t *crc_algorithm;
2203 armv4_5_algorithm_t armv4_5_info;
2204 reg_param_t reg_params[2];
2205 int retval;
2206
2207 u32 arm7_9_crc_code[] = {
2208 0xE1A02000, /* mov r2, r0 */
2209 0xE3E00000, /* mov r0, #0xffffffff */
2210 0xE1A03001, /* mov r3, r1 */
2211 0xE3A04000, /* mov r4, #0 */
2212 0xEA00000B, /* b ncomp */
2213 /* nbyte: */
2214 0xE7D21004, /* ldrb r1, [r2, r4] */
2215 0xE59F7030, /* ldr r7, CRC32XOR */
2216 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2217 0xE3A05000, /* mov r5, #0 */
2218 /* loop: */
2219 0xE3500000, /* cmp r0, #0 */
2220 0xE1A06080, /* mov r6, r0, asl #1 */
2221 0xE2855001, /* add r5, r5, #1 */
2222 0xE1A00006, /* mov r0, r6 */
2223 0xB0260007, /* eorlt r0, r6, r7 */
2224 0xE3550008, /* cmp r5, #8 */
2225 0x1AFFFFF8, /* bne loop */
2226 0xE2844001, /* add r4, r4, #1 */
2227 /* ncomp: */
2228 0xE1540003, /* cmp r4, r3 */
2229 0x1AFFFFF1, /* bne nbyte */
2230 /* end: */
2231 0xEAFFFFFE, /* b end */
2232 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2233 };
2234
2235 int i;
2236
2237 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2238 {
2239 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2240 }
2241
2242 /* convert flash writing code into a buffer in target endianness */
2243 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2244 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2245
2246 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2247 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2248 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2249
2250 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2251 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2252
2253 buf_set_u32(reg_params[0].value, 0, 32, address);
2254 buf_set_u32(reg_params[1].value, 0, 32, count);
2255
2256 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2257 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2258 {
2259 LOG_ERROR("error executing arm7_9 crc algorithm");
2260 destroy_reg_param(&reg_params[0]);
2261 destroy_reg_param(&reg_params[1]);
2262 target_free_working_area(target, crc_algorithm);
2263 return retval;
2264 }
2265
2266 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2267
2268 destroy_reg_param(&reg_params[0]);
2269 destroy_reg_param(&reg_params[1]);
2270
2271 target_free_working_area(target, crc_algorithm);
2272
2273 return ERROR_OK;
2274 }
2275
2276 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2277 {
2278 command_t *arm7_9_cmd;
2279
2280 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2281
2282 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2283 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2284
2285 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2286
2287 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2288 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2289 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2290 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2291 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2292 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2293 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2294 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2295 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2296 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2297
2298 armv4_5_register_commands(cmd_ctx);
2299
2300 etm_register_commands(cmd_ctx);
2301
2302 return ERROR_OK;
2303 }
2304
2305 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2306 {
2307 u32 value;
2308 int spsr;
2309 int retval;
2310 target_t *target = get_current_target(cmd_ctx);
2311 armv4_5_common_t *armv4_5;
2312 arm7_9_common_t *arm7_9;
2313
2314 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2315 {
2316 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2317 return ERROR_OK;
2318 }
2319
2320 if (target->state != TARGET_HALTED)
2321 {
2322 command_print(cmd_ctx, "can't write registers while running");
2323 return ERROR_OK;
2324 }
2325
2326 if (argc < 2)
2327 {
2328 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2329 return ERROR_OK;
2330 }
2331
2332 value = strtoul(args[0], NULL, 0);
2333 spsr = strtol(args[1], NULL, 0);
2334
2335 /* if we're writing the CPSR, mask the T bit */
2336 if (!spsr)
2337 value &= ~0x20;
2338
2339 arm7_9->write_xpsr(target, value, spsr);
2340 if ((retval = jtag_execute_queue()) != ERROR_OK)
2341 {
2342 LOG_ERROR("JTAG error while writing to xpsr");
2343 return retval;
2344 }
2345
2346 return ERROR_OK;
2347 }
2348
2349 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2350 {
2351 u32 value;
2352 int rotate;
2353 int spsr;
2354 int retval;
2355 target_t *target = get_current_target(cmd_ctx);
2356 armv4_5_common_t *armv4_5;
2357 arm7_9_common_t *arm7_9;
2358
2359 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2360 {
2361 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2362 return ERROR_OK;
2363 }
2364
2365 if (target->state != TARGET_HALTED)
2366 {
2367 command_print(cmd_ctx, "can't write registers while running");
2368 return ERROR_OK;
2369 }
2370
2371 if (argc < 3)
2372 {
2373 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2374 return ERROR_OK;
2375 }
2376
2377 value = strtoul(args[0], NULL, 0);
2378 rotate = strtol(args[1], NULL, 0);
2379 spsr = strtol(args[2], NULL, 0);
2380
2381 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2382 if ((retval = jtag_execute_queue()) != ERROR_OK)
2383 {
2384 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2385 return retval;
2386 }
2387
2388 return ERROR_OK;
2389 }
2390
2391 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2392 {
2393 u32 value;
2394 u32 mode;
2395 int num;
2396 target_t *target = get_current_target(cmd_ctx);
2397 armv4_5_common_t *armv4_5;
2398 arm7_9_common_t *arm7_9;
2399
2400 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2401 {
2402 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2403 return ERROR_OK;
2404 }
2405
2406 if (target->state != TARGET_HALTED)
2407 {
2408 command_print(cmd_ctx, "can't write registers while running");
2409 return ERROR_OK;
2410 }
2411
2412 if (argc < 3)
2413 {
2414 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2415 return ERROR_OK;
2416 }
2417
2418 num = strtol(args[0], NULL, 0);
2419 mode = strtoul(args[1], NULL, 0);
2420 value = strtoul(args[2], NULL, 0);
2421
2422 arm7_9_write_core_reg(target, num, mode, value);
2423
2424 return ERROR_OK;
2425 }
2426
2427 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2428 {
2429 target_t *target = get_current_target(cmd_ctx);
2430 armv4_5_common_t *armv4_5;
2431 arm7_9_common_t *arm7_9;
2432
2433 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2434 {
2435 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2436 return ERROR_OK;
2437 }
2438
2439 if (argc == 0)
2440 {
2441 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2442 return ERROR_OK;
2443 }
2444
2445 if (strcmp("enable", args[0]) == 0)
2446 {
2447 if (arm7_9->sw_bkpts_use_wp)
2448 {
2449 arm7_9_enable_sw_bkpts(target);
2450 }
2451 else
2452 {
2453 arm7_9->sw_bkpts_enabled = 1;
2454 }
2455 }
2456 else if (strcmp("disable", args[0]) == 0)
2457 {
2458 if (arm7_9->sw_bkpts_use_wp)
2459 {
2460 arm7_9_disable_sw_bkpts(target);
2461 }
2462 else
2463 {
2464 arm7_9->sw_bkpts_enabled = 0;
2465 }
2466 }
2467 else
2468 {
2469 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2470 }
2471
2472 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2473
2474 return ERROR_OK;
2475 }
2476
2477 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2478 {
2479 target_t *target = get_current_target(cmd_ctx);
2480 armv4_5_common_t *armv4_5;
2481 arm7_9_common_t *arm7_9;
2482
2483 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2484 {
2485 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2486 return ERROR_OK;
2487 }
2488
2489 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2490 {
2491 arm7_9->force_hw_bkpts = 1;
2492 if (arm7_9->sw_bkpts_use_wp)
2493 {
2494 arm7_9_disable_sw_bkpts(target);
2495 }
2496 }
2497 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2498 {
2499 arm7_9->force_hw_bkpts = 0;
2500 }
2501 else
2502 {
2503 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2504 }
2505
2506 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2507
2508 return ERROR_OK;
2509 }
2510
2511 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2512 {
2513 target_t *target = get_current_target(cmd_ctx);
2514 armv4_5_common_t *armv4_5;
2515 arm7_9_common_t *arm7_9;
2516
2517 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2518 {
2519 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2520 return ERROR_OK;
2521 }
2522
2523 if (argc > 0)
2524 {
2525 if (strcmp("enable", args[0]) == 0)
2526 {
2527 arm7_9->use_dbgrq = 1;
2528 }
2529 else if (strcmp("disable", args[0]) == 0)
2530 {
2531 arm7_9->use_dbgrq = 0;
2532 }
2533 else
2534 {
2535 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2536 }
2537 }
2538
2539 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2540
2541 return ERROR_OK;
2542 }
2543
2544 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2545 {
2546 target_t *target = get_current_target(cmd_ctx);
2547 armv4_5_common_t *armv4_5;
2548 arm7_9_common_t *arm7_9;
2549
2550 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2551 {
2552 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2553 return ERROR_OK;
2554 }
2555
2556 if (argc > 0)
2557 {
2558 if (strcmp("enable", args[0]) == 0)
2559 {
2560 arm7_9->fast_memory_access = 1;
2561 }
2562 else if (strcmp("disable", args[0]) == 0)
2563 {
2564 arm7_9->fast_memory_access = 0;
2565 }
2566 else
2567 {
2568 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2569 }
2570 }
2571
2572 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2573
2574 return ERROR_OK;
2575 }
2576
2577 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2578 {
2579 target_t *target = get_current_target(cmd_ctx);
2580 armv4_5_common_t *armv4_5;
2581 arm7_9_common_t *arm7_9;
2582
2583 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2584 {
2585 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2586 return ERROR_OK;
2587 }
2588
2589 if (argc > 0)
2590 {
2591 if (strcmp("enable", args[0]) == 0)
2592 {
2593 arm7_9->dcc_downloads = 1;
2594 }
2595 else if (strcmp("disable", args[0]) == 0)
2596 {
2597 arm7_9->dcc_downloads = 0;
2598 }
2599 else
2600 {
2601 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2602 }
2603 }
2604
2605 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2606
2607 return ERROR_OK;
2608 }
2609
2610 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2611 {
2612 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2613
2614 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2615
2616 arm_jtag_setup_connection(&arm7_9->jtag_info);
2617 arm7_9->wp_available = 2;
2618 arm7_9->wp0_used = 0;
2619 arm7_9->wp1_used = 0;
2620 arm7_9->force_hw_bkpts = 0;
2621 arm7_9->use_dbgrq = 0;
2622
2623 arm7_9->etm_ctx = NULL;
2624 arm7_9->has_single_step = 0;
2625 arm7_9->has_monitor_mode = 0;
2626 arm7_9->has_vector_catch = 0;
2627
2628 arm7_9->reinit_embeddedice = 0;
2629
2630 arm7_9->debug_entry_from_reset = 0;
2631
2632 arm7_9->dcc_working_area = NULL;
2633
2634 arm7_9->fast_memory_access = 0;
2635 arm7_9->dcc_downloads = 0;
2636
2637 jtag_register_event_callback(arm7_9_jtag_callback, target);
2638
2639 armv4_5->arch_info = arm7_9;
2640 armv4_5->read_core_reg = arm7_9_read_core_reg;
2641 armv4_5->write_core_reg = arm7_9_write_core_reg;
2642 armv4_5->full_context = arm7_9_full_context;
2643
2644 armv4_5_init_arch_info(target, armv4_5);
2645
2646 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2647
2648 return ERROR_OK;
2649 }
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