1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t
*target
);
45 int arm7_9_enable_sw_bkpts(struct target_s
*target
);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
57 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 int handle_arm7_9_etb_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
60 int arm7_9_reinit_embeddedice(target_t
*target
)
62 armv4_5_common_t
*armv4_5
= target
->arch_info
;
63 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
65 breakpoint_t
*breakpoint
= target
->breakpoints
;
67 arm7_9
->wp_available
= 2;
71 /* mark all hardware breakpoints as unset */
74 if (breakpoint
->type
== BKPT_HARD
)
78 breakpoint
= breakpoint
->next
;
81 if (arm7_9
->sw_bkpts_enabled
&& arm7_9
->sw_bkpts_use_wp
)
83 arm7_9
->sw_bkpts_enabled
= 0;
84 arm7_9_enable_sw_bkpts(target
);
87 arm7_9
->reinit_embeddedice
= 0;
92 int arm7_9_jtag_callback(enum jtag_event event
, void *priv
)
94 target_t
*target
= priv
;
95 armv4_5_common_t
*armv4_5
= target
->arch_info
;
96 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
102 if (event
== JTAG_TRST_ASSERTED
)
104 arm7_9
->reinit_embeddedice
= 1;
110 int arm7_9_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
)
112 armv4_5_common_t
*armv4_5
= target
->arch_info
;
113 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
115 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
120 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
125 *armv4_5_p
= armv4_5
;
131 int arm7_9_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
133 armv4_5_common_t
*armv4_5
= target
->arch_info
;
134 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
136 if (target
->state
!= TARGET_HALTED
)
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED
;
142 if (arm7_9
->force_hw_bkpts
)
143 breakpoint
->type
= BKPT_HARD
;
147 WARNING("breakpoint already set");
151 if (breakpoint
->type
== BKPT_HARD
)
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
155 if (!arm7_9
->wp0_used
)
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
161 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
163 jtag_execute_queue();
164 arm7_9
->wp0_used
= 1;
167 else if (!arm7_9
->wp1_used
)
169 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
170 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
171 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
172 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
173 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
175 jtag_execute_queue();
176 arm7_9
->wp1_used
= 1;
181 ERROR("BUG: no hardware comparator available");
185 else if (breakpoint
->type
== BKPT_SOFT
)
187 if (breakpoint
->length
== 4)
189 /* keep the original instruction in target endianness */
190 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
191 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
192 target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
);
196 /* keep the original instruction in target endianness */
197 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
198 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
199 target_write_u32(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
);
208 int arm7_9_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
210 armv4_5_common_t
*armv4_5
= target
->arch_info
;
211 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
213 if (target
->state
!= TARGET_HALTED
)
215 WARNING("target not halted");
216 return ERROR_TARGET_NOT_HALTED
;
219 if (!breakpoint
->set
)
221 WARNING("breakpoint not set");
225 if (breakpoint
->type
== BKPT_HARD
)
227 if (breakpoint
->set
== 1)
229 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
230 jtag_execute_queue();
231 arm7_9
->wp0_used
= 0;
233 else if (breakpoint
->set
== 2)
235 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
236 jtag_execute_queue();
237 arm7_9
->wp1_used
= 0;
243 /* restore original instruction (kept in target endianness) */
244 if (breakpoint
->length
== 4)
246 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
250 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
258 int arm7_9_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
260 armv4_5_common_t
*armv4_5
= target
->arch_info
;
261 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
263 if (target
->state
!= TARGET_HALTED
)
265 WARNING("target not halted");
266 return ERROR_TARGET_NOT_HALTED
;
269 if (arm7_9
->force_hw_bkpts
)
271 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
272 breakpoint
->type
= BKPT_HARD
;
275 if ((breakpoint
->type
== BKPT_SOFT
) && (arm7_9
->sw_bkpts_enabled
== 0))
277 INFO("sw breakpoint requested, but software breakpoints not enabled");
278 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
281 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
283 INFO("no watchpoint unit available for hardware breakpoint");
284 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
287 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
289 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
290 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
293 if (breakpoint
->type
== BKPT_HARD
)
294 arm7_9
->wp_available
--;
299 int arm7_9_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
301 armv4_5_common_t
*armv4_5
= target
->arch_info
;
302 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
304 if (target
->state
!= TARGET_HALTED
)
306 WARNING("target not halted");
307 return ERROR_TARGET_NOT_HALTED
;
312 arm7_9_unset_breakpoint(target
, breakpoint
);
315 if (breakpoint
->type
== BKPT_HARD
)
316 arm7_9
->wp_available
++;
321 int arm7_9_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
323 armv4_5_common_t
*armv4_5
= target
->arch_info
;
324 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
328 mask
= watchpoint
->length
- 1;
330 if (target
->state
!= TARGET_HALTED
)
332 WARNING("target not halted");
333 return ERROR_TARGET_NOT_HALTED
;
336 if (watchpoint
->rw
== WPT_ACCESS
)
341 if (!arm7_9
->wp0_used
)
343 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
344 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
345 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
346 if( watchpoint
->mask
!= 0xffffffffu
)
347 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
348 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
349 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
351 jtag_execute_queue();
353 arm7_9
->wp0_used
= 2;
355 else if (!arm7_9
->wp1_used
)
357 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
358 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
359 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
360 if( watchpoint
->mask
!= 0xffffffffu
)
361 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
362 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
363 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
365 jtag_execute_queue();
367 arm7_9
->wp1_used
= 2;
371 ERROR("BUG: no hardware comparator available");
378 int arm7_9_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
380 armv4_5_common_t
*armv4_5
= target
->arch_info
;
381 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
383 if (target
->state
!= TARGET_HALTED
)
385 WARNING("target not halted");
386 return ERROR_TARGET_NOT_HALTED
;
389 if (!watchpoint
->set
)
391 WARNING("breakpoint not set");
395 if (watchpoint
->set
== 1)
397 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
398 jtag_execute_queue();
399 arm7_9
->wp0_used
= 0;
401 else if (watchpoint
->set
== 2)
403 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
404 jtag_execute_queue();
405 arm7_9
->wp1_used
= 0;
412 int arm7_9_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
414 armv4_5_common_t
*armv4_5
= target
->arch_info
;
415 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
417 if (target
->state
!= TARGET_HALTED
)
419 WARNING("target not halted");
420 return ERROR_TARGET_NOT_HALTED
;
423 if (arm7_9
->wp_available
< 1)
425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
428 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
430 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
433 arm7_9
->wp_available
--;
438 int arm7_9_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
440 armv4_5_common_t
*armv4_5
= target
->arch_info
;
441 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
443 if (target
->state
!= TARGET_HALTED
)
445 WARNING("target not halted");
446 return ERROR_TARGET_NOT_HALTED
;
451 arm7_9_unset_watchpoint(target
, watchpoint
);
454 arm7_9
->wp_available
++;
459 int arm7_9_enable_sw_bkpts(struct target_s
*target
)
461 armv4_5_common_t
*armv4_5
= target
->arch_info
;
462 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
465 if (arm7_9
->sw_bkpts_enabled
)
468 if (arm7_9
->wp_available
< 1)
470 WARNING("can't enable sw breakpoints with no watchpoint unit available");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
473 arm7_9
->wp_available
--;
475 if (!arm7_9
->wp0_used
)
477 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
478 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
479 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
480 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
481 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
482 arm7_9
->sw_bkpts_enabled
= 1;
483 arm7_9
->wp0_used
= 3;
485 else if (!arm7_9
->wp1_used
)
487 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
488 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
489 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
490 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
491 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
492 arm7_9
->sw_bkpts_enabled
= 2;
493 arm7_9
->wp1_used
= 3;
497 ERROR("BUG: both watchpoints used, but wp_available >= 1");
501 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
503 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
510 int arm7_9_disable_sw_bkpts(struct target_s
*target
)
512 armv4_5_common_t
*armv4_5
= target
->arch_info
;
513 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
515 if (!arm7_9
->sw_bkpts_enabled
)
518 if (arm7_9
->sw_bkpts_enabled
== 1)
520 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
521 arm7_9
->sw_bkpts_enabled
= 0;
522 arm7_9
->wp0_used
= 0;
523 arm7_9
->wp_available
++;
525 else if (arm7_9
->sw_bkpts_enabled
== 2)
527 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
528 arm7_9
->sw_bkpts_enabled
= 0;
529 arm7_9
->wp1_used
= 0;
530 arm7_9
->wp_available
++;
536 int arm7_9_execute_sys_speed(struct target_s
*target
)
541 armv4_5_common_t
*armv4_5
= target
->arch_info
;
542 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
543 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
544 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
546 /* set RESTART instruction */
547 jtag_add_end_state(TAP_RTI
);
548 arm_jtag_set_instr(jtag_info
, 0x4);
550 for (timeout
=0; timeout
<50; timeout
++)
552 /* read debug status register */
553 embeddedice_read_reg(dbg_stat
);
554 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
556 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
557 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
563 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
564 return ERROR_TARGET_TIMEOUT
;
570 int arm7_9_execute_fast_sys_speed(struct target_s
*target
)
572 u8 check_value
[4], check_mask
[4];
574 armv4_5_common_t
*armv4_5
= target
->arch_info
;
575 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
576 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
577 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
579 /* set RESTART instruction */
580 jtag_add_end_state(TAP_RTI
);
581 arm_jtag_set_instr(jtag_info
, 0x4);
583 /* check for DBGACK and SYSCOMP set (others don't care) */
584 buf_set_u32(check_value
, 0, 32, 0x9);
585 buf_set_u32(check_mask
, 0, 32, 0x9);
587 /* read debug status register */
588 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_value
);
593 enum target_state
arm7_9_poll(target_t
*target
)
596 armv4_5_common_t
*armv4_5
= target
->arch_info
;
597 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
598 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
600 if (arm7_9
->reinit_embeddedice
)
602 arm7_9_reinit_embeddedice(target
);
605 /* read debug status register */
606 embeddedice_read_reg(dbg_stat
);
607 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
611 case ERROR_JTAG_QUEUE_FAILED
:
612 ERROR("JTAG queue failed while reading EmbeddedICE status register");
620 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
622 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat
->value
, 0, 32));
623 if ((target
->state
== TARGET_UNKNOWN
))
625 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
626 target
->state
= TARGET_RUNNING
;
628 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
630 target
->state
= TARGET_HALTED
;
631 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
634 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
636 if (target
->state
== TARGET_DEBUG_RUNNING
)
638 target
->state
= TARGET_HALTED
;
639 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
642 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
647 if (target
->state
!= TARGET_DEBUG_RUNNING
)
648 target
->state
= TARGET_RUNNING
;
651 return target
->state
;
654 int arm7_9_assert_reset(target_t
*target
)
658 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
660 if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_UNKNOWN
)
662 /* if the target wasn't running, there might be working areas allocated */
663 target_free_all_working_areas(target
);
665 /* assert SRST and TRST */
666 /* system would get ouf sync if we didn't reset test-logic, too */
667 if ((retval
= jtag_add_reset(1, 1)) != ERROR_OK
)
669 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
671 WARNING("can't assert srst");
676 ERROR("unknown error");
680 jtag_add_sleep(5000);
681 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
683 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
685 WARNING("srst resets test logic, too");
686 retval
= jtag_add_reset(1, 1);
692 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
694 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
696 WARNING("srst resets test logic, too");
697 retval
= jtag_add_reset(1, 1);
700 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
702 WARNING("can't assert srst");
705 else if (retval
!= ERROR_OK
)
707 ERROR("unknown error");
713 target
->state
= TARGET_RESET
;
714 jtag_add_sleep(50000);
716 armv4_5_invalidate_core_regs(target
);
722 int arm7_9_deassert_reset(target_t
*target
)
724 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
726 /* deassert reset lines */
727 jtag_add_reset(0, 0);
733 int arm7_9_clear_halt(target_t
*target
)
735 armv4_5_common_t
*armv4_5
= target
->arch_info
;
736 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
737 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
739 if (arm7_9
->use_dbgrq
)
741 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
743 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
744 embeddedice_store_reg(dbg_ctrl
);
748 /* restore registers if watchpoint unit 0 was in use
750 if (arm7_9
->wp0_used
)
752 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
753 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
754 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
756 /* control value always has to be restored, as it was either disabled,
757 * or enabled with possibly different bits
759 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
765 int arm7_9_soft_reset_halt(struct target_s
*target
)
767 armv4_5_common_t
*armv4_5
= target
->arch_info
;
768 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
769 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
770 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
773 if (target
->state
== TARGET_RUNNING
)
775 target
->type
->halt(target
);
778 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_CONTROL_DBGACK
, 1) == 0)
780 embeddedice_read_reg(dbg_stat
);
781 jtag_execute_queue();
783 target
->state
= TARGET_HALTED
;
785 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
786 * ensure that DBGRQ is cleared
788 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
789 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
790 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
791 embeddedice_store_reg(dbg_ctrl
);
793 arm7_9_clear_halt(target
);
795 /* if the target is in Thumb state, change to ARM state */
796 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
798 u32 r0_thumb
, pc_thumb
;
799 DEBUG("target entered debug from Thumb state, changing to ARM");
800 /* Entered debug from Thumb mode */
801 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
802 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
805 /* all register content is now invalid */
806 armv4_5_invalidate_core_regs(target
);
808 /* SVC, ARM state, IRQ and FIQ disabled */
809 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
810 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
811 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
813 /* start fetching from 0x0 */
814 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
815 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
816 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
818 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
819 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
821 /* reset registers */
822 for (i
= 0; i
<= 14; i
++)
824 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
825 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
826 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
829 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
834 int arm7_9_halt(target_t
*target
)
836 armv4_5_common_t
*armv4_5
= target
->arch_info
;
837 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
838 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
840 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
842 if (target
->state
== TARGET_HALTED
)
844 WARNING("target was already halted");
845 return ERROR_TARGET_ALREADY_HALTED
;
848 if (target
->state
== TARGET_UNKNOWN
)
850 WARNING("target was in unknown state when halt was requested");
853 if ((target
->state
== TARGET_RESET
) && (jtag_reset_config
& RESET_SRST_PULLS_TRST
) && (jtag_srst
))
855 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
856 return ERROR_TARGET_FAILURE
;
859 if (arm7_9
->use_dbgrq
)
861 /* program EmbeddedICE Debug Control Register to assert DBGRQ
863 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
864 embeddedice_store_reg(dbg_ctrl
);
868 /* program watchpoint unit to match on any address
870 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
871 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
872 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
873 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
876 target
->debug_reason
= DBG_REASON_DBGRQ
;
881 int arm7_9_debug_entry(target_t
*target
)
886 u32 r0_thumb
, pc_thumb
;
889 /* get pointers to arch-specific information */
890 armv4_5_common_t
*armv4_5
= target
->arch_info
;
891 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
892 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
893 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
895 #ifdef _DEBUG_ARM7_9_
899 if (arm7_9
->pre_debug_entry
)
900 arm7_9
->pre_debug_entry(target
);
902 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
903 * ensure that DBGRQ is cleared
905 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
906 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
907 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
908 embeddedice_store_reg(dbg_ctrl
);
910 arm7_9_clear_halt(target
);
912 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
916 case ERROR_JTAG_QUEUE_FAILED
:
917 ERROR("JTAG queue failed while writing EmbeddedICE control register");
925 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
929 if (target
->state
!= TARGET_HALTED
)
931 WARNING("target not halted");
932 return ERROR_TARGET_NOT_HALTED
;
935 /* if the target is in Thumb state, change to ARM state */
936 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
938 DEBUG("target entered debug from Thumb state");
939 /* Entered debug from Thumb mode */
940 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
941 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
942 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb
, pc_thumb
);
946 DEBUG("target entered debug from ARM state");
947 /* Entered debug from ARM mode */
948 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
951 for (i
= 0; i
< 16; i
++)
952 context_p
[i
] = &context
[i
];
953 /* save core registers (r0 - r15 of current core mode) */
954 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
956 arm7_9
->read_xpsr(target
, &cpsr
, 0);
958 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
961 /* if the core has been executing in Thumb state, set the T bit */
962 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
965 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
966 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
967 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
969 armv4_5
->core_mode
= cpsr
& 0x1f;
971 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
973 target
->state
= TARGET_UNKNOWN
;
974 ERROR("cpsr contains invalid mode value - communication failure");
975 return ERROR_TARGET_FAILURE
;
978 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
980 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
982 DEBUG("thumb state, applying fixups");
983 context
[0] = r0_thumb
;
984 context
[15] = pc_thumb
;
985 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
987 /* adjust value stored by STM */
988 context
[15] -= 3 * 4;
991 if ((target
->debug_reason
== DBG_REASON_BREAKPOINT
)
992 || (target
->debug_reason
== DBG_REASON_SINGLESTEP
)
993 || (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
994 || (target
->debug_reason
== DBG_REASON_WPTANDBKPT
)
995 || ((target
->debug_reason
== DBG_REASON_DBGRQ
) && (arm7_9
->use_dbgrq
== 0)))
996 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
997 else if (target
->debug_reason
== DBG_REASON_DBGRQ
)
998 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1001 ERROR("unknown debug reason: %i", target
->debug_reason
);
1005 for (i
=0; i
<=15; i
++)
1007 DEBUG("r%i: 0x%8.8x", i
, context
[i
]);
1008 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1009 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1010 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1013 DEBUG("entered debug state at PC 0x%x", context
[15]);
1015 /* exceptions other than USR & SYS have a saved program status register */
1016 if ((armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_USR
) && (armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_SYS
))
1019 arm7_9
->read_xpsr(target
, &spsr
, 1);
1020 jtag_execute_queue();
1021 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1022 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1023 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1026 /* r0 and r15 (pc) have to be restored later */
1027 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
1028 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= 1;
1030 if ((retval
= jtag
->execute_queue()) != ERROR_OK
)
1033 if (arm7_9
->post_debug_entry
)
1034 arm7_9
->post_debug_entry(target
);
1039 int arm7_9_full_context(target_t
*target
)
1043 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1044 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1048 if (target
->state
!= TARGET_HALTED
)
1050 WARNING("target not halted");
1051 return ERROR_TARGET_NOT_HALTED
;
1054 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1055 * SYS shares registers with User, so we don't touch SYS
1057 for(i
= 0; i
< 6; i
++)
1064 /* check if there are invalid registers in the current mode
1066 for (j
= 0; j
<= 16; j
++)
1068 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1076 /* change processor mode (and mask T bit) */
1077 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1078 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1080 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1082 for (j
= 0; j
< 15; j
++)
1084 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1086 reg_p
[j
] = (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1088 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1089 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1093 /* if only the PSR is invalid, mask is all zeroes */
1095 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1097 /* check if the PSR has to be read */
1098 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1100 arm7_9
->read_xpsr(target
, (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1101 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1102 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1107 /* restore processor mode (mask T bit) */
1108 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1110 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1112 ERROR("JTAG failure");
1118 int arm7_9_restore_context(target_t
*target
)
1120 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1121 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1123 armv4_5_core_reg_t
*reg_arch_info
;
1124 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1131 if (target
->state
!= TARGET_HALTED
)
1133 WARNING("target not halted");
1134 return ERROR_TARGET_NOT_HALTED
;
1137 if (arm7_9
->pre_restore_context
)
1138 arm7_9
->pre_restore_context(target
);
1140 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1141 * SYS shares registers with User, so we don't touch SYS
1143 for (i
= 0; i
< 6; i
++)
1145 DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1148 /* check if there are dirty registers in the current mode
1150 for (j
= 0; j
<= 16; j
++)
1152 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1153 reg_arch_info
= reg
->arch_info
;
1154 if (reg
->dirty
== 1)
1156 if (reg
->valid
== 1)
1159 DEBUG("examining dirty reg: %s", reg
->name
);
1160 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1161 && (reg_arch_info
->mode
!= current_mode
)
1162 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1163 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1166 DEBUG("require mode change");
1171 ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1187 /* change processor mode (mask T bit) */
1188 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1189 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1191 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1192 current_mode
= armv4_5_number_to_mode(i
);
1195 for (j
= 0; j
<= 14; j
++)
1197 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1198 reg_arch_info
= reg
->arch_info
;
1201 if (reg
->dirty
== 1)
1203 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1208 DEBUG("writing register %i of mode %s with value 0x%8.8x", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1214 arm7_9
->write_core_regs(target
, mask
, regs
);
1217 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1218 reg_arch_info
= reg
->arch_info
;
1219 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1221 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i
, buf_get_u32(reg
->value
, 0, 32));
1222 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1227 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1229 /* restore processor mode (mask T bit) */
1232 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1233 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1235 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr
);
1236 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1238 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1240 /* CPSR has been changed, full restore necessary (mask T bit) */
1241 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1242 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1243 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1244 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1248 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1249 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1250 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1252 if (arm7_9
->post_restore_context
)
1253 arm7_9
->post_restore_context(target
);
1258 int arm7_9_restart_core(struct target_s
*target
)
1260 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1261 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1262 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
1264 /* set RESTART instruction */
1265 jtag_add_end_state(TAP_RTI
);
1266 arm_jtag_set_instr(jtag_info
, 0x4);
1268 jtag_add_runtest(1, TAP_RTI
);
1269 if ((jtag_execute_queue()) != ERROR_OK
)
1277 void arm7_9_enable_watchpoints(struct target_s
*target
)
1279 watchpoint_t
*watchpoint
= target
->watchpoints
;
1283 if (watchpoint
->set
== 0)
1284 arm7_9_set_watchpoint(target
, watchpoint
);
1285 watchpoint
= watchpoint
->next
;
1289 void arm7_9_enable_breakpoints(struct target_s
*target
)
1291 breakpoint_t
*breakpoint
= target
->breakpoints
;
1293 /* set any pending breakpoints */
1296 if (breakpoint
->set
== 0)
1297 arm7_9_set_breakpoint(target
, breakpoint
);
1298 breakpoint
= breakpoint
->next
;
1302 void arm7_9_disable_bkpts_and_wpts(struct target_s
*target
)
1304 breakpoint_t
*breakpoint
= target
->breakpoints
;
1305 watchpoint_t
*watchpoint
= target
->watchpoints
;
1307 /* set any pending breakpoints */
1310 if (breakpoint
->set
!= 0)
1311 arm7_9_unset_breakpoint(target
, breakpoint
);
1312 breakpoint
= breakpoint
->next
;
1317 if (watchpoint
->set
!= 0)
1318 arm7_9_unset_watchpoint(target
, watchpoint
);
1319 watchpoint
= watchpoint
->next
;
1323 int arm7_9_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1325 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1326 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1327 breakpoint_t
*breakpoint
= target
->breakpoints
;
1328 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1332 if (target
->state
!= TARGET_HALTED
)
1334 WARNING("target not halted");
1335 return ERROR_TARGET_NOT_HALTED
;
1338 if (!debug_execution
)
1340 target_free_all_working_areas(target
);
1343 /* current = 1: continue on current pc, otherwise continue at <address> */
1345 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1347 /* the front-end may request us not to handle breakpoints */
1348 if (handle_breakpoints
)
1350 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1352 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1353 arm7_9_unset_breakpoint(target
, breakpoint
);
1355 DEBUG("enable single-step");
1356 arm7_9
->enable_single_step(target
);
1358 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1360 arm7_9_restore_context(target
);
1362 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1363 arm7_9
->branch_resume(target
);
1364 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1366 arm7_9
->branch_resume_thumb(target
);
1370 ERROR("unhandled core state");
1374 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1375 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1376 arm7_9_execute_sys_speed(target
);
1378 DEBUG("disable single-step");
1379 arm7_9
->disable_single_step(target
);
1381 arm7_9_debug_entry(target
);
1382 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1384 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1385 arm7_9_set_breakpoint(target
, breakpoint
);
1389 /* enable any pending breakpoints and watchpoints */
1390 arm7_9_enable_breakpoints(target
);
1391 arm7_9_enable_watchpoints(target
);
1393 arm7_9_restore_context(target
);
1395 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1397 arm7_9
->branch_resume(target
);
1399 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1401 arm7_9
->branch_resume_thumb(target
);
1405 ERROR("unhandled core state");
1409 /* deassert DBGACK and INTDIS */
1410 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1411 /* INTDIS only when we really resume, not during debug execution */
1412 if (!debug_execution
)
1413 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1414 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1416 arm7_9_restart_core(target
);
1418 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1420 if (!debug_execution
)
1422 /* registers are now invalid */
1423 armv4_5_invalidate_core_regs(target
);
1424 target
->state
= TARGET_RUNNING
;
1425 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1429 target
->state
= TARGET_DEBUG_RUNNING
;
1430 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1433 DEBUG("target resumed");
1438 void arm7_9_enable_eice_step(target_t
*target
)
1440 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1441 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1443 /* setup an inverse breakpoint on the current PC
1444 * - comparator 1 matches the current address
1445 * - rangeout from comparator 1 is connected to comparator 0 rangein
1446 * - comparator 0 matches any address, as long as rangein is low */
1447 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1448 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1449 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1450 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0x77);
1451 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1452 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1453 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1454 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1455 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xf7);
1458 void arm7_9_disable_eice_step(target_t
*target
)
1460 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1461 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1463 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1464 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1465 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1466 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1467 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1468 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1469 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1470 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1471 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1474 int arm7_9_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1476 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1477 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1478 breakpoint_t
*breakpoint
= NULL
;
1480 if (target
->state
!= TARGET_HALTED
)
1482 WARNING("target not halted");
1483 return ERROR_TARGET_NOT_HALTED
;
1486 /* current = 1: continue on current pc, otherwise continue at <address> */
1488 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1490 /* the front-end may request us not to handle breakpoints */
1491 if (handle_breakpoints
)
1492 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1493 arm7_9_unset_breakpoint(target
, breakpoint
);
1495 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1497 arm7_9_restore_context(target
);
1499 arm7_9
->enable_single_step(target
);
1501 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1503 arm7_9
->branch_resume(target
);
1505 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1507 arm7_9
->branch_resume_thumb(target
);
1511 ERROR("unhandled core state");
1515 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1517 arm7_9_execute_sys_speed(target
);
1518 arm7_9
->disable_single_step(target
);
1520 /* registers are now invalid */
1521 armv4_5_invalidate_core_regs(target
);
1523 arm7_9_debug_entry(target
);
1525 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1528 arm7_9_set_breakpoint(target
, breakpoint
);
1530 DEBUG("target stepped");
1536 int arm7_9_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1541 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1542 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1543 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1545 if ((num
< 0) || (num
> 16))
1546 return ERROR_INVALID_ARGUMENTS
;
1548 if ((mode
!= ARMV4_5_MODE_ANY
)
1549 && (mode
!= armv4_5
->core_mode
)
1550 && (reg_mode
!= ARMV4_5_MODE_ANY
))
1554 /* change processor mode (mask T bit) */
1555 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1558 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1561 if ((num
>= 0) && (num
<= 15))
1563 /* read a normal core register */
1564 reg_p
[num
] = &value
;
1566 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
1570 /* read a program status register
1571 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1573 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1574 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1576 arm7_9
->read_xpsr(target
, &value
, spsr
);
1579 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1581 ERROR("JTAG failure");
1585 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1586 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1587 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
1589 if ((mode
!= ARMV4_5_MODE_ANY
)
1590 && (mode
!= armv4_5
->core_mode
)
1591 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1592 /* restore processor mode (mask T bit) */
1593 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1600 int arm7_9_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1604 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1605 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1606 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1608 if ((num
< 0) || (num
> 16))
1609 return ERROR_INVALID_ARGUMENTS
;
1611 if ((mode
!= ARMV4_5_MODE_ANY
)
1612 && (mode
!= armv4_5
->core_mode
)
1613 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1616 /* change processor mode (mask T bit) */
1617 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1620 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1623 if ((num
>= 0) && (num
<= 15))
1625 /* write a normal core register */
1628 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
1632 /* write a program status register
1633 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1635 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1636 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1638 /* if we're writing the CPSR, mask the T bit */
1642 arm7_9
->write_xpsr(target
, value
, spsr
);
1645 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1646 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1648 if ((mode
!= ARMV4_5_MODE_ANY
)
1649 && (mode
!= armv4_5
->core_mode
)
1650 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1651 /* restore processor mode (mask T bit) */
1652 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1655 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1657 ERROR("JTAG failure");
1665 int arm7_9_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1667 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1668 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1671 int num_accesses
= 0;
1672 int thisrun_accesses
;
1678 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1680 if (target
->state
!= TARGET_HALTED
)
1682 WARNING("target not halted");
1683 return ERROR_TARGET_NOT_HALTED
;
1686 /* sanitize arguments */
1687 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1688 return ERROR_INVALID_ARGUMENTS
;
1690 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1691 return ERROR_TARGET_UNALIGNED_ACCESS
;
1693 /* load the base register with the address of the first word */
1695 arm7_9
->write_core_regs(target
, 0x1, reg
);
1700 while (num_accesses
< count
)
1703 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1704 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1706 if (last_reg
<= thisrun_accesses
)
1707 last_reg
= thisrun_accesses
;
1709 arm7_9
->load_word_regs(target
, reg_list
);
1711 /* fast memory reads are only safe when the target is running
1712 * from a sufficiently high clock (32 kHz is usually too slow)
1714 if (arm7_9
->fast_memory_access
)
1715 arm7_9_execute_fast_sys_speed(target
);
1717 arm7_9_execute_sys_speed(target
);
1719 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
1721 /* advance buffer, count number of accesses */
1722 buffer
+= thisrun_accesses
* 4;
1723 num_accesses
+= thisrun_accesses
;
1727 while (num_accesses
< count
)
1730 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1731 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1733 for (i
= 1; i
<= thisrun_accesses
; i
++)
1737 arm7_9
->load_hword_reg(target
, i
);
1738 /* fast memory reads are only safe when the target is running
1739 * from a sufficiently high clock (32 kHz is usually too slow)
1741 if (arm7_9
->fast_memory_access
)
1742 arm7_9_execute_fast_sys_speed(target
);
1744 arm7_9_execute_sys_speed(target
);
1747 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
1749 /* advance buffer, count number of accesses */
1750 buffer
+= thisrun_accesses
* 2;
1751 num_accesses
+= thisrun_accesses
;
1755 while (num_accesses
< count
)
1758 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1759 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1761 for (i
= 1; i
<= thisrun_accesses
; i
++)
1765 arm7_9
->load_byte_reg(target
, i
);
1766 /* fast memory reads are only safe when the target is running
1767 * from a sufficiently high clock (32 kHz is usually too slow)
1769 if (arm7_9
->fast_memory_access
)
1770 arm7_9_execute_fast_sys_speed(target
);
1772 arm7_9_execute_sys_speed(target
);
1775 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
1777 /* advance buffer, count number of accesses */
1778 buffer
+= thisrun_accesses
* 1;
1779 num_accesses
+= thisrun_accesses
;
1783 ERROR("BUG: we shouldn't get here");
1788 for (i
=0; i
<=last_reg
; i
++)
1789 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1791 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1792 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1794 ERROR("JTAG error while reading cpsr");
1798 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1800 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1802 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1804 return ERROR_TARGET_DATA_ABORT
;
1810 int arm7_9_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1812 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1813 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1814 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1817 int num_accesses
= 0;
1818 int thisrun_accesses
;
1824 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1826 if (target
->state
!= TARGET_HALTED
)
1828 WARNING("target not halted");
1829 return ERROR_TARGET_NOT_HALTED
;
1832 /* sanitize arguments */
1833 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1834 return ERROR_INVALID_ARGUMENTS
;
1836 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1837 return ERROR_TARGET_UNALIGNED_ACCESS
;
1839 /* load the base register with the address of the first word */
1841 arm7_9
->write_core_regs(target
, 0x1, reg
);
1843 /* Clear DBGACK, to make sure memory fetches work as expected */
1844 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1845 embeddedice_store_reg(dbg_ctrl
);
1850 while (num_accesses
< count
)
1853 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1854 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1856 for (i
= 1; i
<= thisrun_accesses
; i
++)
1860 reg
[i
] = target_buffer_get_u32(target
, buffer
);
1864 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1866 arm7_9
->store_word_regs(target
, reg_list
);
1868 /* fast memory writes are only safe when the target is running
1869 * from a sufficiently high clock (32 kHz is usually too slow)
1871 if (arm7_9
->fast_memory_access
)
1872 arm7_9_execute_fast_sys_speed(target
);
1874 arm7_9_execute_sys_speed(target
);
1876 num_accesses
+= thisrun_accesses
;
1880 while (num_accesses
< count
)
1883 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1884 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1886 for (i
= 1; i
<= thisrun_accesses
; i
++)
1890 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
1894 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1896 for (i
= 1; i
<= thisrun_accesses
; i
++)
1898 arm7_9
->store_hword_reg(target
, i
);
1900 /* fast memory writes are only safe when the target is running
1901 * from a sufficiently high clock (32 kHz is usually too slow)
1903 if (arm7_9
->fast_memory_access
)
1904 arm7_9_execute_fast_sys_speed(target
);
1906 arm7_9_execute_sys_speed(target
);
1909 num_accesses
+= thisrun_accesses
;
1913 while (num_accesses
< count
)
1916 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1917 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1919 for (i
= 1; i
<= thisrun_accesses
; i
++)
1923 reg
[i
] = *buffer
++ & 0xff;
1926 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1928 for (i
= 1; i
<= thisrun_accesses
; i
++)
1930 arm7_9
->store_byte_reg(target
, i
);
1931 /* fast memory writes are only safe when the target is running
1932 * from a sufficiently high clock (32 kHz is usually too slow)
1934 if (arm7_9
->fast_memory_access
)
1935 arm7_9_execute_fast_sys_speed(target
);
1937 arm7_9_execute_sys_speed(target
);
1940 num_accesses
+= thisrun_accesses
;
1944 ERROR("BUG: we shouldn't get here");
1950 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1951 embeddedice_store_reg(dbg_ctrl
);
1953 for (i
=0; i
<=last_reg
; i
++)
1954 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1956 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1957 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1959 ERROR("JTAG error while reading cpsr");
1963 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1965 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1967 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1969 return ERROR_TARGET_DATA_ABORT
;
1975 int arm7_9_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
1977 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1978 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1979 enum armv4_5_state core_state
= armv4_5
->core_state
;
1980 u32 r0
= buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32);
1981 u32 r1
= buf_get_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32);
1982 u32 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1987 /* MRC TST BNE MRC STR B */
1988 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1991 if (!arm7_9
->dcc_downloads
)
1992 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
1994 /* regrab previously allocated working_area, or allocate a new one */
1995 if (!arm7_9
->dcc_working_area
)
1997 u8 dcc_code_buf
[6 * 4];
1999 /* make sure we have a working area */
2000 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2002 INFO("no working area available, falling back to memory writes");
2003 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2006 /* copy target instructions to target endianness */
2007 for (i
= 0; i
< 6; i
++)
2009 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2012 /* write DCC code to working area */
2013 target
->type
->write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
);
2016 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, address
);
2017 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2018 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2019 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
2021 arm7_9_resume(target
, 0, arm7_9
->dcc_working_area
->address
, 1, 1);
2023 for (i
= 0; i
< count
; i
++)
2025 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], target_buffer_get_u32(target
, buffer
));
2029 target
->type
->halt(target
);
2031 while (target
->state
!= TARGET_HALTED
)
2032 target
->type
->poll(target
);
2034 /* restore target state */
2035 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, r0
);
2036 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2037 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2038 buf_set_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32, r1
);
2039 armv4_5
->core_cache
->reg_list
[1].valid
= 1;
2040 armv4_5
->core_cache
->reg_list
[1].dirty
= 1;
2041 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
2042 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
2043 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
2044 armv4_5
->core_state
= core_state
;
2049 int arm7_9_register_commands(struct command_context_s
*cmd_ctx
)
2051 command_t
*arm7_9_cmd
;
2053 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9", NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2055 register_command(cmd_ctx
, arm7_9_cmd
, "etm", handle_arm7_9_etm_command
, COMMAND_CONFIG
, NULL
);
2056 register_command(cmd_ctx
, arm7_9_cmd
, "etb", handle_arm7_9_etb_command
, COMMAND_CONFIG
, NULL
);
2058 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr", handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
, "write program status register <value> <not cpsr|spsr>");
2059 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2061 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg", handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
, "write core register <num> <mode> <value>");
2063 register_command(cmd_ctx
, arm7_9_cmd
, "sw_bkpts", handle_arm7_9_sw_bkpts_command
, COMMAND_EXEC
, "support for software breakpoints <enable|disable>");
2064 register_command(cmd_ctx
, arm7_9_cmd
, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command
, COMMAND_EXEC
, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2065 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq", handle_arm7_9_dbgrq_command
,
2066 COMMAND_ANY
, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2067 register_command(cmd_ctx
, arm7_9_cmd
, "fast_writes", handle_arm7_9_fast_memory_access_command
,
2068 COMMAND_ANY
, "(deprecated, see: arm7_9 fast_memory_access)");
2069 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access", handle_arm7_9_fast_memory_access_command
,
2070 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2071 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads", handle_arm7_9_dcc_downloads_command
,
2072 COMMAND_ANY
, "use DCC downloads for larger memory writes <enable|disable>");
2074 armv4_5_register_commands(cmd_ctx
);
2079 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2084 target_t
*target
= get_current_target(cmd_ctx
);
2085 armv4_5_common_t
*armv4_5
;
2086 arm7_9_common_t
*arm7_9
;
2088 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2090 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2094 if (target
->state
!= TARGET_HALTED
)
2096 command_print(cmd_ctx
, "can't write registers while running");
2102 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr|spsr>");
2106 value
= strtoul(args
[0], NULL
, 0);
2107 spsr
= strtol(args
[1], NULL
, 0);
2109 /* if we're writing the CPSR, mask the T bit */
2113 arm7_9
->write_xpsr(target
, value
, spsr
);
2114 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2116 ERROR("JTAG error while writing to xpsr");
2123 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2129 target_t
*target
= get_current_target(cmd_ctx
);
2130 armv4_5_common_t
*armv4_5
;
2131 arm7_9_common_t
*arm7_9
;
2133 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2135 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2139 if (target
->state
!= TARGET_HALTED
)
2141 command_print(cmd_ctx
, "can't write registers while running");
2147 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2151 value
= strtoul(args
[0], NULL
, 0);
2152 rotate
= strtol(args
[1], NULL
, 0);
2153 spsr
= strtol(args
[2], NULL
, 0);
2155 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2156 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2158 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2165 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2170 target_t
*target
= get_current_target(cmd_ctx
);
2171 armv4_5_common_t
*armv4_5
;
2172 arm7_9_common_t
*arm7_9
;
2174 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2176 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2180 if (target
->state
!= TARGET_HALTED
)
2182 command_print(cmd_ctx
, "can't write registers while running");
2188 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
2192 num
= strtol(args
[0], NULL
, 0);
2193 mode
= strtoul(args
[1], NULL
, 0);
2194 value
= strtoul(args
[2], NULL
, 0);
2196 arm7_9_write_core_reg(target
, num
, mode
, value
);
2201 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2203 target_t
*target
= get_current_target(cmd_ctx
);
2204 armv4_5_common_t
*armv4_5
;
2205 arm7_9_common_t
*arm7_9
;
2207 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2209 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2215 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2219 if (strcmp("enable", args
[0]) == 0)
2221 if (arm7_9
->sw_bkpts_use_wp
)
2223 arm7_9_enable_sw_bkpts(target
);
2227 arm7_9
->sw_bkpts_enabled
= 1;
2230 else if (strcmp("disable", args
[0]) == 0)
2232 if (arm7_9
->sw_bkpts_use_wp
)
2234 arm7_9_disable_sw_bkpts(target
);
2238 arm7_9
->sw_bkpts_enabled
= 0;
2243 command_print(cmd_ctx
, "usage: arm7_9 sw_bkpts <enable|disable>");
2246 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2251 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2253 target_t
*target
= get_current_target(cmd_ctx
);
2254 armv4_5_common_t
*armv4_5
;
2255 arm7_9_common_t
*arm7_9
;
2257 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2259 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2263 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
2265 arm7_9
->force_hw_bkpts
= 1;
2266 if (arm7_9
->sw_bkpts_use_wp
)
2268 arm7_9_disable_sw_bkpts(target
);
2271 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
2273 arm7_9
->force_hw_bkpts
= 0;
2277 command_print(cmd_ctx
, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2280 command_print(cmd_ctx
, "force hardware breakpoints %s", (arm7_9
->force_hw_bkpts
) ? "enabled" : "disabled");
2285 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2287 target_t
*target
= get_current_target(cmd_ctx
);
2288 armv4_5_common_t
*armv4_5
;
2289 arm7_9_common_t
*arm7_9
;
2291 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2293 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2299 if (strcmp("enable", args
[0]) == 0)
2301 arm7_9
->use_dbgrq
= 1;
2303 else if (strcmp("disable", args
[0]) == 0)
2305 arm7_9
->use_dbgrq
= 0;
2309 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable|disable>");
2313 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2318 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2320 target_t
*target
= get_current_target(cmd_ctx
);
2321 armv4_5_common_t
*armv4_5
;
2322 arm7_9_common_t
*arm7_9
;
2324 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2326 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2332 if (strcmp("enable", args
[0]) == 0)
2334 arm7_9
->fast_memory_access
= 1;
2336 else if (strcmp("disable", args
[0]) == 0)
2338 arm7_9
->fast_memory_access
= 0;
2342 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable|disable>");
2346 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2351 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2353 target_t
*target
= get_current_target(cmd_ctx
);
2354 armv4_5_common_t
*armv4_5
;
2355 arm7_9_common_t
*arm7_9
;
2357 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2359 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2365 if (strcmp("enable", args
[0]) == 0)
2367 arm7_9
->dcc_downloads
= 1;
2369 else if (strcmp("disable", args
[0]) == 0)
2371 arm7_9
->dcc_downloads
= 0;
2375 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable|disable>");
2379 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2384 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2387 armv4_5_common_t
*armv4_5
;
2388 arm7_9_common_t
*arm7_9
;
2392 ERROR("incomplete 'arm7_9 etm <target>' command");
2396 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
2400 ERROR("target number '%s' not defined", args
[0]);
2404 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2406 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2410 arm7_9
->has_etm
= 1;
2415 int handle_arm7_9_etb_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2418 jtag_device_t
*jtag_device
;
2419 armv4_5_common_t
*armv4_5
;
2420 arm7_9_common_t
*arm7_9
;
2424 ERROR("incomplete 'arm7_9 etb <target> <chain_pos>' command");
2428 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
2432 ERROR("target number '%s' not defined", args
[0]);
2436 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2438 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2442 jtag_device
= jtag_get_device(strtoul(args
[1], NULL
, 0));
2446 ERROR("jtag device number '%s' not defined", args
[1]);
2450 arm7_9
->etb
= malloc(sizeof(etb_t
));
2452 arm7_9
->etb
->chain_pos
= strtoul(args
[1], NULL
, 0);
2453 arm7_9
->etb
->cur_scan_chain
= -1;
2454 arm7_9
->etb
->reg_cache
= NULL
;
2459 int arm7_9_init_arch_info(target_t
*target
, arm7_9_common_t
*arm7_9
)
2461 armv4_5_common_t
*armv4_5
= &arm7_9
->armv4_5_common
;
2463 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2465 arm_jtag_setup_connection(&arm7_9
->jtag_info
);
2466 arm7_9
->wp_available
= 2;
2467 arm7_9
->wp0_used
= 0;
2468 arm7_9
->wp1_used
= 0;
2469 arm7_9
->force_hw_bkpts
= 0;
2470 arm7_9
->use_dbgrq
= 0;
2472 arm7_9
->has_etm
= 0;
2474 arm7_9
->has_single_step
= 0;
2475 arm7_9
->has_monitor_mode
= 0;
2476 arm7_9
->has_vector_catch
= 0;
2478 arm7_9
->reinit_embeddedice
= 0;
2480 arm7_9
->dcc_working_area
= NULL
;
2482 arm7_9
->fast_memory_access
= 0;
2483 arm7_9
->dcc_downloads
= 0;
2485 jtag_register_event_callback(arm7_9_jtag_callback
, target
);
2487 armv4_5
->arch_info
= arm7_9
;
2488 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2489 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2490 armv4_5
->full_context
= arm7_9_full_context
;
2492 armv4_5_init_arch_info(target
, armv4_5
);
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