1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2008 by Hongtao Zheng *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
33 #include "embeddedice.h"
34 #include "target_request.h"
35 #include "arm7_9_common.h"
36 #include "time_support.h"
37 #include "arm_simulator.h"
42 * Hold common code supporting the ARM7 and ARM9 core generations.
44 * While the ARM core implementations evolved substantially during these
45 * two generations, they look quite similar from the JTAG perspective.
46 * Both have similar debug facilities, based on the same two scan chains
47 * providing access to the core and to an EmbeddedICE module. Both can
48 * support similar ETM and ETB modules, for tracing. And both expose
49 * what could be viewed as "ARM Classic", with multiple processor modes,
50 * shadowed registers, and support for the Thumb instruction set.
52 * Processor differences include things like presence or absence of MMU
53 * and cache, pipeline sizes, use of a modified Harvard Architecure
54 * (with separate instruction and data busses from the CPU), support
55 * for cpu clock gating during idle, and more.
58 static int arm7_9_debug_entry(struct target
*target
);
61 * Clear watchpoints for an ARM7/9 target.
63 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
64 * @return JTAG error status after executing queue
66 static int arm7_9_clear_watchpoints(struct arm7_9_common
*arm7_9
)
69 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
70 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
71 arm7_9
->sw_breakpoint_count
= 0;
72 arm7_9
->sw_breakpoints_added
= 0;
74 arm7_9
->wp1_used
= arm7_9
->wp1_used_default
;
75 arm7_9
->wp_available
= arm7_9
->wp_available_max
;
77 return jtag_execute_queue();
81 * Assign a watchpoint to one of the two available hardware comparators in an
82 * ARM7 or ARM9 target.
84 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
85 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
87 static void arm7_9_assign_wp(struct arm7_9_common
*arm7_9
, struct breakpoint
*breakpoint
)
89 if (!arm7_9
->wp0_used
)
93 arm7_9
->wp_available
--;
95 else if (!arm7_9
->wp1_used
)
99 arm7_9
->wp_available
--;
103 LOG_ERROR("BUG: no hardware comparator available");
105 LOG_DEBUG("BPID: %d (0x%08" PRIx32
") using hw wp: %d",
106 breakpoint
->unique_id
,
112 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
114 * @param arm7_9 Pointer to common struct for ARM7/9 targets
115 * @return Error codes if there is a problem finding a watchpoint or the result
116 * of executing the JTAG queue
118 static int arm7_9_set_software_breakpoints(struct arm7_9_common
*arm7_9
)
120 if (arm7_9
->sw_breakpoints_added
)
124 if (arm7_9
->wp_available
< 1)
126 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
127 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
129 arm7_9
->wp_available
--;
131 /* pick a breakpoint unit */
132 if (!arm7_9
->wp0_used
)
134 arm7_9
->sw_breakpoints_added
= 1;
135 arm7_9
->wp0_used
= 3;
136 } else if (!arm7_9
->wp1_used
)
138 arm7_9
->sw_breakpoints_added
= 2;
139 arm7_9
->wp1_used
= 3;
143 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
147 if (arm7_9
->sw_breakpoints_added
== 1)
149 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
150 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
151 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
152 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
153 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
155 else if (arm7_9
->sw_breakpoints_added
== 2)
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
161 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
165 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
168 LOG_DEBUG("SW BP using hw wp: %d",
169 arm7_9
->sw_breakpoints_added
);
171 return jtag_execute_queue();
175 * Setup the common pieces for an ARM7/9 target after reset or on startup.
177 * @param target Pointer to an ARM7/9 target to setup
178 * @return Result of clearing the watchpoints on the target
180 int arm7_9_setup(struct target
*target
)
182 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
184 return arm7_9_clear_watchpoints(arm7_9
);
188 * Set either a hardware or software breakpoint on an ARM7/9 target. The
189 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
190 * might have erased the values in Embedded ICE.
192 * @param target Pointer to the target device to set the breakpoints on
193 * @param breakpoint Pointer to the breakpoint to be set
194 * @return For hardware breakpoints, this is the result of executing the JTAG
195 * queue. For software breakpoints, this will be the status of the
196 * required memory reads and writes
198 int arm7_9_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
200 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
201 int retval
= ERROR_OK
;
203 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
", Type: %d" ,
204 breakpoint
->unique_id
,
208 if (target
->state
!= TARGET_HALTED
)
210 LOG_WARNING("target not halted");
211 return ERROR_TARGET_NOT_HALTED
;
214 if (breakpoint
->type
== BKPT_HARD
)
216 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
217 uint32_t mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
219 /* reassign a hw breakpoint */
220 if (breakpoint
->set
== 0)
222 arm7_9_assign_wp(arm7_9
, breakpoint
);
225 if (breakpoint
->set
== 1)
227 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
228 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
229 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
230 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
231 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
233 else if (breakpoint
->set
== 2)
235 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
236 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
237 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
238 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
239 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
243 LOG_ERROR("BUG: no hardware comparator available");
247 retval
= jtag_execute_queue();
249 else if (breakpoint
->type
== BKPT_SOFT
)
251 /* did we already set this breakpoint? */
255 if (breakpoint
->length
== 4)
257 uint32_t verify
= 0xffffffff;
258 /* keep the original instruction in target endianness */
259 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
263 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
264 if ((retval
= target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
)) != ERROR_OK
)
269 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
273 if (verify
!= arm7_9
->arm_bkpt
)
275 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
281 uint16_t verify
= 0xffff;
282 /* keep the original instruction in target endianness */
283 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
287 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
288 if ((retval
= target_write_u16(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
)) != ERROR_OK
)
293 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
297 if (verify
!= arm7_9
->thumb_bkpt
)
299 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
304 if ((retval
= arm7_9_set_software_breakpoints(arm7_9
)) != ERROR_OK
)
307 arm7_9
->sw_breakpoint_count
++;
316 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
317 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
318 * will be updated. Otherwise, the software breakpoint will be restored to its
319 * original instruction if it hasn't already been modified.
321 * @param target Pointer to ARM7/9 target to unset the breakpoint from
322 * @param breakpoint Pointer to breakpoint to be unset
323 * @return For hardware breakpoints, this is the result of executing the JTAG
324 * queue. For software breakpoints, this will be the status of the
325 * required memory reads and writes
327 int arm7_9_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
329 int retval
= ERROR_OK
;
330 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
332 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
,
333 breakpoint
->unique_id
,
334 breakpoint
->address
);
336 if (!breakpoint
->set
)
338 LOG_WARNING("breakpoint not set");
342 if (breakpoint
->type
== BKPT_HARD
)
344 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
345 breakpoint
->unique_id
,
347 if (breakpoint
->set
== 1)
349 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
350 arm7_9
->wp0_used
= 0;
351 arm7_9
->wp_available
++;
353 else if (breakpoint
->set
== 2)
355 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
356 arm7_9
->wp1_used
= 0;
357 arm7_9
->wp_available
++;
359 retval
= jtag_execute_queue();
364 /* restore original instruction (kept in target endianness) */
365 if (breakpoint
->length
== 4)
367 uint32_t current_instr
;
368 /* check that user program as not modified breakpoint instruction */
369 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
373 if (current_instr
== arm7_9
->arm_bkpt
)
374 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
381 uint16_t current_instr
;
382 /* check that user program as not modified breakpoint instruction */
383 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
387 if (current_instr
== arm7_9
->thumb_bkpt
)
388 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
394 if (--arm7_9
->sw_breakpoint_count
==0)
396 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
397 if (arm7_9
->sw_breakpoints_added
== 1)
399 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0);
401 else if (arm7_9
->sw_breakpoints_added
== 2)
403 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0);
414 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
415 * dangling breakpoints and that the desired breakpoint can be added.
417 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
418 * @param breakpoint Pointer to the breakpoint to be added
419 * @return An error status if there is a problem adding the breakpoint or the
420 * result of setting the breakpoint
422 int arm7_9_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
424 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
426 if (target
->state
!= TARGET_HALTED
)
428 LOG_WARNING("target not halted");
429 return ERROR_TARGET_NOT_HALTED
;
432 if (arm7_9
->breakpoint_count
== 0)
434 /* make sure we don't have any dangling breakpoints. This is vital upon
435 * GDB connect/disconnect
437 arm7_9_clear_watchpoints(arm7_9
);
440 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
442 LOG_INFO("no watchpoint unit available for hardware breakpoint");
443 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
446 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
448 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
452 if (breakpoint
->type
== BKPT_HARD
)
454 arm7_9_assign_wp(arm7_9
, breakpoint
);
457 arm7_9
->breakpoint_count
++;
459 return arm7_9_set_breakpoint(target
, breakpoint
);
463 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
464 * dangling breakpoints and updates available watchpoints if it is a hardware
467 * @param target Pointer to the target to have a breakpoint removed
468 * @param breakpoint Pointer to the breakpoint to be removed
469 * @return Error status if there was a problem unsetting the breakpoint or the
470 * watchpoints could not be cleared
472 int arm7_9_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
474 int retval
= ERROR_OK
;
475 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
477 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
482 if (breakpoint
->type
== BKPT_HARD
)
483 arm7_9
->wp_available
++;
485 arm7_9
->breakpoint_count
--;
486 if (arm7_9
->breakpoint_count
== 0)
488 /* make sure we don't have any dangling breakpoints */
489 if ((retval
= arm7_9_clear_watchpoints(arm7_9
)) != ERROR_OK
)
499 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
500 * considered a bug to call this function when there are no available watchpoint
503 * @param target Pointer to an ARM7/9 target to set a watchpoint on
504 * @param watchpoint Pointer to the watchpoint to be set
505 * @return Error status if watchpoint set fails or the result of executing the
508 int arm7_9_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
510 int retval
= ERROR_OK
;
511 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
515 mask
= watchpoint
->length
- 1;
517 if (target
->state
!= TARGET_HALTED
)
519 LOG_WARNING("target not halted");
520 return ERROR_TARGET_NOT_HALTED
;
523 if (watchpoint
->rw
== WPT_ACCESS
)
528 if (!arm7_9
->wp0_used
)
530 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
531 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
532 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
533 if (watchpoint
->mask
!= 0xffffffffu
)
534 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
535 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
536 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
538 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
543 arm7_9
->wp0_used
= 2;
545 else if (!arm7_9
->wp1_used
)
547 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
548 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
549 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
550 if (watchpoint
->mask
!= 0xffffffffu
)
551 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
552 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
553 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
555 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
560 arm7_9
->wp1_used
= 2;
564 LOG_ERROR("BUG: no hardware comparator available");
572 * Unset an existing watchpoint and clear the used watchpoint unit.
574 * @param target Pointer to the target to have the watchpoint removed
575 * @param watchpoint Pointer to the watchpoint to be removed
576 * @return Error status while trying to unset the watchpoint or the result of
577 * executing the JTAG queue
579 int arm7_9_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
581 int retval
= ERROR_OK
;
582 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
584 if (target
->state
!= TARGET_HALTED
)
586 LOG_WARNING("target not halted");
587 return ERROR_TARGET_NOT_HALTED
;
590 if (!watchpoint
->set
)
592 LOG_WARNING("breakpoint not set");
596 if (watchpoint
->set
== 1)
598 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
599 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
603 arm7_9
->wp0_used
= 0;
605 else if (watchpoint
->set
== 2)
607 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
608 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
612 arm7_9
->wp1_used
= 0;
620 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
621 * available, an error response is returned.
623 * @param target Pointer to the ARM7/9 target to add a watchpoint to
624 * @param watchpoint Pointer to the watchpoint to be added
625 * @return Error status while trying to add the watchpoint
627 int arm7_9_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
629 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
631 if (target
->state
!= TARGET_HALTED
)
633 LOG_WARNING("target not halted");
634 return ERROR_TARGET_NOT_HALTED
;
637 if (arm7_9
->wp_available
< 1)
639 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
642 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
644 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
647 arm7_9
->wp_available
--;
653 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
654 * the used watchpoint unit will be reopened.
656 * @param target Pointer to the target to remove a watchpoint from
657 * @param watchpoint Pointer to the watchpoint to be removed
658 * @return Result of trying to unset the watchpoint
660 int arm7_9_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
662 int retval
= ERROR_OK
;
663 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
667 if ((retval
= arm7_9_unset_watchpoint(target
, watchpoint
)) != ERROR_OK
)
673 arm7_9
->wp_available
++;
679 * Restarts the target by sending a RESTART instruction and moving the JTAG
680 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
681 * asserted by the processor.
683 * @param target Pointer to target to issue commands to
684 * @return Error status if there is a timeout or a problem while executing the
687 int arm7_9_execute_sys_speed(struct target
*target
)
690 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
691 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
692 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
694 /* set RESTART instruction */
695 jtag_set_end_state(TAP_IDLE
);
696 if (arm7_9
->need_bypass_before_restart
) {
697 arm7_9
->need_bypass_before_restart
= 0;
698 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
700 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
702 long long then
= timeval_ms();
704 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
706 /* read debug status register */
707 embeddedice_read_reg(dbg_stat
);
708 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
710 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
711 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
713 if (debug_level
>= 3)
723 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32
"", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
724 return ERROR_TARGET_TIMEOUT
;
731 * Restarts the target by sending a RESTART instruction and moving the JTAG
732 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
733 * waiting until they are.
735 * @param target Pointer to the target to issue commands to
736 * @return Always ERROR_OK
738 int arm7_9_execute_fast_sys_speed(struct target
*target
)
741 static uint8_t check_value
[4], check_mask
[4];
743 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
744 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
745 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
747 /* set RESTART instruction */
748 jtag_set_end_state(TAP_IDLE
);
749 if (arm7_9
->need_bypass_before_restart
) {
750 arm7_9
->need_bypass_before_restart
= 0;
751 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
753 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
757 /* check for DBGACK and SYSCOMP set (others don't care) */
759 /* NB! These are constants that must be available until after next jtag_execute() and
760 * we evaluate the values upon first execution in lieu of setting up these constants
761 * during early setup.
763 buf_set_u32(check_value
, 0, 32, 0x9);
764 buf_set_u32(check_mask
, 0, 32, 0x9);
768 /* read debug status register */
769 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_mask
);
775 * Get some data from the ARM7/9 target.
777 * @param target Pointer to the ARM7/9 target to read data from
778 * @param size The number of 32bit words to be read
779 * @param buffer Pointer to the buffer that will hold the data
780 * @return The result of receiving data from the Embedded ICE unit
782 int arm7_9_target_request_data(struct target
*target
, uint32_t size
, uint8_t *buffer
)
784 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
785 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
787 int retval
= ERROR_OK
;
790 data
= malloc(size
* (sizeof(uint32_t)));
792 retval
= embeddedice_receive(jtag_info
, data
, size
);
794 /* return the 32-bit ints in the 8-bit array */
795 for (i
= 0; i
< size
; i
++)
797 h_u32_to_le(buffer
+ (i
* 4), data
[i
]);
806 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
807 * target is running and the DCC control register has the W bit high, this will
808 * execute the request on the target.
810 * @param priv Void pointer expected to be a struct target pointer
811 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
812 * from the Embedded ICE unit
814 int arm7_9_handle_target_request(void *priv
)
816 int retval
= ERROR_OK
;
817 struct target
*target
= priv
;
818 if (!target_was_examined(target
))
820 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
821 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
822 struct reg
*dcc_control
= &arm7_9
->eice_cache
->reg_list
[EICE_COMMS_CTRL
];
824 if (!target
->dbg_msg_enabled
)
827 if (target
->state
== TARGET_RUNNING
)
829 /* read DCC control register */
830 embeddedice_read_reg(dcc_control
);
831 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
837 if (buf_get_u32(dcc_control
->value
, 1, 1) == 1)
841 if ((retval
= embeddedice_receive(jtag_info
, &request
, 1)) != ERROR_OK
)
845 if ((retval
= target_request(target
, request
)) != ERROR_OK
)
856 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
857 * is manipulated to the right halted state based on its current state. This is
861 * <tr><th > State</th><th > Action</th></tr>
862 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
863 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
864 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
865 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
868 * If the target does not end up in the halted state, a warning is produced. If
869 * DBGACK is cleared, then the target is expected to either be running or
872 * @param target Pointer to the ARM7/9 target to poll
873 * @return ERROR_OK or an error status if a command fails
875 int arm7_9_poll(struct target
*target
)
878 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
879 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
881 /* read debug status register */
882 embeddedice_read_reg(dbg_stat
);
883 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
888 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
890 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
891 if (target
->state
== TARGET_UNKNOWN
)
893 /* Starting OpenOCD with target in debug-halt */
894 target
->state
= TARGET_RUNNING
;
895 LOG_DEBUG("DBGACK already set during server startup.");
897 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
900 if (target
->state
== TARGET_RESET
)
902 if (target
->reset_halt
)
904 enum reset_types jtag_reset_config
= jtag_get_reset_config();
905 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0)
912 target
->state
= TARGET_HALTED
;
914 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
919 struct reg
*reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
920 uint32_t t
=*((uint32_t *)reg
->value
);
923 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
927 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
932 if (target
->state
== TARGET_DEBUG_RUNNING
)
934 target
->state
= TARGET_HALTED
;
935 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
938 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
)) != ERROR_OK
)
943 if (target
->state
!= TARGET_HALTED
)
945 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target
->state
);
950 if (target
->state
!= TARGET_DEBUG_RUNNING
)
951 target
->state
= TARGET_RUNNING
;
958 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
959 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
960 * affected) completely stop the JTAG clock while the core is held in reset
961 * (SRST). It isn't possible to program the halt condition once reset is
962 * asserted, hence a hook that allows the target to set up its reset-halt
963 * condition is setup prior to asserting reset.
965 * @param target Pointer to an ARM7/9 target to assert reset on
966 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
968 int arm7_9_assert_reset(struct target
*target
)
970 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
972 LOG_DEBUG("target->state: %s",
973 target_state_name(target
));
975 enum reset_types jtag_reset_config
= jtag_get_reset_config();
976 if (!(jtag_reset_config
& RESET_HAS_SRST
))
978 LOG_ERROR("Can't assert SRST");
982 /* At this point trst has been asserted/deasserted once. We would
983 * like to program EmbeddedICE while SRST is asserted, instead of
984 * depending on SRST to leave that module alone. However, many CPUs
985 * gate the JTAG clock while SRST is asserted; or JTAG may need
986 * clock stability guarantees (adaptive clocking might help).
988 * So we assume JTAG access during SRST is off the menu unless it's
989 * been specifically enabled.
991 bool srst_asserted
= false;
993 if (((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0)
994 && (jtag_reset_config
& RESET_SRST_NO_GATING
))
996 jtag_add_reset(0, 1);
997 srst_asserted
= true;
1000 if (target
->reset_halt
)
1003 * Some targets do not support communication while SRST is asserted. We need to
1004 * set up the reset vector catch here.
1006 * If TRST is asserted, then these settings will be reset anyway, so setting them
1009 if (arm7_9
->has_vector_catch
)
1011 /* program vector catch register to catch reset vector */
1012 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
], 0x1);
1014 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1015 jtag_add_runtest(1, jtag_get_end_state());
1019 /* program watchpoint unit to match on reset vector address */
1020 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], 0x0);
1021 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0x3);
1022 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1023 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1024 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1028 /* here we should issue an SRST only, but we may have to assert TRST as well */
1029 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1031 jtag_add_reset(1, 1);
1032 } else if (!srst_asserted
)
1034 jtag_add_reset(0, 1);
1037 target
->state
= TARGET_RESET
;
1038 jtag_add_sleep(50000);
1040 armv4_5_invalidate_core_regs(target
);
1042 if ((target
->reset_halt
) && ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0))
1044 /* debug entry was already prepared in arm7_9_assert_reset() */
1045 target
->debug_reason
= DBG_REASON_DBGRQ
;
1052 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1053 * and the target is being reset into a halt, a warning will be triggered
1054 * because it is not possible to reset into a halted mode in this case. The
1055 * target is halted using the target's functions.
1057 * @param target Pointer to the target to have the reset deasserted
1058 * @return ERROR_OK or an error from polling or halting the target
1060 int arm7_9_deassert_reset(struct target
*target
)
1062 int retval
= ERROR_OK
;
1063 LOG_DEBUG("target->state: %s",
1064 target_state_name(target
));
1066 /* deassert reset lines */
1067 jtag_add_reset(0, 0);
1069 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1070 if (target
->reset_halt
&& (jtag_reset_config
& RESET_SRST_PULLS_TRST
) != 0)
1072 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1073 /* set up embedded ice registers again */
1074 if ((retval
= target_examine_one(target
)) != ERROR_OK
)
1077 if ((retval
= target_poll(target
)) != ERROR_OK
)
1082 if ((retval
= target_halt(target
)) != ERROR_OK
)
1092 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1093 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1094 * vector catch was used, it is restored. Otherwise, the control value is
1095 * restored and the watchpoint unit is restored if it was in use.
1097 * @param target Pointer to the ARM7/9 target to have halt cleared
1098 * @return Always ERROR_OK
1100 int arm7_9_clear_halt(struct target
*target
)
1102 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1103 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1105 /* we used DBGRQ only if we didn't come out of reset */
1106 if (!arm7_9
->debug_entry_from_reset
&& arm7_9
->use_dbgrq
)
1108 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1110 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1111 embeddedice_store_reg(dbg_ctrl
);
1115 if (arm7_9
->debug_entry_from_reset
&& arm7_9
->has_vector_catch
)
1117 /* if we came out of reset, and vector catch is supported, we used
1118 * vector catch to enter debug state
1119 * restore the register in that case
1121 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
]);
1125 /* restore registers if watchpoint unit 0 was in use
1127 if (arm7_9
->wp0_used
)
1129 if (arm7_9
->debug_entry_from_reset
)
1131 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
]);
1133 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1134 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1135 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1137 /* control value always has to be restored, as it was either disabled,
1138 * or enabled with possibly different bits
1140 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1148 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1149 * and then there is a wait until the processor shows the halt. This wait can
1150 * timeout and results in an error being returned. The software reset involves
1151 * clearing the halt, updating the debug control register, changing to ARM mode,
1152 * reset of the program counter, and reset of all of the registers.
1154 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1155 * @return Error status if any of the commands fail, otherwise ERROR_OK
1157 int arm7_9_soft_reset_halt(struct target
*target
)
1159 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1160 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1161 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1162 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1166 /* FIX!!! replace some of this code with tcl commands
1168 * halt # the halt command is synchronous
1169 * armv4_5 core_state arm
1173 if ((retval
= target_halt(target
)) != ERROR_OK
)
1176 long long then
= timeval_ms();
1178 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
1180 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) != 0)
1182 embeddedice_read_reg(dbg_stat
);
1183 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1185 if (debug_level
>= 3)
1195 LOG_ERROR("Failed to halt CPU after 1 sec");
1196 return ERROR_TARGET_TIMEOUT
;
1198 target
->state
= TARGET_HALTED
;
1200 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1201 * ensure that DBGRQ is cleared
1203 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1204 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1205 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1206 embeddedice_store_reg(dbg_ctrl
);
1208 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1213 /* if the target is in Thumb state, change to ARM state */
1214 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1216 uint32_t r0_thumb
, pc_thumb
;
1217 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1218 /* Entered debug from Thumb mode */
1219 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1220 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1223 /* all register content is now invalid */
1224 if ((retval
= armv4_5_invalidate_core_regs(target
)) != ERROR_OK
)
1229 /* SVC, ARM state, IRQ and FIQ disabled */
1230 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
1231 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1232 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1234 /* start fetching from 0x0 */
1235 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
1236 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1237 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1239 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
1240 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1242 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1245 /* reset registers */
1246 for (i
= 0; i
<= 14; i
++)
1248 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
1249 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1250 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1253 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
1262 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1263 * line or by programming a watchpoint to trigger on any address. It is
1264 * considered a bug to call this function while the target is in the
1265 * TARGET_RESET state.
1267 * @param target Pointer to the ARM7/9 target to be halted
1268 * @return Always ERROR_OK
1270 int arm7_9_halt(struct target
*target
)
1272 if (target
->state
== TARGET_RESET
)
1274 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1278 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1279 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1281 LOG_DEBUG("target->state: %s",
1282 target_state_name(target
));
1284 if (target
->state
== TARGET_HALTED
)
1286 LOG_DEBUG("target was already halted");
1290 if (target
->state
== TARGET_UNKNOWN
)
1292 LOG_WARNING("target was in unknown state when halt was requested");
1295 if (arm7_9
->use_dbgrq
)
1297 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1299 if (arm7_9
->set_special_dbgrq
) {
1300 arm7_9
->set_special_dbgrq(target
);
1302 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
1303 embeddedice_store_reg(dbg_ctrl
);
1308 /* program watchpoint unit to match on any address
1310 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1311 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1312 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1313 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1316 target
->debug_reason
= DBG_REASON_DBGRQ
;
1322 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1323 * ARM. The JTAG queue is then executed and the reason for debug entry is
1324 * examined. Once done, the target is verified to be halted and the processor
1325 * is forced into ARM mode. The core registers are saved for the current core
1326 * mode and the program counter (register 15) is updated as needed. The core
1327 * registers and CPSR and SPSR are saved for restoration later.
1329 * @param target Pointer to target that is entering debug mode
1330 * @return Error code if anything fails, otherwise ERROR_OK
1332 static int arm7_9_debug_entry(struct target
*target
)
1335 uint32_t context
[16];
1336 uint32_t* context_p
[16];
1337 uint32_t r0_thumb
, pc_thumb
;
1340 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1341 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1342 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1343 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1345 #ifdef _DEBUG_ARM7_9_
1349 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1350 * ensure that DBGRQ is cleared
1352 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1353 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1354 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1355 embeddedice_store_reg(dbg_ctrl
);
1357 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1362 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1367 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
1371 if (target
->state
!= TARGET_HALTED
)
1373 LOG_WARNING("target not halted");
1374 return ERROR_TARGET_NOT_HALTED
;
1377 /* if the target is in Thumb state, change to ARM state */
1378 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1380 LOG_DEBUG("target entered debug from Thumb state");
1381 /* Entered debug from Thumb mode */
1382 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1383 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1384 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
", pc_thumb: 0x%8.8" PRIx32
"", r0_thumb
, pc_thumb
);
1388 LOG_DEBUG("target entered debug from ARM state");
1389 /* Entered debug from ARM mode */
1390 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1393 for (i
= 0; i
< 16; i
++)
1394 context_p
[i
] = &context
[i
];
1395 /* save core registers (r0 - r15 of current core mode) */
1396 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
1398 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1400 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1403 /* if the core has been executing in Thumb state, set the T bit */
1404 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1407 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
1408 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1409 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1411 armv4_5
->core_mode
= cpsr
& 0x1f;
1413 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1415 target
->state
= TARGET_UNKNOWN
;
1416 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1417 return ERROR_TARGET_FAILURE
;
1420 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1422 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1424 LOG_DEBUG("thumb state, applying fixups");
1425 context
[0] = r0_thumb
;
1426 context
[15] = pc_thumb
;
1427 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1429 /* adjust value stored by STM */
1430 context
[15] -= 3 * 4;
1433 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
) || (!arm7_9
->use_dbgrq
))
1434 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1436 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1438 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1441 for (i
= 0; i
<= 15; i
++)
1443 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, context
[i
]);
1444 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1445 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1446 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1449 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
"", context
[15]);
1451 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1454 /* exceptions other than USR & SYS have a saved program status register */
1455 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1458 arm7_9
->read_xpsr(target
, &spsr
, 1);
1459 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1463 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1464 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1465 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1468 /* r0 and r15 (pc) have to be restored later */
1469 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1470 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).valid
;
1472 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1475 if (arm7_9
->post_debug_entry
)
1476 arm7_9
->post_debug_entry(target
);
1482 * Validate the full context for an ARM7/9 target in all processor modes. If
1483 * there are any invalid registers for the target, they will all be read. This
1486 * @param target Pointer to the ARM7/9 target to capture the full context from
1487 * @return Error if the target is not halted, has an invalid core mode, or if
1488 * the JTAG queue fails to execute
1490 int arm7_9_full_context(struct target
*target
)
1494 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1495 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1499 if (target
->state
!= TARGET_HALTED
)
1501 LOG_WARNING("target not halted");
1502 return ERROR_TARGET_NOT_HALTED
;
1505 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1508 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1509 * SYS shares registers with User, so we don't touch SYS
1511 for (i
= 0; i
< 6; i
++)
1514 uint32_t* reg_p
[16];
1518 /* check if there are invalid registers in the current mode
1520 for (j
= 0; j
<= 16; j
++)
1522 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1530 /* change processor mode (and mask T bit) */
1531 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1532 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1534 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1536 for (j
= 0; j
< 15; j
++)
1538 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1540 reg_p
[j
] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1542 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1543 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1547 /* if only the PSR is invalid, mask is all zeroes */
1549 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1551 /* check if the PSR has to be read */
1552 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1554 arm7_9
->read_xpsr(target
, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1555 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1556 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1561 /* restore processor mode (mask T bit) */
1562 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1564 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1572 * Restore the processor context on an ARM7/9 target. The full processor
1573 * context is analyzed to see if any of the registers are dirty on this end, but
1574 * have a valid new value. If this is the case, the processor is changed to the
1575 * appropriate mode and the new register values are written out to the
1576 * processor. If there happens to be a dirty register with an invalid value, an
1577 * error will be logged.
1579 * @param target Pointer to the ARM7/9 target to have its context restored
1580 * @return Error status if the target is not halted or the core mode in the
1581 * armv4_5 struct is invalid.
1583 int arm7_9_restore_context(struct target
*target
)
1585 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1586 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1588 struct armv4_5_core_reg
*reg_arch_info
;
1589 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1596 if (target
->state
!= TARGET_HALTED
)
1598 LOG_WARNING("target not halted");
1599 return ERROR_TARGET_NOT_HALTED
;
1602 if (arm7_9
->pre_restore_context
)
1603 arm7_9
->pre_restore_context(target
);
1605 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1608 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1609 * SYS shares registers with User, so we don't touch SYS
1611 for (i
= 0; i
< 6; i
++)
1613 LOG_DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1616 /* check if there are dirty registers in the current mode
1618 for (j
= 0; j
<= 16; j
++)
1620 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1621 reg_arch_info
= reg
->arch_info
;
1622 if (reg
->dirty
== 1)
1624 if (reg
->valid
== 1)
1627 LOG_DEBUG("examining dirty reg: %s", reg
->name
);
1628 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1629 && (reg_arch_info
->mode
!= current_mode
)
1630 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1631 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1634 LOG_DEBUG("require mode change");
1639 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1646 uint32_t mask
= 0x0;
1654 /* change processor mode (mask T bit) */
1655 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1656 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1658 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1659 current_mode
= armv4_5_number_to_mode(i
);
1662 for (j
= 0; j
<= 14; j
++)
1664 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1665 reg_arch_info
= reg
->arch_info
;
1668 if (reg
->dirty
== 1)
1670 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1675 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32
"", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1681 arm7_9
->write_core_regs(target
, mask
, regs
);
1684 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1685 reg_arch_info
= reg
->arch_info
;
1686 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1688 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(reg
->value
, 0, 32));
1689 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1694 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1696 /* restore processor mode (mask T bit) */
1699 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1700 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1702 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr
));
1703 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1705 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1707 /* CPSR has been changed, full restore necessary (mask T bit) */
1708 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1709 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1710 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1711 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1715 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1716 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1717 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1719 if (arm7_9
->post_restore_context
)
1720 arm7_9
->post_restore_context(target
);
1726 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1727 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1730 * @param target Pointer to the ARM7/9 target to be restarted
1731 * @return Result of executing the JTAG queue
1733 int arm7_9_restart_core(struct target
*target
)
1735 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1736 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
1738 /* set RESTART instruction */
1739 jtag_set_end_state(TAP_IDLE
);
1740 if (arm7_9
->need_bypass_before_restart
) {
1741 arm7_9
->need_bypass_before_restart
= 0;
1742 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
1744 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
1746 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE
));
1747 return jtag_execute_queue();
1751 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1752 * iterated through and are set on the target if they aren't already set.
1754 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1756 void arm7_9_enable_watchpoints(struct target
*target
)
1758 struct watchpoint
*watchpoint
= target
->watchpoints
;
1762 if (watchpoint
->set
== 0)
1763 arm7_9_set_watchpoint(target
, watchpoint
);
1764 watchpoint
= watchpoint
->next
;
1769 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1770 * iterated through and are set on the target.
1772 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1774 void arm7_9_enable_breakpoints(struct target
*target
)
1776 struct breakpoint
*breakpoint
= target
->breakpoints
;
1778 /* set any pending breakpoints */
1781 arm7_9_set_breakpoint(target
, breakpoint
);
1782 breakpoint
= breakpoint
->next
;
1786 int arm7_9_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1788 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1789 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1790 struct breakpoint
*breakpoint
= target
->breakpoints
;
1791 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1792 int err
, retval
= ERROR_OK
;
1796 if (target
->state
!= TARGET_HALTED
)
1798 LOG_WARNING("target not halted");
1799 return ERROR_TARGET_NOT_HALTED
;
1802 if (!debug_execution
)
1804 target_free_all_working_areas(target
);
1807 /* current = 1: continue on current pc, otherwise continue at <address> */
1809 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1811 uint32_t current_pc
;
1812 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1814 /* the front-end may request us not to handle breakpoints */
1815 if (handle_breakpoints
)
1817 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1819 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (id: %d)", breakpoint
->address
, breakpoint
->unique_id
);
1820 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1825 /* calculate PC of next instruction */
1827 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1829 uint32_t current_opcode
;
1830 target_read_u32(target
, current_pc
, ¤t_opcode
);
1831 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1835 LOG_DEBUG("enable single-step");
1836 arm7_9
->enable_single_step(target
, next_pc
);
1838 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1840 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1845 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1846 arm7_9
->branch_resume(target
);
1847 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1849 arm7_9
->branch_resume_thumb(target
);
1853 LOG_ERROR("unhandled core state");
1857 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1858 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1859 err
= arm7_9_execute_sys_speed(target
);
1861 LOG_DEBUG("disable single-step");
1862 arm7_9
->disable_single_step(target
);
1864 if (err
!= ERROR_OK
)
1866 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1870 target
->state
= TARGET_UNKNOWN
;
1874 arm7_9_debug_entry(target
);
1875 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1877 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1878 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1885 /* enable any pending breakpoints and watchpoints */
1886 arm7_9_enable_breakpoints(target
);
1887 arm7_9_enable_watchpoints(target
);
1889 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1894 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1896 arm7_9
->branch_resume(target
);
1898 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1900 arm7_9
->branch_resume_thumb(target
);
1904 LOG_ERROR("unhandled core state");
1908 /* deassert DBGACK and INTDIS */
1909 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1910 /* INTDIS only when we really resume, not during debug execution */
1911 if (!debug_execution
)
1912 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1913 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1915 if ((retval
= arm7_9_restart_core(target
)) != ERROR_OK
)
1920 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1922 if (!debug_execution
)
1924 /* registers are now invalid */
1925 armv4_5_invalidate_core_regs(target
);
1926 target
->state
= TARGET_RUNNING
;
1927 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
1934 target
->state
= TARGET_DEBUG_RUNNING
;
1935 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
)) != ERROR_OK
)
1941 LOG_DEBUG("target resumed");
1946 void arm7_9_enable_eice_step(struct target
*target
, uint32_t next_pc
)
1948 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1949 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
1950 uint32_t current_pc
;
1951 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1953 if (next_pc
!= current_pc
)
1955 /* setup an inverse breakpoint on the current PC
1956 * - comparator 1 matches the current address
1957 * - rangeout from comparator 1 is connected to comparator 0 rangein
1958 * - comparator 0 matches any address, as long as rangein is low */
1959 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1960 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1961 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1962 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~(EICE_W_CTRL_RANGE
| EICE_W_CTRL_nOPC
) & 0xff);
1963 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], current_pc
);
1964 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1965 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1966 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1967 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1971 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1972 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
1974 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff);
1975 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], next_pc
);
1976 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1977 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1978 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1979 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1983 void arm7_9_disable_eice_step(struct target
*target
)
1985 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
1987 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1988 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1989 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1990 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1991 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1992 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1993 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1994 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1995 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1998 int arm7_9_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
2000 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2001 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2002 struct breakpoint
*breakpoint
= NULL
;
2005 if (target
->state
!= TARGET_HALTED
)
2007 LOG_WARNING("target not halted");
2008 return ERROR_TARGET_NOT_HALTED
;
2011 /* current = 1: continue on current pc, otherwise continue at <address> */
2013 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
2015 uint32_t current_pc
;
2016 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2018 /* the front-end may request us not to handle breakpoints */
2019 if (handle_breakpoints
)
2020 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
2021 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2026 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2028 /* calculate PC of next instruction */
2030 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
2032 uint32_t current_opcode
;
2033 target_read_u32(target
, current_pc
, ¤t_opcode
);
2034 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
2038 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
2043 arm7_9
->enable_single_step(target
, next_pc
);
2045 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
2047 arm7_9
->branch_resume(target
);
2049 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
2051 arm7_9
->branch_resume_thumb(target
);
2055 LOG_ERROR("unhandled core state");
2059 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
2064 err
= arm7_9_execute_sys_speed(target
);
2065 arm7_9
->disable_single_step(target
);
2067 /* registers are now invalid */
2068 armv4_5_invalidate_core_regs(target
);
2070 if (err
!= ERROR_OK
)
2072 target
->state
= TARGET_UNKNOWN
;
2074 arm7_9_debug_entry(target
);
2075 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
2079 LOG_DEBUG("target stepped");
2083 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2091 int arm7_9_read_core_reg(struct target
*target
, int num
, enum armv4_5_mode mode
)
2093 uint32_t* reg_p
[16];
2096 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2097 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2099 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2102 enum armv4_5_mode reg_mode
= ((struct armv4_5_core_reg
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
2104 if ((num
< 0) || (num
> 16))
2105 return ERROR_INVALID_ARGUMENTS
;
2107 if ((mode
!= ARMV4_5_MODE_ANY
)
2108 && (mode
!= armv4_5
->core_mode
)
2109 && (reg_mode
!= ARMV4_5_MODE_ANY
))
2113 /* change processor mode (mask T bit) */
2114 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
2117 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2120 if ((num
>= 0) && (num
<= 15))
2122 /* read a normal core register */
2123 reg_p
[num
] = &value
;
2125 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
2129 /* read a program status register
2130 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2132 struct armv4_5_core_reg
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
2133 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
2135 arm7_9
->read_xpsr(target
, &value
, spsr
);
2138 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2143 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
2144 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
2145 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
2147 if ((mode
!= ARMV4_5_MODE_ANY
)
2148 && (mode
!= armv4_5
->core_mode
)
2149 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2150 /* restore processor mode (mask T bit) */
2151 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2157 int arm7_9_write_core_reg(struct target
*target
, int num
, enum armv4_5_mode mode
, uint32_t value
)
2160 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2161 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2163 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2166 enum armv4_5_mode reg_mode
= ((struct armv4_5_core_reg
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
2168 if ((num
< 0) || (num
> 16))
2169 return ERROR_INVALID_ARGUMENTS
;
2171 if ((mode
!= ARMV4_5_MODE_ANY
)
2172 && (mode
!= armv4_5
->core_mode
)
2173 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2176 /* change processor mode (mask T bit) */
2177 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
2180 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2183 if ((num
>= 0) && (num
<= 15))
2185 /* write a normal core register */
2188 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
2192 /* write a program status register
2193 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2195 struct armv4_5_core_reg
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
2196 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
2198 /* if we're writing the CPSR, mask the T bit */
2202 arm7_9
->write_xpsr(target
, value
, spsr
);
2205 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
2206 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
2208 if ((mode
!= ARMV4_5_MODE_ANY
)
2209 && (mode
!= armv4_5
->core_mode
)
2210 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2211 /* restore processor mode (mask T bit) */
2212 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2215 return jtag_execute_queue();
2218 int arm7_9_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2220 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2221 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2223 uint32_t num_accesses
= 0;
2224 int thisrun_accesses
;
2230 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
2232 if (target
->state
!= TARGET_HALTED
)
2234 LOG_WARNING("target not halted");
2235 return ERROR_TARGET_NOT_HALTED
;
2238 /* sanitize arguments */
2239 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2240 return ERROR_INVALID_ARGUMENTS
;
2242 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2243 return ERROR_TARGET_UNALIGNED_ACCESS
;
2245 /* load the base register with the address of the first word */
2247 arm7_9
->write_core_regs(target
, 0x1, reg
);
2254 while (num_accesses
< count
)
2257 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2258 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2260 if (last_reg
<= thisrun_accesses
)
2261 last_reg
= thisrun_accesses
;
2263 arm7_9
->load_word_regs(target
, reg_list
);
2265 /* fast memory reads are only safe when the target is running
2266 * from a sufficiently high clock (32 kHz is usually too slow)
2268 if (arm7_9
->fast_memory_access
)
2269 retval
= arm7_9_execute_fast_sys_speed(target
);
2271 retval
= arm7_9_execute_sys_speed(target
);
2272 if (retval
!= ERROR_OK
)
2275 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
2277 /* advance buffer, count number of accesses */
2278 buffer
+= thisrun_accesses
* 4;
2279 num_accesses
+= thisrun_accesses
;
2281 if ((j
++%1024) == 0)
2288 while (num_accesses
< count
)
2291 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2292 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2294 for (i
= 1; i
<= thisrun_accesses
; i
++)
2298 arm7_9
->load_hword_reg(target
, i
);
2299 /* fast memory reads are only safe when the target is running
2300 * from a sufficiently high clock (32 kHz is usually too slow)
2302 if (arm7_9
->fast_memory_access
)
2303 retval
= arm7_9_execute_fast_sys_speed(target
);
2305 retval
= arm7_9_execute_sys_speed(target
);
2306 if (retval
!= ERROR_OK
)
2313 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
2315 /* advance buffer, count number of accesses */
2316 buffer
+= thisrun_accesses
* 2;
2317 num_accesses
+= thisrun_accesses
;
2319 if ((j
++%1024) == 0)
2326 while (num_accesses
< count
)
2329 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2330 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2332 for (i
= 1; i
<= thisrun_accesses
; i
++)
2336 arm7_9
->load_byte_reg(target
, i
);
2337 /* fast memory reads are only safe when the target is running
2338 * from a sufficiently high clock (32 kHz is usually too slow)
2340 if (arm7_9
->fast_memory_access
)
2341 retval
= arm7_9_execute_fast_sys_speed(target
);
2343 retval
= arm7_9_execute_sys_speed(target
);
2344 if (retval
!= ERROR_OK
)
2350 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
2352 /* advance buffer, count number of accesses */
2353 buffer
+= thisrun_accesses
* 1;
2354 num_accesses
+= thisrun_accesses
;
2356 if ((j
++%1024) == 0)
2363 LOG_ERROR("BUG: we shouldn't get here");
2368 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2371 for (i
= 0; i
<= last_reg
; i
++)
2372 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2374 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2375 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2377 LOG_ERROR("JTAG error while reading cpsr");
2378 return ERROR_TARGET_DATA_ABORT
;
2381 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2383 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2385 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2387 return ERROR_TARGET_DATA_ABORT
;
2393 int arm7_9_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2395 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2396 struct armv4_5_common_s
*armv4_5
= &arm7_9
->armv4_5_common
;
2397 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
2400 uint32_t num_accesses
= 0;
2401 int thisrun_accesses
;
2407 #ifdef _DEBUG_ARM7_9_
2408 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
2411 if (target
->state
!= TARGET_HALTED
)
2413 LOG_WARNING("target not halted");
2414 return ERROR_TARGET_NOT_HALTED
;
2417 /* sanitize arguments */
2418 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2419 return ERROR_INVALID_ARGUMENTS
;
2421 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2422 return ERROR_TARGET_UNALIGNED_ACCESS
;
2424 /* load the base register with the address of the first word */
2426 arm7_9
->write_core_regs(target
, 0x1, reg
);
2428 /* Clear DBGACK, to make sure memory fetches work as expected */
2429 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
2430 embeddedice_store_reg(dbg_ctrl
);
2435 while (num_accesses
< count
)
2438 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2439 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2441 for (i
= 1; i
<= thisrun_accesses
; i
++)
2445 reg
[i
] = target_buffer_get_u32(target
, buffer
);
2449 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2451 arm7_9
->store_word_regs(target
, reg_list
);
2453 /* fast memory writes are only safe when the target is running
2454 * from a sufficiently high clock (32 kHz is usually too slow)
2456 if (arm7_9
->fast_memory_access
)
2457 retval
= arm7_9_execute_fast_sys_speed(target
);
2459 retval
= arm7_9_execute_sys_speed(target
);
2460 if (retval
!= ERROR_OK
)
2465 num_accesses
+= thisrun_accesses
;
2469 while (num_accesses
< count
)
2472 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2473 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2475 for (i
= 1; i
<= thisrun_accesses
; i
++)
2479 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
2483 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2485 for (i
= 1; i
<= thisrun_accesses
; i
++)
2487 arm7_9
->store_hword_reg(target
, i
);
2489 /* fast memory writes are only safe when the target is running
2490 * from a sufficiently high clock (32 kHz is usually too slow)
2492 if (arm7_9
->fast_memory_access
)
2493 retval
= arm7_9_execute_fast_sys_speed(target
);
2495 retval
= arm7_9_execute_sys_speed(target
);
2496 if (retval
!= ERROR_OK
)
2502 num_accesses
+= thisrun_accesses
;
2506 while (num_accesses
< count
)
2509 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2510 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2512 for (i
= 1; i
<= thisrun_accesses
; i
++)
2516 reg
[i
] = *buffer
++ & 0xff;
2519 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2521 for (i
= 1; i
<= thisrun_accesses
; i
++)
2523 arm7_9
->store_byte_reg(target
, i
);
2524 /* fast memory writes are only safe when the target is running
2525 * from a sufficiently high clock (32 kHz is usually too slow)
2527 if (arm7_9
->fast_memory_access
)
2528 retval
= arm7_9_execute_fast_sys_speed(target
);
2530 retval
= arm7_9_execute_sys_speed(target
);
2531 if (retval
!= ERROR_OK
)
2538 num_accesses
+= thisrun_accesses
;
2542 LOG_ERROR("BUG: we shouldn't get here");
2548 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
2549 embeddedice_store_reg(dbg_ctrl
);
2551 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2554 for (i
= 0; i
<= last_reg
; i
++)
2555 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2557 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2558 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2560 LOG_ERROR("JTAG error while reading cpsr");
2561 return ERROR_TARGET_DATA_ABORT
;
2564 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2566 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2568 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2570 return ERROR_TARGET_DATA_ABORT
;
2576 static int dcc_count
;
2577 static uint8_t *dcc_buffer
;
2579 static int arm7_9_dcc_completion(struct target
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
2581 int retval
= ERROR_OK
;
2582 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2584 if ((retval
= target_wait_state(target
, TARGET_DEBUG_RUNNING
, 500)) != ERROR_OK
)
2587 int little
= target
->endianness
== TARGET_LITTLE_ENDIAN
;
2588 int count
= dcc_count
;
2589 uint8_t *buffer
= dcc_buffer
;
2592 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2593 * core function repeated. */
2594 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2597 struct embeddedice_reg
*ice_reg
= arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
].arch_info
;
2598 uint8_t reg_addr
= ice_reg
->addr
& 0x1f;
2599 struct jtag_tap
*tap
;
2600 tap
= ice_reg
->jtag_info
->tap
;
2602 embeddedice_write_dcc(tap
, reg_addr
, buffer
, little
, count
-2);
2603 buffer
+= (count
-2)*4;
2605 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2609 for (i
= 0; i
< count
; i
++)
2611 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2616 if ((retval
= target_halt(target
))!= ERROR_OK
)
2620 return target_wait_state(target
, TARGET_HALTED
, 500);
2623 static const uint32_t dcc_code
[] =
2625 /* r0 == input, points to memory buffer
2629 /* spin until DCC control (c0) reports data arrived */
2630 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2631 0xe3110001, /* tst r1, #1 */
2632 0x0afffffc, /* bne w */
2634 /* read word from DCC (c1), write to memory */
2635 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2636 0xe4801004, /* str r1, [r0], #4 */
2639 0xeafffff9 /* b w */
2642 int armv4_5_run_algorithm_inner(struct target
*target
, int num_mem_params
, struct mem_param
*mem_params
, int num_reg_params
, struct reg_param
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
, int (*run_it
)(struct target
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
));
2644 int arm7_9_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
2647 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2650 if (!arm7_9
->dcc_downloads
)
2651 return target_write_memory(target
, address
, 4, count
, buffer
);
2653 /* regrab previously allocated working_area, or allocate a new one */
2654 if (!arm7_9
->dcc_working_area
)
2656 uint8_t dcc_code_buf
[6 * 4];
2658 /* make sure we have a working area */
2659 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2661 LOG_INFO("no working area available, falling back to memory writes");
2662 return target_write_memory(target
, address
, 4, count
, buffer
);
2665 /* copy target instructions to target endianness */
2666 for (i
= 0; i
< 6; i
++)
2668 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2671 /* write DCC code to working area */
2672 if ((retval
= target_write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
)) != ERROR_OK
)
2678 struct armv4_5_algorithm armv4_5_info
;
2679 struct reg_param reg_params
[1];
2681 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2682 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2683 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2685 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2687 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2690 dcc_buffer
= buffer
;
2691 retval
= armv4_5_run_algorithm_inner(target
, 0, NULL
, 1, reg_params
,
2692 arm7_9
->dcc_working_area
->address
, arm7_9
->dcc_working_area
->address
+ 6*4, 20*1000, &armv4_5_info
, arm7_9_dcc_completion
);
2694 if (retval
== ERROR_OK
)
2696 uint32_t endaddress
= buf_get_u32(reg_params
[0].value
, 0, 32);
2697 if (endaddress
!= (address
+ count
*4))
2699 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32
" got 0x%0" PRIx32
"", (address
+ count
*4), endaddress
);
2700 retval
= ERROR_FAIL
;
2704 destroy_reg_param(®_params
[0]);
2709 int arm7_9_checksum_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
)
2711 struct working_area
*crc_algorithm
;
2712 struct armv4_5_algorithm armv4_5_info
;
2713 struct reg_param reg_params
[2];
2716 static const uint32_t arm7_9_crc_code
[] = {
2717 0xE1A02000, /* mov r2, r0 */
2718 0xE3E00000, /* mov r0, #0xffffffff */
2719 0xE1A03001, /* mov r3, r1 */
2720 0xE3A04000, /* mov r4, #0 */
2721 0xEA00000B, /* b ncomp */
2723 0xE7D21004, /* ldrb r1, [r2, r4] */
2724 0xE59F7030, /* ldr r7, CRC32XOR */
2725 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2726 0xE3A05000, /* mov r5, #0 */
2728 0xE3500000, /* cmp r0, #0 */
2729 0xE1A06080, /* mov r6, r0, asl #1 */
2730 0xE2855001, /* add r5, r5, #1 */
2731 0xE1A00006, /* mov r0, r6 */
2732 0xB0260007, /* eorlt r0, r6, r7 */
2733 0xE3550008, /* cmp r5, #8 */
2734 0x1AFFFFF8, /* bne loop */
2735 0xE2844001, /* add r4, r4, #1 */
2737 0xE1540003, /* cmp r4, r3 */
2738 0x1AFFFFF1, /* bne nbyte */
2740 0xEAFFFFFE, /* b end */
2741 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2746 if (target_alloc_working_area(target
, sizeof(arm7_9_crc_code
), &crc_algorithm
) != ERROR_OK
)
2748 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2751 /* convert flash writing code into a buffer in target endianness */
2752 for (i
= 0; i
< (sizeof(arm7_9_crc_code
)/sizeof(uint32_t)); i
++)
2754 if ((retval
= target_write_u32(target
, crc_algorithm
->address
+ i
*sizeof(uint32_t), arm7_9_crc_code
[i
])) != ERROR_OK
)
2760 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2761 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2762 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2764 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2765 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2767 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2768 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
2770 /* 20 second timeout/megabyte */
2771 int timeout
= 20000 * (1 + (count
/ (1024*1024)));
2773 if ((retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
2774 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(arm7_9_crc_code
) - 8), timeout
, &armv4_5_info
)) != ERROR_OK
)
2776 LOG_ERROR("error executing arm7_9 crc algorithm");
2777 destroy_reg_param(®_params
[0]);
2778 destroy_reg_param(®_params
[1]);
2779 target_free_working_area(target
, crc_algorithm
);
2783 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
2785 destroy_reg_param(®_params
[0]);
2786 destroy_reg_param(®_params
[1]);
2788 target_free_working_area(target
, crc_algorithm
);
2793 int arm7_9_blank_check_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint32_t* blank
)
2795 struct working_area
*erase_check_algorithm
;
2796 struct reg_param reg_params
[3];
2797 struct armv4_5_algorithm armv4_5_info
;
2801 static const uint32_t erase_check_code
[] =
2804 0xe4d03001, /* ldrb r3, [r0], #1 */
2805 0xe0022003, /* and r2, r2, r3 */
2806 0xe2511001, /* subs r1, r1, #1 */
2807 0x1afffffb, /* bne loop */
2809 0xeafffffe /* b end */
2812 /* make sure we have a working area */
2813 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
2815 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2818 /* convert flash writing code into a buffer in target endianness */
2819 for (i
= 0; i
< (sizeof(erase_check_code
)/sizeof(uint32_t)); i
++)
2820 if ((retval
= target_write_u32(target
, erase_check_algorithm
->address
+ i
*sizeof(uint32_t), erase_check_code
[i
])) != ERROR_OK
)
2825 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2826 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2827 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2829 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
2830 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2832 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2833 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
2835 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
2836 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
2838 if ((retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
2839 erase_check_algorithm
->address
, erase_check_algorithm
->address
+ (sizeof(erase_check_code
) - 4), 10000, &armv4_5_info
)) != ERROR_OK
)
2841 destroy_reg_param(®_params
[0]);
2842 destroy_reg_param(®_params
[1]);
2843 destroy_reg_param(®_params
[2]);
2844 target_free_working_area(target
, erase_check_algorithm
);
2848 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
2850 destroy_reg_param(®_params
[0]);
2851 destroy_reg_param(®_params
[1]);
2852 destroy_reg_param(®_params
[2]);
2854 target_free_working_area(target
, erase_check_algorithm
);
2860 * Perform per-target setup that requires JTAG access.
2862 int arm7_9_examine(struct target
*target
)
2864 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2867 if (!target_was_examined(target
)) {
2868 struct reg_cache
*t
, **cache_p
;
2870 t
= embeddedice_build_reg_cache(target
, arm7_9
);
2874 cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2876 arm7_9
->eice_cache
= (*cache_p
);
2878 if (arm7_9
->armv4_5_common
.etm
)
2879 (*cache_p
)->next
= etm_build_reg_cache(target
,
2881 arm7_9
->armv4_5_common
.etm
);
2883 target_set_examined(target
);
2886 retval
= embeddedice_setup(target
);
2887 if (retval
== ERROR_OK
)
2888 retval
= arm7_9_setup(target
);
2889 if (retval
== ERROR_OK
&& arm7_9
->armv4_5_common
.etm
)
2890 retval
= etm_setup(target
);
2895 COMMAND_HANDLER(handle_arm7_9_write_xpsr_command
)
2900 struct target
*target
= get_current_target(cmd_ctx
);
2901 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2903 if (!is_arm7_9(arm7_9
))
2905 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2906 return ERROR_TARGET_INVALID
;
2909 if (target
->state
!= TARGET_HALTED
)
2911 command_print(cmd_ctx
, "can't write registers while running");
2917 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr | spsr>");
2921 COMMAND_PARSE_NUMBER(u32
, args
[0], value
);
2922 COMMAND_PARSE_NUMBER(int, args
[1], spsr
);
2924 /* if we're writing the CPSR, mask the T bit */
2928 arm7_9
->write_xpsr(target
, value
, spsr
);
2929 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2931 LOG_ERROR("JTAG error while writing to xpsr");
2938 COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command
)
2944 struct target
*target
= get_current_target(cmd_ctx
);
2945 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2947 if (!is_arm7_9(arm7_9
))
2949 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2950 return ERROR_TARGET_INVALID
;
2953 if (target
->state
!= TARGET_HALTED
)
2955 command_print(cmd_ctx
, "can't write registers while running");
2961 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
2965 COMMAND_PARSE_NUMBER(u32
, args
[0], value
);
2966 COMMAND_PARSE_NUMBER(int, args
[1], rotate
);
2967 COMMAND_PARSE_NUMBER(int, args
[2], spsr
);
2969 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2970 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2972 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2979 COMMAND_HANDLER(handle_arm7_9_write_core_reg_command
)
2984 struct target
*target
= get_current_target(cmd_ctx
);
2985 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
2987 if (!is_arm7_9(arm7_9
))
2989 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2990 return ERROR_TARGET_INVALID
;
2993 if (target
->state
!= TARGET_HALTED
)
2995 command_print(cmd_ctx
, "can't write registers while running");
3001 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
3005 COMMAND_PARSE_NUMBER(int, args
[0], num
);
3006 COMMAND_PARSE_NUMBER(u32
, args
[1], mode
);
3007 COMMAND_PARSE_NUMBER(u32
, args
[2], value
);
3009 return arm7_9_write_core_reg(target
, num
, mode
, value
);
3012 COMMAND_HANDLER(handle_arm7_9_dbgrq_command
)
3014 struct target
*target
= get_current_target(cmd_ctx
);
3015 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
3017 if (!is_arm7_9(arm7_9
))
3019 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3020 return ERROR_TARGET_INVALID
;
3025 if (strcmp("enable", args
[0]) == 0)
3027 arm7_9
->use_dbgrq
= 1;
3029 else if (strcmp("disable", args
[0]) == 0)
3031 arm7_9
->use_dbgrq
= 0;
3035 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable | disable>");
3039 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
3044 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command
)
3046 struct target
*target
= get_current_target(cmd_ctx
);
3047 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
3049 if (!is_arm7_9(arm7_9
))
3051 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3052 return ERROR_TARGET_INVALID
;
3057 if (strcmp("enable", args
[0]) == 0)
3059 arm7_9
->fast_memory_access
= 1;
3061 else if (strcmp("disable", args
[0]) == 0)
3063 arm7_9
->fast_memory_access
= 0;
3067 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable | disable>");
3071 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
3076 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command
)
3078 struct target
*target
= get_current_target(cmd_ctx
);
3079 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
3081 if (!is_arm7_9(arm7_9
))
3083 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3084 return ERROR_TARGET_INVALID
;
3089 if (strcmp("enable", args
[0]) == 0)
3091 arm7_9
->dcc_downloads
= 1;
3093 else if (strcmp("disable", args
[0]) == 0)
3095 arm7_9
->dcc_downloads
= 0;
3099 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable | disable>");
3103 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
3108 int arm7_9_init_arch_info(struct target
*target
, struct arm7_9_common
*arm7_9
)
3110 int retval
= ERROR_OK
;
3111 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
3113 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
3115 if ((retval
= arm_jtag_setup_connection(&arm7_9
->jtag_info
)) != ERROR_OK
)
3118 /* caller must have allocated via calloc(), so everything's zeroed */
3120 arm7_9
->wp_available_max
= 2;
3122 arm7_9
->fast_memory_access
= fast_and_dangerous
;
3123 arm7_9
->dcc_downloads
= fast_and_dangerous
;
3125 armv4_5
->arch_info
= arm7_9
;
3126 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
3127 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
3128 armv4_5
->full_context
= arm7_9_full_context
;
3130 if ((retval
= armv4_5_init_arch_info(target
, armv4_5
)) != ERROR_OK
)
3133 return target_register_timer_callback(arm7_9_handle_target_request
,
3137 int arm7_9_register_commands(struct command_context
*cmd_ctx
)
3139 struct command
*arm7_9_cmd
;
3141 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9",
3142 NULL
, COMMAND_ANY
, "arm7/9 specific commands");
3144 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr",
3145 handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
,
3146 "write program status register <value> <not cpsr | spsr>");
3147 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8",
3148 handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
,
3149 "write program status register "
3150 "<8bit immediate> <rotate> <not cpsr | spsr>");
3152 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg",
3153 handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
,
3154 "write core register <num> <mode> <value>");
3156 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq",
3157 handle_arm7_9_dbgrq_command
, COMMAND_ANY
,
3158 "use EmbeddedICE dbgrq instead of breakpoint "
3159 "for target halt requests <enable | disable>");
3160 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access",
3161 handle_arm7_9_fast_memory_access_command
, COMMAND_ANY
,
3162 "use fast memory accesses instead of slower "
3163 "but potentially safer accesses <enable | disable>");
3164 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads",
3165 handle_arm7_9_dcc_downloads_command
, COMMAND_ANY
,
3166 "use DCC downloads for larger memory writes <enable | disable>");
3168 armv4_5_register_commands(cmd_ctx
);
3170 etm_register_commands(cmd_ctx
);
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