1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t
*target
);
45 int arm7_9_enable_sw_bkpts(struct target_s
*target
);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
57 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
59 int arm7_9_reinit_embeddedice(target_t
*target
)
61 armv4_5_common_t
*armv4_5
= target
->arch_info
;
62 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
64 breakpoint_t
*breakpoint
= target
->breakpoints
;
66 arm7_9
->wp_available
= 2;
70 /* mark all hardware breakpoints as unset */
73 if (breakpoint
->type
== BKPT_HARD
)
77 breakpoint
= breakpoint
->next
;
80 if (arm7_9
->sw_bkpts_enabled
&& arm7_9
->sw_bkpts_use_wp
)
82 arm7_9
->sw_bkpts_enabled
= 0;
83 arm7_9_enable_sw_bkpts(target
);
86 arm7_9
->reinit_embeddedice
= 0;
91 int arm7_9_jtag_callback(enum jtag_event event
, void *priv
)
93 target_t
*target
= priv
;
94 armv4_5_common_t
*armv4_5
= target
->arch_info
;
95 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
97 /* a test-logic reset occured
98 * the EmbeddedICE registers have been reset
99 * hardware breakpoints have been cleared
101 if (event
== JTAG_TRST_ASSERTED
)
103 arm7_9
->reinit_embeddedice
= 1;
109 int arm7_9_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
)
111 armv4_5_common_t
*armv4_5
= target
->arch_info
;
112 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
114 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
119 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
124 *armv4_5_p
= armv4_5
;
130 int arm7_9_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
132 armv4_5_common_t
*armv4_5
= target
->arch_info
;
133 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
135 if (target
->state
!= TARGET_HALTED
)
137 WARNING("target not halted");
138 return ERROR_TARGET_NOT_HALTED
;
141 if (arm7_9
->force_hw_bkpts
)
142 breakpoint
->type
= BKPT_HARD
;
146 WARNING("breakpoint already set");
150 if (breakpoint
->type
== BKPT_HARD
)
152 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
153 u32 mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
154 if (!arm7_9
->wp0_used
)
156 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
162 jtag_execute_queue();
163 arm7_9
->wp0_used
= 1;
166 else if (!arm7_9
->wp1_used
)
168 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
169 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
170 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
171 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
172 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
174 jtag_execute_queue();
175 arm7_9
->wp1_used
= 1;
180 ERROR("BUG: no hardware comparator available");
184 else if (breakpoint
->type
== BKPT_SOFT
)
186 if (breakpoint
->length
== 4)
188 /* keep the original instruction in target endianness */
189 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
190 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
191 target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
);
195 /* keep the original instruction in target endianness */
196 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
197 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
198 target_write_u32(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
);
207 int arm7_9_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
209 armv4_5_common_t
*armv4_5
= target
->arch_info
;
210 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
212 if (target
->state
!= TARGET_HALTED
)
214 WARNING("target not halted");
215 return ERROR_TARGET_NOT_HALTED
;
218 if (!breakpoint
->set
)
220 WARNING("breakpoint not set");
224 if (breakpoint
->type
== BKPT_HARD
)
226 if (breakpoint
->set
== 1)
228 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
229 jtag_execute_queue();
230 arm7_9
->wp0_used
= 0;
232 else if (breakpoint
->set
== 2)
234 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
235 jtag_execute_queue();
236 arm7_9
->wp1_used
= 0;
242 /* restore original instruction (kept in target endianness) */
243 if (breakpoint
->length
== 4)
245 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
249 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
257 int arm7_9_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
259 armv4_5_common_t
*armv4_5
= target
->arch_info
;
260 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
262 if (target
->state
!= TARGET_HALTED
)
264 WARNING("target not halted");
265 return ERROR_TARGET_NOT_HALTED
;
268 if (arm7_9
->force_hw_bkpts
)
270 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
271 breakpoint
->type
= BKPT_HARD
;
274 if ((breakpoint
->type
== BKPT_SOFT
) && (arm7_9
->sw_bkpts_enabled
== 0))
276 INFO("sw breakpoint requested, but software breakpoints not enabled");
277 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
280 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
282 INFO("no watchpoint unit available for hardware breakpoint");
283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
286 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
288 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
289 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
292 if (breakpoint
->type
== BKPT_HARD
)
293 arm7_9
->wp_available
--;
298 int arm7_9_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
300 armv4_5_common_t
*armv4_5
= target
->arch_info
;
301 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
303 if (target
->state
!= TARGET_HALTED
)
305 WARNING("target not halted");
306 return ERROR_TARGET_NOT_HALTED
;
311 arm7_9_unset_breakpoint(target
, breakpoint
);
314 if (breakpoint
->type
== BKPT_HARD
)
315 arm7_9
->wp_available
++;
320 int arm7_9_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
322 armv4_5_common_t
*armv4_5
= target
->arch_info
;
323 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
327 mask
= watchpoint
->length
- 1;
329 if (target
->state
!= TARGET_HALTED
)
331 WARNING("target not halted");
332 return ERROR_TARGET_NOT_HALTED
;
335 if (watchpoint
->rw
== WPT_ACCESS
)
340 if (!arm7_9
->wp0_used
)
342 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
343 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
344 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
345 if( watchpoint
->mask
!= 0xffffffffu
)
346 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
347 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
348 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
350 jtag_execute_queue();
352 arm7_9
->wp0_used
= 2;
354 else if (!arm7_9
->wp1_used
)
356 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
357 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
358 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
359 if( watchpoint
->mask
!= 0xffffffffu
)
360 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
361 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
362 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
364 jtag_execute_queue();
366 arm7_9
->wp1_used
= 2;
370 ERROR("BUG: no hardware comparator available");
377 int arm7_9_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
379 armv4_5_common_t
*armv4_5
= target
->arch_info
;
380 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
382 if (target
->state
!= TARGET_HALTED
)
384 WARNING("target not halted");
385 return ERROR_TARGET_NOT_HALTED
;
388 if (!watchpoint
->set
)
390 WARNING("breakpoint not set");
394 if (watchpoint
->set
== 1)
396 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
397 jtag_execute_queue();
398 arm7_9
->wp0_used
= 0;
400 else if (watchpoint
->set
== 2)
402 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
403 jtag_execute_queue();
404 arm7_9
->wp1_used
= 0;
411 int arm7_9_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
413 armv4_5_common_t
*armv4_5
= target
->arch_info
;
414 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
416 if (target
->state
!= TARGET_HALTED
)
418 WARNING("target not halted");
419 return ERROR_TARGET_NOT_HALTED
;
422 if (arm7_9
->wp_available
< 1)
424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
427 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
429 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
432 arm7_9
->wp_available
--;
437 int arm7_9_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
439 armv4_5_common_t
*armv4_5
= target
->arch_info
;
440 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
442 if (target
->state
!= TARGET_HALTED
)
444 WARNING("target not halted");
445 return ERROR_TARGET_NOT_HALTED
;
450 arm7_9_unset_watchpoint(target
, watchpoint
);
453 arm7_9
->wp_available
++;
458 int arm7_9_enable_sw_bkpts(struct target_s
*target
)
460 armv4_5_common_t
*armv4_5
= target
->arch_info
;
461 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
464 if (arm7_9
->sw_bkpts_enabled
)
467 if (arm7_9
->wp_available
< 1)
469 WARNING("can't enable sw breakpoints with no watchpoint unit available");
470 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
472 arm7_9
->wp_available
--;
474 if (!arm7_9
->wp0_used
)
476 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
477 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
478 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
479 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
480 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
481 arm7_9
->sw_bkpts_enabled
= 1;
482 arm7_9
->wp0_used
= 3;
484 else if (!arm7_9
->wp1_used
)
486 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
487 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
488 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
489 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
490 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
491 arm7_9
->sw_bkpts_enabled
= 2;
492 arm7_9
->wp1_used
= 3;
496 ERROR("BUG: both watchpoints used, but wp_available >= 1");
500 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
502 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
509 int arm7_9_disable_sw_bkpts(struct target_s
*target
)
511 armv4_5_common_t
*armv4_5
= target
->arch_info
;
512 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
514 if (!arm7_9
->sw_bkpts_enabled
)
517 if (arm7_9
->sw_bkpts_enabled
== 1)
519 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
520 arm7_9
->sw_bkpts_enabled
= 0;
521 arm7_9
->wp0_used
= 0;
522 arm7_9
->wp_available
++;
524 else if (arm7_9
->sw_bkpts_enabled
== 2)
526 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
527 arm7_9
->sw_bkpts_enabled
= 0;
528 arm7_9
->wp1_used
= 0;
529 arm7_9
->wp_available
++;
535 int arm7_9_execute_sys_speed(struct target_s
*target
)
540 armv4_5_common_t
*armv4_5
= target
->arch_info
;
541 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
542 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
543 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
545 /* set RESTART instruction */
546 jtag_add_end_state(TAP_RTI
);
547 arm_jtag_set_instr(jtag_info
, 0x4);
549 for (timeout
=0; timeout
<50; timeout
++)
551 /* read debug status register */
552 embeddedice_read_reg(dbg_stat
);
553 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
555 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
556 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
562 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
563 return ERROR_TARGET_TIMEOUT
;
569 int arm7_9_execute_fast_sys_speed(struct target_s
*target
)
571 u8 check_value
[4], check_mask
[4];
573 armv4_5_common_t
*armv4_5
= target
->arch_info
;
574 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
575 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
576 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
578 /* set RESTART instruction */
579 jtag_add_end_state(TAP_RTI
);
580 arm_jtag_set_instr(jtag_info
, 0x4);
582 /* check for DBGACK and SYSCOMP set (others don't care) */
583 buf_set_u32(check_value
, 0, 32, 0x9);
584 buf_set_u32(check_mask
, 0, 32, 0x9);
586 /* read debug status register */
587 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_value
);
592 enum target_state
arm7_9_poll(target_t
*target
)
595 armv4_5_common_t
*armv4_5
= target
->arch_info
;
596 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
597 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
599 if (arm7_9
->reinit_embeddedice
)
601 arm7_9_reinit_embeddedice(target
);
604 /* read debug status register */
605 embeddedice_read_reg(dbg_stat
);
606 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
610 case ERROR_JTAG_QUEUE_FAILED
:
611 ERROR("JTAG queue failed while reading EmbeddedICE status register");
619 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
621 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat
->value
, 0, 32));
622 if ((target
->state
== TARGET_UNKNOWN
))
624 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
625 target
->state
= TARGET_RUNNING
;
627 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
629 target
->state
= TARGET_HALTED
;
630 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
633 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
635 if (target
->state
== TARGET_DEBUG_RUNNING
)
637 target
->state
= TARGET_HALTED
;
638 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
641 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
646 if (target
->state
!= TARGET_DEBUG_RUNNING
)
647 target
->state
= TARGET_RUNNING
;
650 return target
->state
;
653 int arm7_9_assert_reset(target_t
*target
)
657 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
659 if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_UNKNOWN
)
661 /* if the target wasn't running, there might be working areas allocated */
662 target_free_all_working_areas(target
);
664 /* assert SRST and TRST */
665 /* system would get ouf sync if we didn't reset test-logic, too */
666 if ((retval
= jtag_add_reset(1, 1)) != ERROR_OK
)
668 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
670 WARNING("can't assert srst");
675 ERROR("unknown error");
679 jtag_add_sleep(5000);
680 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
682 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
684 WARNING("srst resets test logic, too");
685 retval
= jtag_add_reset(1, 1);
691 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
693 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
695 WARNING("srst resets test logic, too");
696 retval
= jtag_add_reset(1, 1);
699 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
701 WARNING("can't assert srst");
704 else if (retval
!= ERROR_OK
)
706 ERROR("unknown error");
712 target
->state
= TARGET_RESET
;
713 jtag_add_sleep(50000);
715 armv4_5_invalidate_core_regs(target
);
721 int arm7_9_deassert_reset(target_t
*target
)
723 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
725 /* deassert reset lines */
726 jtag_add_reset(0, 0);
732 int arm7_9_clear_halt(target_t
*target
)
734 armv4_5_common_t
*armv4_5
= target
->arch_info
;
735 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
736 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
738 if (arm7_9
->use_dbgrq
)
740 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
742 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
743 embeddedice_store_reg(dbg_ctrl
);
747 /* restore registers if watchpoint unit 0 was in use
749 if (arm7_9
->wp0_used
)
751 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
752 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
753 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
755 /* control value always has to be restored, as it was either disabled,
756 * or enabled with possibly different bits
758 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
764 int arm7_9_soft_reset_halt(struct target_s
*target
)
766 armv4_5_common_t
*armv4_5
= target
->arch_info
;
767 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
768 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
769 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
772 if (target
->state
== TARGET_RUNNING
)
774 target
->type
->halt(target
);
777 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_CONTROL_DBGACK
, 1) == 0)
779 embeddedice_read_reg(dbg_stat
);
780 jtag_execute_queue();
782 target
->state
= TARGET_HALTED
;
784 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
785 * ensure that DBGRQ is cleared
787 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
788 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
789 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
790 embeddedice_store_reg(dbg_ctrl
);
792 arm7_9_clear_halt(target
);
794 /* if the target is in Thumb state, change to ARM state */
795 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
797 u32 r0_thumb
, pc_thumb
;
798 DEBUG("target entered debug from Thumb state, changing to ARM");
799 /* Entered debug from Thumb mode */
800 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
801 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
804 /* all register content is now invalid */
805 armv4_5_invalidate_core_regs(target
);
807 /* SVC, ARM state, IRQ and FIQ disabled */
808 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
809 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
810 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
812 /* start fetching from 0x0 */
813 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
814 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
815 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
817 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
818 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
820 /* reset registers */
821 for (i
= 0; i
<= 14; i
++)
823 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
824 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
825 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
828 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
833 int arm7_9_halt(target_t
*target
)
835 armv4_5_common_t
*armv4_5
= target
->arch_info
;
836 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
837 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
839 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
841 if (target
->state
== TARGET_HALTED
)
843 WARNING("target was already halted");
844 return ERROR_TARGET_ALREADY_HALTED
;
847 if (target
->state
== TARGET_UNKNOWN
)
849 WARNING("target was in unknown state when halt was requested");
852 if ((target
->state
== TARGET_RESET
) && (jtag_reset_config
& RESET_SRST_PULLS_TRST
) && (jtag_srst
))
854 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
855 return ERROR_TARGET_FAILURE
;
858 if (arm7_9
->use_dbgrq
)
860 /* program EmbeddedICE Debug Control Register to assert DBGRQ
862 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
863 embeddedice_store_reg(dbg_ctrl
);
867 /* program watchpoint unit to match on any address
869 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
870 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
871 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
872 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
875 target
->debug_reason
= DBG_REASON_DBGRQ
;
880 int arm7_9_debug_entry(target_t
*target
)
885 u32 r0_thumb
, pc_thumb
;
888 /* get pointers to arch-specific information */
889 armv4_5_common_t
*armv4_5
= target
->arch_info
;
890 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
891 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
892 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
894 #ifdef _DEBUG_ARM7_9_
898 if (arm7_9
->pre_debug_entry
)
899 arm7_9
->pre_debug_entry(target
);
901 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
902 * ensure that DBGRQ is cleared
904 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
905 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
906 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
907 embeddedice_store_reg(dbg_ctrl
);
909 arm7_9_clear_halt(target
);
911 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
915 case ERROR_JTAG_QUEUE_FAILED
:
916 ERROR("JTAG queue failed while writing EmbeddedICE control register");
924 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
928 if (target
->state
!= TARGET_HALTED
)
930 WARNING("target not halted");
931 return ERROR_TARGET_NOT_HALTED
;
934 /* if the target is in Thumb state, change to ARM state */
935 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
937 DEBUG("target entered debug from Thumb state");
938 /* Entered debug from Thumb mode */
939 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
940 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
941 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb
, pc_thumb
);
945 DEBUG("target entered debug from ARM state");
946 /* Entered debug from ARM mode */
947 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
950 for (i
= 0; i
< 16; i
++)
951 context_p
[i
] = &context
[i
];
952 /* save core registers (r0 - r15 of current core mode) */
953 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
955 arm7_9
->read_xpsr(target
, &cpsr
, 0);
957 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
960 /* if the core has been executing in Thumb state, set the T bit */
961 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
964 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
965 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
966 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
968 armv4_5
->core_mode
= cpsr
& 0x1f;
970 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
972 target
->state
= TARGET_UNKNOWN
;
973 ERROR("cpsr contains invalid mode value - communication failure");
974 return ERROR_TARGET_FAILURE
;
977 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
979 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
981 DEBUG("thumb state, applying fixups");
982 context
[0] = r0_thumb
;
983 context
[15] = pc_thumb
;
984 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
986 /* adjust value stored by STM */
987 context
[15] -= 3 * 4;
990 if ((target
->debug_reason
== DBG_REASON_BREAKPOINT
)
991 || (target
->debug_reason
== DBG_REASON_SINGLESTEP
)
992 || (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
993 || (target
->debug_reason
== DBG_REASON_WPTANDBKPT
)
994 || ((target
->debug_reason
== DBG_REASON_DBGRQ
) && (arm7_9
->use_dbgrq
== 0)))
995 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
996 else if (target
->debug_reason
== DBG_REASON_DBGRQ
)
997 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1000 ERROR("unknown debug reason: %i", target
->debug_reason
);
1004 for (i
=0; i
<=15; i
++)
1006 DEBUG("r%i: 0x%8.8x", i
, context
[i
]);
1007 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1008 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1009 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1012 DEBUG("entered debug state at PC 0x%x", context
[15]);
1014 /* exceptions other than USR & SYS have a saved program status register */
1015 if ((armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_USR
) && (armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_SYS
))
1018 arm7_9
->read_xpsr(target
, &spsr
, 1);
1019 jtag_execute_queue();
1020 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1021 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1022 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1025 /* r0 and r15 (pc) have to be restored later */
1026 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
1027 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= 1;
1029 if ((retval
= jtag
->execute_queue()) != ERROR_OK
)
1032 if (arm7_9
->post_debug_entry
)
1033 arm7_9
->post_debug_entry(target
);
1038 int arm7_9_full_context(target_t
*target
)
1042 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1043 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1047 if (target
->state
!= TARGET_HALTED
)
1049 WARNING("target not halted");
1050 return ERROR_TARGET_NOT_HALTED
;
1053 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1054 * SYS shares registers with User, so we don't touch SYS
1056 for(i
= 0; i
< 6; i
++)
1063 /* check if there are invalid registers in the current mode
1065 for (j
= 0; j
<= 16; j
++)
1067 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1075 /* change processor mode (and mask T bit) */
1076 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1077 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1079 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1081 for (j
= 0; j
< 15; j
++)
1083 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1085 reg_p
[j
] = (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1087 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1088 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1092 /* if only the PSR is invalid, mask is all zeroes */
1094 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1096 /* check if the PSR has to be read */
1097 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1099 arm7_9
->read_xpsr(target
, (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1100 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1101 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1106 /* restore processor mode (mask T bit) */
1107 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1109 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1111 ERROR("JTAG failure");
1117 int arm7_9_restore_context(target_t
*target
)
1119 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1120 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1122 armv4_5_core_reg_t
*reg_arch_info
;
1123 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1130 if (target
->state
!= TARGET_HALTED
)
1132 WARNING("target not halted");
1133 return ERROR_TARGET_NOT_HALTED
;
1136 if (arm7_9
->pre_restore_context
)
1137 arm7_9
->pre_restore_context(target
);
1139 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1140 * SYS shares registers with User, so we don't touch SYS
1142 for (i
= 0; i
< 6; i
++)
1144 DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1147 /* check if there are dirty registers in the current mode
1149 for (j
= 0; j
<= 16; j
++)
1151 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1152 reg_arch_info
= reg
->arch_info
;
1153 if (reg
->dirty
== 1)
1155 if (reg
->valid
== 1)
1158 DEBUG("examining dirty reg: %s", reg
->name
);
1159 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1160 && (reg_arch_info
->mode
!= current_mode
)
1161 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1162 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1165 DEBUG("require mode change");
1170 ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1186 /* change processor mode (mask T bit) */
1187 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1188 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1190 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1191 current_mode
= armv4_5_number_to_mode(i
);
1194 for (j
= 0; j
<= 14; j
++)
1196 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1197 reg_arch_info
= reg
->arch_info
;
1200 if (reg
->dirty
== 1)
1202 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1207 DEBUG("writing register %i of mode %s with value 0x%8.8x", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1213 arm7_9
->write_core_regs(target
, mask
, regs
);
1216 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1217 reg_arch_info
= reg
->arch_info
;
1218 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1220 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i
, buf_get_u32(reg
->value
, 0, 32));
1221 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1226 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1228 /* restore processor mode (mask T bit) */
1231 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1232 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1234 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr
);
1235 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1237 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1239 /* CPSR has been changed, full restore necessary (mask T bit) */
1240 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1241 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1242 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1243 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1247 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1248 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1249 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1251 if (arm7_9
->post_restore_context
)
1252 arm7_9
->post_restore_context(target
);
1257 int arm7_9_restart_core(struct target_s
*target
)
1259 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1260 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1261 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
1263 /* set RESTART instruction */
1264 jtag_add_end_state(TAP_RTI
);
1265 arm_jtag_set_instr(jtag_info
, 0x4);
1267 jtag_add_runtest(1, TAP_RTI
);
1268 if ((jtag_execute_queue()) != ERROR_OK
)
1276 void arm7_9_enable_watchpoints(struct target_s
*target
)
1278 watchpoint_t
*watchpoint
= target
->watchpoints
;
1282 if (watchpoint
->set
== 0)
1283 arm7_9_set_watchpoint(target
, watchpoint
);
1284 watchpoint
= watchpoint
->next
;
1288 void arm7_9_enable_breakpoints(struct target_s
*target
)
1290 breakpoint_t
*breakpoint
= target
->breakpoints
;
1292 /* set any pending breakpoints */
1295 if (breakpoint
->set
== 0)
1296 arm7_9_set_breakpoint(target
, breakpoint
);
1297 breakpoint
= breakpoint
->next
;
1301 void arm7_9_disable_bkpts_and_wpts(struct target_s
*target
)
1303 breakpoint_t
*breakpoint
= target
->breakpoints
;
1304 watchpoint_t
*watchpoint
= target
->watchpoints
;
1306 /* set any pending breakpoints */
1309 if (breakpoint
->set
!= 0)
1310 arm7_9_unset_breakpoint(target
, breakpoint
);
1311 breakpoint
= breakpoint
->next
;
1316 if (watchpoint
->set
!= 0)
1317 arm7_9_unset_watchpoint(target
, watchpoint
);
1318 watchpoint
= watchpoint
->next
;
1322 int arm7_9_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1324 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1325 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1326 breakpoint_t
*breakpoint
= target
->breakpoints
;
1327 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1331 if (target
->state
!= TARGET_HALTED
)
1333 WARNING("target not halted");
1334 return ERROR_TARGET_NOT_HALTED
;
1337 if (!debug_execution
)
1339 target_free_all_working_areas(target
);
1342 /* current = 1: continue on current pc, otherwise continue at <address> */
1344 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1346 /* the front-end may request us not to handle breakpoints */
1347 if (handle_breakpoints
)
1349 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1351 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1352 arm7_9_unset_breakpoint(target
, breakpoint
);
1354 DEBUG("enable single-step");
1355 arm7_9
->enable_single_step(target
);
1357 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1359 arm7_9_restore_context(target
);
1361 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1362 arm7_9
->branch_resume(target
);
1363 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1365 arm7_9
->branch_resume_thumb(target
);
1369 ERROR("unhandled core state");
1373 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1374 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1375 arm7_9_execute_sys_speed(target
);
1377 DEBUG("disable single-step");
1378 arm7_9
->disable_single_step(target
);
1380 arm7_9_debug_entry(target
);
1381 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1383 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1384 arm7_9_set_breakpoint(target
, breakpoint
);
1388 /* enable any pending breakpoints and watchpoints */
1389 arm7_9_enable_breakpoints(target
);
1390 arm7_9_enable_watchpoints(target
);
1392 arm7_9_restore_context(target
);
1394 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1396 arm7_9
->branch_resume(target
);
1398 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1400 arm7_9
->branch_resume_thumb(target
);
1404 ERROR("unhandled core state");
1408 /* deassert DBGACK and INTDIS */
1409 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1410 /* INTDIS only when we really resume, not during debug execution */
1411 if (!debug_execution
)
1412 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1413 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1415 arm7_9_restart_core(target
);
1417 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1419 if (!debug_execution
)
1421 /* registers are now invalid */
1422 armv4_5_invalidate_core_regs(target
);
1423 target
->state
= TARGET_RUNNING
;
1424 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1428 target
->state
= TARGET_DEBUG_RUNNING
;
1429 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1432 DEBUG("target resumed");
1437 void arm7_9_enable_eice_step(target_t
*target
)
1439 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1440 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1442 /* setup an inverse breakpoint on the current PC
1443 * - comparator 1 matches the current address
1444 * - rangeout from comparator 1 is connected to comparator 0 rangein
1445 * - comparator 0 matches any address, as long as rangein is low */
1446 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1447 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1448 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1449 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0x77);
1450 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1451 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1452 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1453 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1454 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xf7);
1457 void arm7_9_disable_eice_step(target_t
*target
)
1459 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1460 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1462 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1463 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1464 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1465 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1466 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1467 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1468 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1469 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1470 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1473 int arm7_9_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1475 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1476 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1477 breakpoint_t
*breakpoint
= NULL
;
1479 if (target
->state
!= TARGET_HALTED
)
1481 WARNING("target not halted");
1482 return ERROR_TARGET_NOT_HALTED
;
1485 /* current = 1: continue on current pc, otherwise continue at <address> */
1487 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1489 /* the front-end may request us not to handle breakpoints */
1490 if (handle_breakpoints
)
1491 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1492 arm7_9_unset_breakpoint(target
, breakpoint
);
1494 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1496 arm7_9_restore_context(target
);
1498 arm7_9
->enable_single_step(target
);
1500 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1502 arm7_9
->branch_resume(target
);
1504 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1506 arm7_9
->branch_resume_thumb(target
);
1510 ERROR("unhandled core state");
1514 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1516 arm7_9_execute_sys_speed(target
);
1517 arm7_9
->disable_single_step(target
);
1519 /* registers are now invalid */
1520 armv4_5_invalidate_core_regs(target
);
1522 arm7_9_debug_entry(target
);
1524 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1527 arm7_9_set_breakpoint(target
, breakpoint
);
1529 DEBUG("target stepped");
1535 int arm7_9_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1540 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1541 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1542 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1544 if ((num
< 0) || (num
> 16))
1545 return ERROR_INVALID_ARGUMENTS
;
1547 if ((mode
!= ARMV4_5_MODE_ANY
)
1548 && (mode
!= armv4_5
->core_mode
)
1549 && (reg_mode
!= ARMV4_5_MODE_ANY
))
1553 /* change processor mode (mask T bit) */
1554 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1557 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1560 if ((num
>= 0) && (num
<= 15))
1562 /* read a normal core register */
1563 reg_p
[num
] = &value
;
1565 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
1569 /* read a program status register
1570 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1572 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1573 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1575 arm7_9
->read_xpsr(target
, &value
, spsr
);
1578 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1580 ERROR("JTAG failure");
1584 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1585 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1586 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
1588 if ((mode
!= ARMV4_5_MODE_ANY
)
1589 && (mode
!= armv4_5
->core_mode
)
1590 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1591 /* restore processor mode (mask T bit) */
1592 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1599 int arm7_9_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1603 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1604 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1605 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1607 if ((num
< 0) || (num
> 16))
1608 return ERROR_INVALID_ARGUMENTS
;
1610 if ((mode
!= ARMV4_5_MODE_ANY
)
1611 && (mode
!= armv4_5
->core_mode
)
1612 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1615 /* change processor mode (mask T bit) */
1616 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1619 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1622 if ((num
>= 0) && (num
<= 15))
1624 /* write a normal core register */
1627 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
1631 /* write a program status register
1632 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1634 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1635 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1637 /* if we're writing the CPSR, mask the T bit */
1641 arm7_9
->write_xpsr(target
, value
, spsr
);
1644 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1645 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1647 if ((mode
!= ARMV4_5_MODE_ANY
)
1648 && (mode
!= armv4_5
->core_mode
)
1649 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1650 /* restore processor mode (mask T bit) */
1651 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1654 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1656 ERROR("JTAG failure");
1664 int arm7_9_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1666 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1667 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1670 int num_accesses
= 0;
1671 int thisrun_accesses
;
1677 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1679 if (target
->state
!= TARGET_HALTED
)
1681 WARNING("target not halted");
1682 return ERROR_TARGET_NOT_HALTED
;
1685 /* sanitize arguments */
1686 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1687 return ERROR_INVALID_ARGUMENTS
;
1689 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1690 return ERROR_TARGET_UNALIGNED_ACCESS
;
1692 /* load the base register with the address of the first word */
1694 arm7_9
->write_core_regs(target
, 0x1, reg
);
1699 while (num_accesses
< count
)
1702 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1703 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1705 if (last_reg
<= thisrun_accesses
)
1706 last_reg
= thisrun_accesses
;
1708 arm7_9
->load_word_regs(target
, reg_list
);
1710 /* fast memory reads are only safe when the target is running
1711 * from a sufficiently high clock (32 kHz is usually too slow)
1713 if (arm7_9
->fast_memory_access
)
1714 arm7_9_execute_fast_sys_speed(target
);
1716 arm7_9_execute_sys_speed(target
);
1718 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
1720 /* advance buffer, count number of accesses */
1721 buffer
+= thisrun_accesses
* 4;
1722 num_accesses
+= thisrun_accesses
;
1726 while (num_accesses
< count
)
1729 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1730 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1732 for (i
= 1; i
<= thisrun_accesses
; i
++)
1736 arm7_9
->load_hword_reg(target
, i
);
1737 /* fast memory reads are only safe when the target is running
1738 * from a sufficiently high clock (32 kHz is usually too slow)
1740 if (arm7_9
->fast_memory_access
)
1741 arm7_9_execute_fast_sys_speed(target
);
1743 arm7_9_execute_sys_speed(target
);
1746 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
1748 /* advance buffer, count number of accesses */
1749 buffer
+= thisrun_accesses
* 2;
1750 num_accesses
+= thisrun_accesses
;
1754 while (num_accesses
< count
)
1757 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1758 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1760 for (i
= 1; i
<= thisrun_accesses
; i
++)
1764 arm7_9
->load_byte_reg(target
, i
);
1765 /* fast memory reads are only safe when the target is running
1766 * from a sufficiently high clock (32 kHz is usually too slow)
1768 if (arm7_9
->fast_memory_access
)
1769 arm7_9_execute_fast_sys_speed(target
);
1771 arm7_9_execute_sys_speed(target
);
1774 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
1776 /* advance buffer, count number of accesses */
1777 buffer
+= thisrun_accesses
* 1;
1778 num_accesses
+= thisrun_accesses
;
1782 ERROR("BUG: we shouldn't get here");
1787 for (i
=0; i
<=last_reg
; i
++)
1788 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1790 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1791 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1793 ERROR("JTAG error while reading cpsr");
1797 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1799 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1801 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1803 return ERROR_TARGET_DATA_ABORT
;
1809 int arm7_9_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1811 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1812 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1813 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1816 int num_accesses
= 0;
1817 int thisrun_accesses
;
1823 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1825 if (target
->state
!= TARGET_HALTED
)
1827 WARNING("target not halted");
1828 return ERROR_TARGET_NOT_HALTED
;
1831 /* sanitize arguments */
1832 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1833 return ERROR_INVALID_ARGUMENTS
;
1835 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1836 return ERROR_TARGET_UNALIGNED_ACCESS
;
1838 /* load the base register with the address of the first word */
1840 arm7_9
->write_core_regs(target
, 0x1, reg
);
1842 /* Clear DBGACK, to make sure memory fetches work as expected */
1843 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1844 embeddedice_store_reg(dbg_ctrl
);
1849 while (num_accesses
< count
)
1852 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1853 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1855 for (i
= 1; i
<= thisrun_accesses
; i
++)
1859 reg
[i
] = target_buffer_get_u32(target
, buffer
);
1863 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1865 arm7_9
->store_word_regs(target
, reg_list
);
1867 /* fast memory writes are only safe when the target is running
1868 * from a sufficiently high clock (32 kHz is usually too slow)
1870 if (arm7_9
->fast_memory_access
)
1871 arm7_9_execute_fast_sys_speed(target
);
1873 arm7_9_execute_sys_speed(target
);
1875 num_accesses
+= thisrun_accesses
;
1879 while (num_accesses
< count
)
1882 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1883 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1885 for (i
= 1; i
<= thisrun_accesses
; i
++)
1889 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
1893 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1895 for (i
= 1; i
<= thisrun_accesses
; i
++)
1897 arm7_9
->store_hword_reg(target
, i
);
1899 /* fast memory writes are only safe when the target is running
1900 * from a sufficiently high clock (32 kHz is usually too slow)
1902 if (arm7_9
->fast_memory_access
)
1903 arm7_9_execute_fast_sys_speed(target
);
1905 arm7_9_execute_sys_speed(target
);
1908 num_accesses
+= thisrun_accesses
;
1912 while (num_accesses
< count
)
1915 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1916 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1918 for (i
= 1; i
<= thisrun_accesses
; i
++)
1922 reg
[i
] = *buffer
++ & 0xff;
1925 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1927 for (i
= 1; i
<= thisrun_accesses
; i
++)
1929 arm7_9
->store_byte_reg(target
, i
);
1930 /* fast memory writes are only safe when the target is running
1931 * from a sufficiently high clock (32 kHz is usually too slow)
1933 if (arm7_9
->fast_memory_access
)
1934 arm7_9_execute_fast_sys_speed(target
);
1936 arm7_9_execute_sys_speed(target
);
1939 num_accesses
+= thisrun_accesses
;
1943 ERROR("BUG: we shouldn't get here");
1949 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1950 embeddedice_store_reg(dbg_ctrl
);
1952 for (i
=0; i
<=last_reg
; i
++)
1953 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1955 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1956 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1958 ERROR("JTAG error while reading cpsr");
1962 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1964 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1966 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1968 return ERROR_TARGET_DATA_ABORT
;
1974 int arm7_9_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
1976 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1977 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1978 enum armv4_5_state core_state
= armv4_5
->core_state
;
1979 u32 r0
= buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32);
1980 u32 r1
= buf_get_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32);
1981 u32 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1986 /* MRC TST BNE MRC STR B */
1987 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1990 if (!arm7_9
->dcc_downloads
)
1991 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
1993 /* regrab previously allocated working_area, or allocate a new one */
1994 if (!arm7_9
->dcc_working_area
)
1996 u8 dcc_code_buf
[6 * 4];
1998 /* make sure we have a working area */
1999 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2001 INFO("no working area available, falling back to memory writes");
2002 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2005 /* copy target instructions to target endianness */
2006 for (i
= 0; i
< 6; i
++)
2008 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2011 /* write DCC code to working area */
2012 target
->type
->write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
);
2015 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, address
);
2016 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2017 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2018 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
2020 arm7_9_resume(target
, 0, arm7_9
->dcc_working_area
->address
, 1, 1);
2022 for (i
= 0; i
< count
; i
++)
2024 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], target_buffer_get_u32(target
, buffer
));
2028 target
->type
->halt(target
);
2030 while (target
->state
!= TARGET_HALTED
)
2031 target
->type
->poll(target
);
2033 /* restore target state */
2034 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, r0
);
2035 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2036 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2037 buf_set_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32, r1
);
2038 armv4_5
->core_cache
->reg_list
[1].valid
= 1;
2039 armv4_5
->core_cache
->reg_list
[1].dirty
= 1;
2040 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
2041 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
2042 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
2043 armv4_5
->core_state
= core_state
;
2048 int arm7_9_register_commands(struct command_context_s
*cmd_ctx
)
2050 command_t
*arm7_9_cmd
;
2052 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9", NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2054 register_command(cmd_ctx
, arm7_9_cmd
, "etm", handle_arm7_9_etm_command
, COMMAND_CONFIG
, NULL
);
2056 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr", handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
, "write program status register <value> <not cpsr|spsr>");
2057 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2059 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg", handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
, "write core register <num> <mode> <value>");
2061 register_command(cmd_ctx
, arm7_9_cmd
, "sw_bkpts", handle_arm7_9_sw_bkpts_command
, COMMAND_EXEC
, "support for software breakpoints <enable|disable>");
2062 register_command(cmd_ctx
, arm7_9_cmd
, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command
, COMMAND_EXEC
, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2063 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq", handle_arm7_9_dbgrq_command
,
2064 COMMAND_ANY
, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2065 register_command(cmd_ctx
, arm7_9_cmd
, "fast_writes", handle_arm7_9_fast_memory_access_command
,
2066 COMMAND_ANY
, "(deprecated, see: arm7_9 fast_memory_access)");
2067 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access", handle_arm7_9_fast_memory_access_command
,
2068 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2069 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads", handle_arm7_9_dcc_downloads_command
,
2070 COMMAND_ANY
, "use DCC downloads for larger memory writes <enable|disable>");
2072 armv4_5_register_commands(cmd_ctx
);
2077 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2082 target_t
*target
= get_current_target(cmd_ctx
);
2083 armv4_5_common_t
*armv4_5
;
2084 arm7_9_common_t
*arm7_9
;
2086 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2088 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2092 if (target
->state
!= TARGET_HALTED
)
2094 command_print(cmd_ctx
, "can't write registers while running");
2100 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr|spsr>");
2104 value
= strtoul(args
[0], NULL
, 0);
2105 spsr
= strtol(args
[1], NULL
, 0);
2107 /* if we're writing the CPSR, mask the T bit */
2111 arm7_9
->write_xpsr(target
, value
, spsr
);
2112 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2114 ERROR("JTAG error while writing to xpsr");
2121 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2127 target_t
*target
= get_current_target(cmd_ctx
);
2128 armv4_5_common_t
*armv4_5
;
2129 arm7_9_common_t
*arm7_9
;
2131 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2133 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2137 if (target
->state
!= TARGET_HALTED
)
2139 command_print(cmd_ctx
, "can't write registers while running");
2145 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2149 value
= strtoul(args
[0], NULL
, 0);
2150 rotate
= strtol(args
[1], NULL
, 0);
2151 spsr
= strtol(args
[2], NULL
, 0);
2153 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2154 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2156 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2163 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2168 target_t
*target
= get_current_target(cmd_ctx
);
2169 armv4_5_common_t
*armv4_5
;
2170 arm7_9_common_t
*arm7_9
;
2172 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2174 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2178 if (target
->state
!= TARGET_HALTED
)
2180 command_print(cmd_ctx
, "can't write registers while running");
2186 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
2190 num
= strtol(args
[0], NULL
, 0);
2191 mode
= strtoul(args
[1], NULL
, 0);
2192 value
= strtoul(args
[2], NULL
, 0);
2194 arm7_9_write_core_reg(target
, num
, mode
, value
);
2199 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2201 target_t
*target
= get_current_target(cmd_ctx
);
2202 armv4_5_common_t
*armv4_5
;
2203 arm7_9_common_t
*arm7_9
;
2205 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2207 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2213 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2217 if (strcmp("enable", args
[0]) == 0)
2219 if (arm7_9
->sw_bkpts_use_wp
)
2221 arm7_9_enable_sw_bkpts(target
);
2225 arm7_9
->sw_bkpts_enabled
= 1;
2228 else if (strcmp("disable", args
[0]) == 0)
2230 if (arm7_9
->sw_bkpts_use_wp
)
2232 arm7_9_disable_sw_bkpts(target
);
2236 arm7_9
->sw_bkpts_enabled
= 0;
2241 command_print(cmd_ctx
, "usage: arm7_9 sw_bkpts <enable|disable>");
2244 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2249 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2251 target_t
*target
= get_current_target(cmd_ctx
);
2252 armv4_5_common_t
*armv4_5
;
2253 arm7_9_common_t
*arm7_9
;
2255 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2257 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2261 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
2263 arm7_9
->force_hw_bkpts
= 1;
2264 if (arm7_9
->sw_bkpts_use_wp
)
2266 arm7_9_disable_sw_bkpts(target
);
2269 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
2271 arm7_9
->force_hw_bkpts
= 0;
2275 command_print(cmd_ctx
, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2278 command_print(cmd_ctx
, "force hardware breakpoints %s", (arm7_9
->force_hw_bkpts
) ? "enabled" : "disabled");
2283 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2285 target_t
*target
= get_current_target(cmd_ctx
);
2286 armv4_5_common_t
*armv4_5
;
2287 arm7_9_common_t
*arm7_9
;
2289 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2291 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2297 if (strcmp("enable", args
[0]) == 0)
2299 arm7_9
->use_dbgrq
= 1;
2301 else if (strcmp("disable", args
[0]) == 0)
2303 arm7_9
->use_dbgrq
= 0;
2307 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable|disable>");
2311 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2316 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2318 target_t
*target
= get_current_target(cmd_ctx
);
2319 armv4_5_common_t
*armv4_5
;
2320 arm7_9_common_t
*arm7_9
;
2322 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2324 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2330 if (strcmp("enable", args
[0]) == 0)
2332 arm7_9
->fast_memory_access
= 1;
2334 else if (strcmp("disable", args
[0]) == 0)
2336 arm7_9
->fast_memory_access
= 0;
2340 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable|disable>");
2344 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2349 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2351 target_t
*target
= get_current_target(cmd_ctx
);
2352 armv4_5_common_t
*armv4_5
;
2353 arm7_9_common_t
*arm7_9
;
2355 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2357 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2363 if (strcmp("enable", args
[0]) == 0)
2365 arm7_9
->dcc_downloads
= 1;
2367 else if (strcmp("disable", args
[0]) == 0)
2369 arm7_9
->dcc_downloads
= 0;
2373 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable|disable>");
2377 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2382 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2385 armv4_5_common_t
*armv4_5
;
2386 arm7_9_common_t
*arm7_9
;
2390 ERROR("incomplete 'arm7_9 etm <target>' command");
2394 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
2398 ERROR("target number '%s' not defined", args
[0]);
2402 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2404 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2408 arm7_9
->has_etm
= 1;
2413 int arm7_9_init_arch_info(target_t
*target
, arm7_9_common_t
*arm7_9
)
2415 armv4_5_common_t
*armv4_5
= &arm7_9
->armv4_5_common
;
2417 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2419 arm_jtag_setup_connection(&arm7_9
->jtag_info
);
2420 arm7_9
->wp_available
= 2;
2421 arm7_9
->wp0_used
= 0;
2422 arm7_9
->wp1_used
= 0;
2423 arm7_9
->force_hw_bkpts
= 0;
2424 arm7_9
->use_dbgrq
= 0;
2426 arm7_9
->has_etm
= 0;
2427 arm7_9
->has_single_step
= 0;
2428 arm7_9
->has_monitor_mode
= 0;
2429 arm7_9
->has_vector_catch
= 0;
2431 arm7_9
->reinit_embeddedice
= 0;
2433 arm7_9
->dcc_working_area
= NULL
;
2435 arm7_9
->fast_memory_access
= 0;
2436 arm7_9
->dcc_downloads
= 0;
2438 jtag_register_event_callback(arm7_9_jtag_callback
, target
);
2440 armv4_5
->arch_info
= arm7_9
;
2441 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2442 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2443 armv4_5
->full_context
= arm7_9_full_context
;
2445 armv4_5_init_arch_info(target
, armv4_5
);
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