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allow minidrivers to implement inner loop of dcc memory writes
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "embeddedice.h"
30 #include "target.h"
31 #include "target_request.h"
32 #include "armv4_5.h"
33 #include "arm_jtag.h"
34 #include "jtag.h"
35 #include "log.h"
36 #include "arm7_9_common.h"
37 #include "breakpoints.h"
38
39 #include <stdlib.h>
40 #include <string.h>
41 #include <unistd.h>
42
43 #include <sys/types.h>
44 #include <sys/stat.h>
45 #include <sys/time.h>
46 #include <errno.h>
47
48 int arm7_9_debug_entry(target_t *target);
49 int arm7_9_enable_sw_bkpts(struct target_s *target);
50
51 /* command handler forward declarations */
52 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
60 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
61 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
62
63 int arm7_9_reinit_embeddedice(target_t *target)
64 {
65 armv4_5_common_t *armv4_5 = target->arch_info;
66 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
67
68 breakpoint_t *breakpoint = target->breakpoints;
69
70 arm7_9->wp_available = 2;
71 arm7_9->wp0_used = 0;
72 arm7_9->wp1_used = 0;
73
74 /* mark all hardware breakpoints as unset */
75 while (breakpoint)
76 {
77 if (breakpoint->type == BKPT_HARD)
78 {
79 breakpoint->set = 0;
80 }
81 breakpoint = breakpoint->next;
82 }
83
84 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
85 {
86 arm7_9->sw_bkpts_enabled = 0;
87 arm7_9_enable_sw_bkpts(target);
88 }
89
90 return ERROR_OK;
91 }
92
93 /* set things up after a reset / on startup */
94 int arm7_9_setup(target_t *target)
95 {
96 /* a test-logic reset have occured
97 * the EmbeddedICE registers have been reset
98 * hardware breakpoints have been cleared
99 */
100 return arm7_9_reinit_embeddedice(target);
101 }
102
103 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
104 {
105 armv4_5_common_t *armv4_5 = target->arch_info;
106 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
107
108 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
109 {
110 return -1;
111 }
112
113 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
114 {
115 return -1;
116 }
117
118 *armv4_5_p = armv4_5;
119 *arm7_9_p = arm7_9;
120
121 return ERROR_OK;
122 }
123
124 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
125 {
126 armv4_5_common_t *armv4_5 = target->arch_info;
127 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
128
129 if (target->state != TARGET_HALTED)
130 {
131 LOG_WARNING("target not halted");
132 return ERROR_TARGET_NOT_HALTED;
133 }
134
135 if (arm7_9->force_hw_bkpts)
136 breakpoint->type = BKPT_HARD;
137
138 if (breakpoint->set)
139 {
140 LOG_WARNING("breakpoint already set");
141 return ERROR_OK;
142 }
143
144 if (breakpoint->type == BKPT_HARD)
145 {
146 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
147 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
148 if (!arm7_9->wp0_used)
149 {
150 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
151 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
152 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
153 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
154 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
155
156 jtag_execute_queue();
157 arm7_9->wp0_used = 1;
158 breakpoint->set = 1;
159 }
160 else if (!arm7_9->wp1_used)
161 {
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
165 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
166 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
167
168 jtag_execute_queue();
169 arm7_9->wp1_used = 1;
170 breakpoint->set = 2;
171 }
172 else
173 {
174 LOG_ERROR("BUG: no hardware comparator available");
175 return ERROR_OK;
176 }
177 }
178 else if (breakpoint->type == BKPT_SOFT)
179 {
180 if (breakpoint->length == 4)
181 {
182 u32 verify = 0xffffffff;
183 /* keep the original instruction in target endianness */
184 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
185 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
186 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
187
188 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
189 if (verify != arm7_9->arm_bkpt)
190 {
191 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
192 return ERROR_OK;
193 }
194 }
195 else
196 {
197 u16 verify = 0xffff;
198 /* keep the original instruction in target endianness */
199 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
200 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
201 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
202
203 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
204 if (verify != arm7_9->thumb_bkpt)
205 {
206 LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
207 return ERROR_OK;
208 }
209 }
210 breakpoint->set = 1;
211 }
212
213 return ERROR_OK;
214
215 }
216
217 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
218 {
219 armv4_5_common_t *armv4_5 = target->arch_info;
220 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
221
222 if (target->state != TARGET_HALTED)
223 {
224 LOG_WARNING("target not halted");
225 return ERROR_TARGET_NOT_HALTED;
226 }
227
228 if (!breakpoint->set)
229 {
230 LOG_WARNING("breakpoint not set");
231 return ERROR_OK;
232 }
233
234 if (breakpoint->type == BKPT_HARD)
235 {
236 if (breakpoint->set == 1)
237 {
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
239 jtag_execute_queue();
240 arm7_9->wp0_used = 0;
241 }
242 else if (breakpoint->set == 2)
243 {
244 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
245 jtag_execute_queue();
246 arm7_9->wp1_used = 0;
247 }
248 breakpoint->set = 0;
249 }
250 else
251 {
252 /* restore original instruction (kept in target endianness) */
253 if (breakpoint->length == 4)
254 {
255 u32 current_instr;
256 /* check that user program as not modified breakpoint instruction */
257 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
258 if (current_instr==arm7_9->arm_bkpt)
259 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
260 }
261 else
262 {
263 u16 current_instr;
264 /* check that user program as not modified breakpoint instruction */
265 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
266 if (current_instr==arm7_9->thumb_bkpt)
267 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
268 }
269 breakpoint->set = 0;
270 }
271
272 return ERROR_OK;
273 }
274
275 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
276 {
277 armv4_5_common_t *armv4_5 = target->arch_info;
278 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
279
280 if (target->state != TARGET_HALTED)
281 {
282 LOG_WARNING("target not halted");
283 return ERROR_TARGET_NOT_HALTED;
284 }
285
286 if (arm7_9->force_hw_bkpts)
287 {
288 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
289 breakpoint->type = BKPT_HARD;
290 }
291
292 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
293 {
294 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
295 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
296 }
297
298 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
299 {
300 LOG_INFO("no watchpoint unit available for hardware breakpoint");
301 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
302 }
303
304 if ((breakpoint->length != 2) && (breakpoint->length != 4))
305 {
306 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
307 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
308 }
309
310 if (breakpoint->type == BKPT_HARD)
311 arm7_9->wp_available--;
312
313 return ERROR_OK;
314 }
315
316 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
317 {
318 armv4_5_common_t *armv4_5 = target->arch_info;
319 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
320
321 if (target->state != TARGET_HALTED)
322 {
323 LOG_WARNING("target not halted");
324 return ERROR_TARGET_NOT_HALTED;
325 }
326
327 if (breakpoint->set)
328 {
329 arm7_9_unset_breakpoint(target, breakpoint);
330 }
331
332 if (breakpoint->type == BKPT_HARD)
333 arm7_9->wp_available++;
334
335 return ERROR_OK;
336 }
337
338 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
339 {
340 armv4_5_common_t *armv4_5 = target->arch_info;
341 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
342 int rw_mask = 1;
343 u32 mask;
344
345 mask = watchpoint->length - 1;
346
347 if (target->state != TARGET_HALTED)
348 {
349 LOG_WARNING("target not halted");
350 return ERROR_TARGET_NOT_HALTED;
351 }
352
353 if (watchpoint->rw == WPT_ACCESS)
354 rw_mask = 0;
355 else
356 rw_mask = 1;
357
358 if (!arm7_9->wp0_used)
359 {
360 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
363 if( watchpoint->mask != 0xffffffffu )
364 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
365 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
366 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
367
368 jtag_execute_queue();
369 watchpoint->set = 1;
370 arm7_9->wp0_used = 2;
371 }
372 else if (!arm7_9->wp1_used)
373 {
374 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
375 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
376 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
377 if( watchpoint->mask != 0xffffffffu )
378 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
379 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
380 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
381
382 jtag_execute_queue();
383 watchpoint->set = 2;
384 arm7_9->wp1_used = 2;
385 }
386 else
387 {
388 LOG_ERROR("BUG: no hardware comparator available");
389 return ERROR_OK;
390 }
391
392 return ERROR_OK;
393 }
394
395 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
396 {
397 armv4_5_common_t *armv4_5 = target->arch_info;
398 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
399
400 if (target->state != TARGET_HALTED)
401 {
402 LOG_WARNING("target not halted");
403 return ERROR_TARGET_NOT_HALTED;
404 }
405
406 if (!watchpoint->set)
407 {
408 LOG_WARNING("breakpoint not set");
409 return ERROR_OK;
410 }
411
412 if (watchpoint->set == 1)
413 {
414 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
415 jtag_execute_queue();
416 arm7_9->wp0_used = 0;
417 }
418 else if (watchpoint->set == 2)
419 {
420 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
421 jtag_execute_queue();
422 arm7_9->wp1_used = 0;
423 }
424 watchpoint->set = 0;
425
426 return ERROR_OK;
427 }
428
429 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
430 {
431 armv4_5_common_t *armv4_5 = target->arch_info;
432 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
433
434 if (target->state != TARGET_HALTED)
435 {
436 LOG_WARNING("target not halted");
437 return ERROR_TARGET_NOT_HALTED;
438 }
439
440 if (arm7_9->wp_available < 1)
441 {
442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
443 }
444
445 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
446 {
447 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
448 }
449
450 arm7_9->wp_available--;
451
452 return ERROR_OK;
453 }
454
455 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
456 {
457 armv4_5_common_t *armv4_5 = target->arch_info;
458 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
459
460 if (target->state != TARGET_HALTED)
461 {
462 LOG_WARNING("target not halted");
463 return ERROR_TARGET_NOT_HALTED;
464 }
465
466 if (watchpoint->set)
467 {
468 arm7_9_unset_watchpoint(target, watchpoint);
469 }
470
471 arm7_9->wp_available++;
472
473 return ERROR_OK;
474 }
475
476 int arm7_9_enable_sw_bkpts(struct target_s *target)
477 {
478 armv4_5_common_t *armv4_5 = target->arch_info;
479 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
480 int retval;
481
482 if (arm7_9->sw_bkpts_enabled)
483 return ERROR_OK;
484
485 if (arm7_9->wp_available < 1)
486 {
487 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
489 }
490 arm7_9->wp_available--;
491
492 if (!arm7_9->wp0_used)
493 {
494 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
495 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
496 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
497 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
498 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
499 arm7_9->sw_bkpts_enabled = 1;
500 arm7_9->wp0_used = 3;
501 }
502 else if (!arm7_9->wp1_used)
503 {
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
506 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
507 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
508 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
509 arm7_9->sw_bkpts_enabled = 2;
510 arm7_9->wp1_used = 3;
511 }
512 else
513 {
514 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
515 return ERROR_FAIL;
516 }
517
518 if ((retval = jtag_execute_queue()) != ERROR_OK)
519 {
520 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
521 return ERROR_FAIL;
522 };
523
524 return ERROR_OK;
525 }
526
527 int arm7_9_disable_sw_bkpts(struct target_s *target)
528 {
529 armv4_5_common_t *armv4_5 = target->arch_info;
530 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
531
532 if (!arm7_9->sw_bkpts_enabled)
533 return ERROR_OK;
534
535 if (arm7_9->sw_bkpts_enabled == 1)
536 {
537 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
538 arm7_9->sw_bkpts_enabled = 0;
539 arm7_9->wp0_used = 0;
540 arm7_9->wp_available++;
541 }
542 else if (arm7_9->sw_bkpts_enabled == 2)
543 {
544 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
545 arm7_9->sw_bkpts_enabled = 0;
546 arm7_9->wp1_used = 0;
547 arm7_9->wp_available++;
548 }
549
550 return ERROR_OK;
551 }
552
553 int arm7_9_execute_sys_speed(struct target_s *target)
554 {
555 int timeout;
556 int retval;
557
558 armv4_5_common_t *armv4_5 = target->arch_info;
559 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
560 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
561 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
562
563 /* set RESTART instruction */
564 jtag_add_end_state(TAP_RTI);
565 if (arm7_9->need_bypass_before_restart) {
566 arm7_9->need_bypass_before_restart = 0;
567 arm_jtag_set_instr(jtag_info, 0xf, NULL);
568 }
569 arm_jtag_set_instr(jtag_info, 0x4, NULL);
570
571 for (timeout=0; timeout<50; timeout++)
572 {
573 /* read debug status register */
574 embeddedice_read_reg(dbg_stat);
575 if ((retval = jtag_execute_queue()) != ERROR_OK)
576 return retval;
577 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
578 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
579 break;
580 usleep(100000);
581 }
582 if (timeout == 50)
583 {
584 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
585 return ERROR_TARGET_TIMEOUT;
586 }
587
588 return ERROR_OK;
589 }
590
591 int arm7_9_execute_fast_sys_speed(struct target_s *target)
592 {
593 static int set=0;
594 static u8 check_value[4], check_mask[4];
595
596 armv4_5_common_t *armv4_5 = target->arch_info;
597 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
598 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
599 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
600
601 /* set RESTART instruction */
602 jtag_add_end_state(TAP_RTI);
603 if (arm7_9->need_bypass_before_restart) {
604 arm7_9->need_bypass_before_restart = 0;
605 arm_jtag_set_instr(jtag_info, 0xf, NULL);
606 }
607 arm_jtag_set_instr(jtag_info, 0x4, NULL);
608
609 if (!set)
610 {
611 /* check for DBGACK and SYSCOMP set (others don't care) */
612
613 /* NB! These are constants that must be available until after next jtag_execute() and
614 we evaluate the values upon first execution in lieu of setting up these constants
615 during early setup.
616 */
617 buf_set_u32(check_value, 0, 32, 0x9);
618 buf_set_u32(check_mask, 0, 32, 0x9);
619 set=1;
620 }
621
622 /* read debug status register */
623 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
624
625 return ERROR_OK;
626 }
627
628 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
629 {
630 armv4_5_common_t *armv4_5 = target->arch_info;
631 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
632 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
633 u32 *data;
634 int i;
635
636 data = malloc(size * (sizeof(u32)));
637
638 embeddedice_receive(jtag_info, data, size);
639
640 for (i = 0; i < size; i++)
641 {
642 h_u32_to_le(buffer + (i * 4), data[i]);
643 }
644
645 free(data);
646
647 return ERROR_OK;
648 }
649
650 int arm7_9_handle_target_request(void *priv)
651 {
652 target_t *target = priv;
653 if (!target->type->examined)
654 return ERROR_OK;
655 armv4_5_common_t *armv4_5 = target->arch_info;
656 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
657 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
658 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
659
660
661 if (!target->dbg_msg_enabled)
662 return ERROR_OK;
663
664 if (target->state == TARGET_RUNNING)
665 {
666 /* read DCC control register */
667 embeddedice_read_reg(dcc_control);
668 jtag_execute_queue();
669
670 /* check W bit */
671 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
672 {
673 u32 request;
674
675 embeddedice_receive(jtag_info, &request, 1);
676 target_request(target, request);
677 }
678 }
679
680 return ERROR_OK;
681 }
682
683 int arm7_9_poll(target_t *target)
684 {
685 int retval;
686 armv4_5_common_t *armv4_5 = target->arch_info;
687 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
688 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
689
690 /* read debug status register */
691 embeddedice_read_reg(dbg_stat);
692 if ((retval = jtag_execute_queue()) != ERROR_OK)
693 {
694 return retval;
695 }
696
697 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
698 {
699 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
700 if (target->state == TARGET_UNKNOWN)
701 {
702 target->state = TARGET_RUNNING;
703 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
704 }
705 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
706 {
707 int check_pc=0;
708 if (target->state == TARGET_RESET)
709 {
710 if (target->reset_halt)
711 {
712 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
713 {
714 check_pc = 1;
715 }
716 }
717 }
718
719 target->state = TARGET_HALTED;
720
721 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
722 return retval;
723
724 if (check_pc)
725 {
726 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
727 u32 t=*((u32 *)reg->value);
728 if (t!=0)
729 {
730 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
731 }
732 }
733
734 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
735 }
736 if (target->state == TARGET_DEBUG_RUNNING)
737 {
738 target->state = TARGET_HALTED;
739 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
740 return retval;
741
742 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
743 }
744 if (target->state != TARGET_HALTED)
745 {
746 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
747 }
748 }
749 else
750 {
751 if (target->state != TARGET_DEBUG_RUNNING)
752 target->state = TARGET_RUNNING;
753 }
754
755 return ERROR_OK;
756 }
757
758 /*
759 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
760 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
761 while the core is held in reset(SRST). It isn't possible to program the halt
762 condition once reset was asserted, hence a hook that allows the target to set
763 up its reset-halt condition prior to asserting reset.
764 */
765
766 int arm7_9_assert_reset(target_t *target)
767 {
768 armv4_5_common_t *armv4_5 = target->arch_info;
769 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
770 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
771
772 if (!(jtag_reset_config & RESET_HAS_SRST))
773 {
774 LOG_ERROR("Can't assert SRST");
775 return ERROR_FAIL;
776 }
777
778 if (target->reset_halt)
779 {
780 /*
781 * Some targets do not support communication while SRST is asserted. We need to
782 * set up the reset vector catch here.
783 *
784 * If TRST is asserted, then these settings will be reset anyway, so setting them
785 * here is harmless.
786 */
787 if (arm7_9->has_vector_catch)
788 {
789 /* program vector catch register to catch reset vector */
790 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
791 }
792 else
793 {
794 /* program watchpoint unit to match on reset vector address */
795 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
796 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
797 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
798 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
799 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
800 }
801 }
802
803 /* here we should issue a srst only, but we may have to assert trst as well */
804 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
805 {
806 jtag_add_reset(1, 1);
807 } else
808 {
809 jtag_add_reset(0, 1);
810 }
811
812
813 target->state = TARGET_RESET;
814 jtag_add_sleep(50000);
815
816 armv4_5_invalidate_core_regs(target);
817
818 return ERROR_OK;
819
820 }
821
822 int arm7_9_deassert_reset(target_t *target)
823 {
824 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
825
826 /* deassert reset lines */
827 jtag_add_reset(0, 0);
828
829 return ERROR_OK;
830 }
831
832 int arm7_9_clear_halt(target_t *target)
833 {
834 armv4_5_common_t *armv4_5 = target->arch_info;
835 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
836 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
837
838 /* we used DBGRQ only if we didn't come out of reset */
839 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
840 {
841 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
842 */
843 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
844 embeddedice_store_reg(dbg_ctrl);
845 }
846 else
847 {
848 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
849 {
850 /* if we came out of reset, and vector catch is supported, we used
851 * vector catch to enter debug state
852 * restore the register in that case
853 */
854 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
855 }
856 else
857 {
858 /* restore registers if watchpoint unit 0 was in use
859 */
860 if (arm7_9->wp0_used)
861 {
862 if (arm7_9->debug_entry_from_reset)
863 {
864 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
865 }
866 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
867 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
868 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
869 }
870 /* control value always has to be restored, as it was either disabled,
871 * or enabled with possibly different bits
872 */
873 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
874 }
875 }
876
877 return ERROR_OK;
878 }
879
880 int arm7_9_soft_reset_halt(struct target_s *target)
881 {
882 armv4_5_common_t *armv4_5 = target->arch_info;
883 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
884 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
885 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
886 int i;
887 int retval;
888
889 if ((retval=target_halt(target))!=ERROR_OK)
890 return retval;
891
892 for (i=0; i<10; i++)
893 {
894 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
895 break;
896 embeddedice_read_reg(dbg_stat);
897 if ((retval=jtag_execute_queue())!=ERROR_OK)
898 return retval;
899 /* do not eat all CPU, time out after 1 se*/
900 usleep(100*1000);
901
902 }
903 if (i==10)
904 {
905 LOG_ERROR("Failed to halt CPU after 1 sec");
906 return ERROR_TARGET_TIMEOUT;
907 }
908 target->state = TARGET_HALTED;
909
910 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
911 * ensure that DBGRQ is cleared
912 */
913 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
914 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
915 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
916 embeddedice_store_reg(dbg_ctrl);
917
918 arm7_9_clear_halt(target);
919
920 /* if the target is in Thumb state, change to ARM state */
921 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
922 {
923 u32 r0_thumb, pc_thumb;
924 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
925 /* Entered debug from Thumb mode */
926 armv4_5->core_state = ARMV4_5_STATE_THUMB;
927 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
928 }
929
930 /* all register content is now invalid */
931 armv4_5_invalidate_core_regs(target);
932
933 /* SVC, ARM state, IRQ and FIQ disabled */
934 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
935 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
936 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
937
938 /* start fetching from 0x0 */
939 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
940 armv4_5->core_cache->reg_list[15].dirty = 1;
941 armv4_5->core_cache->reg_list[15].valid = 1;
942
943 armv4_5->core_mode = ARMV4_5_MODE_SVC;
944 armv4_5->core_state = ARMV4_5_STATE_ARM;
945
946 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
947 return ERROR_FAIL;
948
949 /* reset registers */
950 for (i = 0; i <= 14; i++)
951 {
952 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
953 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
954 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
955 }
956
957 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
958
959 return ERROR_OK;
960 }
961
962 int arm7_9_halt(target_t *target)
963 {
964 armv4_5_common_t *armv4_5 = target->arch_info;
965 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
966 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
967
968 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
969
970 if (target->state == TARGET_HALTED)
971 {
972 LOG_DEBUG("target was already halted");
973 return ERROR_OK;
974 }
975
976 if (target->state == TARGET_UNKNOWN)
977 {
978 LOG_WARNING("target was in unknown state when halt was requested");
979 }
980
981 if (target->state == TARGET_RESET)
982 {
983 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
984 {
985 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
986 return ERROR_TARGET_FAILURE;
987 }
988 else
989 {
990 /* we came here in a reset_halt or reset_init sequence
991 * debug entry was already prepared in arm7_9_assert_reset()
992 */
993 target->debug_reason = DBG_REASON_DBGRQ;
994
995 return ERROR_OK;
996 }
997 }
998
999 if (arm7_9->use_dbgrq)
1000 {
1001 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1002 */
1003 if (arm7_9->set_special_dbgrq) {
1004 arm7_9->set_special_dbgrq(target);
1005 } else {
1006 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1007 embeddedice_store_reg(dbg_ctrl);
1008 }
1009 }
1010 else
1011 {
1012 /* program watchpoint unit to match on any address
1013 */
1014 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1015 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1016 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1017 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1018 }
1019
1020 target->debug_reason = DBG_REASON_DBGRQ;
1021
1022 return ERROR_OK;
1023 }
1024
1025 int arm7_9_debug_entry(target_t *target)
1026 {
1027 int i;
1028 u32 context[16];
1029 u32* context_p[16];
1030 u32 r0_thumb, pc_thumb;
1031 u32 cpsr;
1032 int retval;
1033 /* get pointers to arch-specific information */
1034 armv4_5_common_t *armv4_5 = target->arch_info;
1035 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1036 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1037 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1038
1039 #ifdef _DEBUG_ARM7_9_
1040 LOG_DEBUG("-");
1041 #endif
1042
1043 if (arm7_9->pre_debug_entry)
1044 arm7_9->pre_debug_entry(target);
1045
1046 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1047 * ensure that DBGRQ is cleared
1048 */
1049 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1050 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1051 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1052 embeddedice_store_reg(dbg_ctrl);
1053
1054 arm7_9_clear_halt(target);
1055
1056 if ((retval = jtag_execute_queue()) != ERROR_OK)
1057 {
1058 return retval;
1059 }
1060
1061 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1062 return retval;
1063
1064
1065 if (target->state != TARGET_HALTED)
1066 {
1067 LOG_WARNING("target not halted");
1068 return ERROR_TARGET_NOT_HALTED;
1069 }
1070
1071 /* if the target is in Thumb state, change to ARM state */
1072 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1073 {
1074 LOG_DEBUG("target entered debug from Thumb state");
1075 /* Entered debug from Thumb mode */
1076 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1077 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1078 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1079 }
1080 else
1081 {
1082 LOG_DEBUG("target entered debug from ARM state");
1083 /* Entered debug from ARM mode */
1084 armv4_5->core_state = ARMV4_5_STATE_ARM;
1085 }
1086
1087 for (i = 0; i < 16; i++)
1088 context_p[i] = &context[i];
1089 /* save core registers (r0 - r15 of current core mode) */
1090 arm7_9->read_core_regs(target, 0xffff, context_p);
1091
1092 arm7_9->read_xpsr(target, &cpsr, 0);
1093
1094 if ((retval = jtag_execute_queue()) != ERROR_OK)
1095 return retval;
1096
1097 /* if the core has been executing in Thumb state, set the T bit */
1098 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1099 cpsr |= 0x20;
1100
1101 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1102 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1103 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1104
1105 armv4_5->core_mode = cpsr & 0x1f;
1106
1107 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1108 {
1109 target->state = TARGET_UNKNOWN;
1110 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1111 return ERROR_TARGET_FAILURE;
1112 }
1113
1114 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1115
1116 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1117 {
1118 LOG_DEBUG("thumb state, applying fixups");
1119 context[0] = r0_thumb;
1120 context[15] = pc_thumb;
1121 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1122 {
1123 /* adjust value stored by STM */
1124 context[15] -= 3 * 4;
1125 }
1126
1127 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1128 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1129 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1130 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1131 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1132 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1133 else if (target->debug_reason == DBG_REASON_DBGRQ)
1134 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1135 else
1136 {
1137 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1138 }
1139
1140 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1141 return ERROR_FAIL;
1142
1143 for (i=0; i<=15; i++)
1144 {
1145 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1146 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1147 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1148 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1149 }
1150
1151 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1152
1153 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1154 return ERROR_FAIL;
1155
1156 /* exceptions other than USR & SYS have a saved program status register */
1157 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1158 {
1159 u32 spsr;
1160 arm7_9->read_xpsr(target, &spsr, 1);
1161 jtag_execute_queue();
1162 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1163 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1164 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1165 }
1166
1167 /* r0 and r15 (pc) have to be restored later */
1168 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1169 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1170
1171 if ((retval = jtag_execute_queue()) != ERROR_OK)
1172 return retval;
1173
1174 if (arm7_9->post_debug_entry)
1175 arm7_9->post_debug_entry(target);
1176
1177 return ERROR_OK;
1178 }
1179
1180 int arm7_9_full_context(target_t *target)
1181 {
1182 int i;
1183 int retval;
1184 armv4_5_common_t *armv4_5 = target->arch_info;
1185 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1186
1187 LOG_DEBUG("-");
1188
1189 if (target->state != TARGET_HALTED)
1190 {
1191 LOG_WARNING("target not halted");
1192 return ERROR_TARGET_NOT_HALTED;
1193 }
1194
1195 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1196 return ERROR_FAIL;
1197
1198 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1199 * SYS shares registers with User, so we don't touch SYS
1200 */
1201 for(i = 0; i < 6; i++)
1202 {
1203 u32 mask = 0;
1204 u32* reg_p[16];
1205 int j;
1206 int valid = 1;
1207
1208 /* check if there are invalid registers in the current mode
1209 */
1210 for (j = 0; j <= 16; j++)
1211 {
1212 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1213 valid = 0;
1214 }
1215
1216 if (!valid)
1217 {
1218 u32 tmp_cpsr;
1219
1220 /* change processor mode (and mask T bit) */
1221 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1222 tmp_cpsr |= armv4_5_number_to_mode(i);
1223 tmp_cpsr &= ~0x20;
1224 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1225
1226 for (j = 0; j < 15; j++)
1227 {
1228 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1229 {
1230 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1231 mask |= 1 << j;
1232 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1233 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1234 }
1235 }
1236
1237 /* if only the PSR is invalid, mask is all zeroes */
1238 if (mask)
1239 arm7_9->read_core_regs(target, mask, reg_p);
1240
1241 /* check if the PSR has to be read */
1242 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1243 {
1244 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1245 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1246 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1247 }
1248 }
1249 }
1250
1251 /* restore processor mode (mask T bit) */
1252 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1253
1254 if ((retval = jtag_execute_queue()) != ERROR_OK)
1255 {
1256 return retval;
1257 }
1258 return ERROR_OK;
1259 }
1260
1261 int arm7_9_restore_context(target_t *target)
1262 {
1263 armv4_5_common_t *armv4_5 = target->arch_info;
1264 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1265 reg_t *reg;
1266 armv4_5_core_reg_t *reg_arch_info;
1267 enum armv4_5_mode current_mode = armv4_5->core_mode;
1268 int i, j;
1269 int dirty;
1270 int mode_change;
1271
1272 LOG_DEBUG("-");
1273
1274 if (target->state != TARGET_HALTED)
1275 {
1276 LOG_WARNING("target not halted");
1277 return ERROR_TARGET_NOT_HALTED;
1278 }
1279
1280 if (arm7_9->pre_restore_context)
1281 arm7_9->pre_restore_context(target);
1282
1283 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1284 return ERROR_FAIL;
1285
1286 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1287 * SYS shares registers with User, so we don't touch SYS
1288 */
1289 for (i = 0; i < 6; i++)
1290 {
1291 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1292 dirty = 0;
1293 mode_change = 0;
1294 /* check if there are dirty registers in the current mode
1295 */
1296 for (j = 0; j <= 16; j++)
1297 {
1298 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1299 reg_arch_info = reg->arch_info;
1300 if (reg->dirty == 1)
1301 {
1302 if (reg->valid == 1)
1303 {
1304 dirty = 1;
1305 LOG_DEBUG("examining dirty reg: %s", reg->name);
1306 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1307 && (reg_arch_info->mode != current_mode)
1308 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1309 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1310 {
1311 mode_change = 1;
1312 LOG_DEBUG("require mode change");
1313 }
1314 }
1315 else
1316 {
1317 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1318 }
1319 }
1320 }
1321
1322 if (dirty)
1323 {
1324 u32 mask = 0x0;
1325 int num_regs = 0;
1326 u32 regs[16];
1327
1328 if (mode_change)
1329 {
1330 u32 tmp_cpsr;
1331
1332 /* change processor mode (mask T bit) */
1333 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1334 tmp_cpsr |= armv4_5_number_to_mode(i);
1335 tmp_cpsr &= ~0x20;
1336 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1337 current_mode = armv4_5_number_to_mode(i);
1338 }
1339
1340 for (j = 0; j <= 14; j++)
1341 {
1342 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1343 reg_arch_info = reg->arch_info;
1344
1345
1346 if (reg->dirty == 1)
1347 {
1348 regs[j] = buf_get_u32(reg->value, 0, 32);
1349 mask |= 1 << j;
1350 num_regs++;
1351 reg->dirty = 0;
1352 reg->valid = 1;
1353 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1354 }
1355 }
1356
1357 if (mask)
1358 {
1359 arm7_9->write_core_regs(target, mask, regs);
1360 }
1361
1362 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1363 reg_arch_info = reg->arch_info;
1364 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1365 {
1366 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1367 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1368 }
1369 }
1370 }
1371
1372 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1373 {
1374 /* restore processor mode (mask T bit) */
1375 u32 tmp_cpsr;
1376
1377 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1378 tmp_cpsr |= armv4_5_number_to_mode(i);
1379 tmp_cpsr &= ~0x20;
1380 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1381 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1382 }
1383 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1384 {
1385 /* CPSR has been changed, full restore necessary (mask T bit) */
1386 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1387 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1388 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1389 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1390 }
1391
1392 /* restore PC */
1393 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1394 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1395 armv4_5->core_cache->reg_list[15].dirty = 0;
1396
1397 if (arm7_9->post_restore_context)
1398 arm7_9->post_restore_context(target);
1399
1400 return ERROR_OK;
1401 }
1402
1403 int arm7_9_restart_core(struct target_s *target)
1404 {
1405 armv4_5_common_t *armv4_5 = target->arch_info;
1406 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1407 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1408
1409 /* set RESTART instruction */
1410 jtag_add_end_state(TAP_RTI);
1411 if (arm7_9->need_bypass_before_restart) {
1412 arm7_9->need_bypass_before_restart = 0;
1413 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1414 }
1415 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1416
1417 jtag_add_runtest(1, TAP_RTI);
1418 return jtag_execute_queue();
1419 }
1420
1421 void arm7_9_enable_watchpoints(struct target_s *target)
1422 {
1423 watchpoint_t *watchpoint = target->watchpoints;
1424
1425 while (watchpoint)
1426 {
1427 if (watchpoint->set == 0)
1428 arm7_9_set_watchpoint(target, watchpoint);
1429 watchpoint = watchpoint->next;
1430 }
1431 }
1432
1433 void arm7_9_enable_breakpoints(struct target_s *target)
1434 {
1435 breakpoint_t *breakpoint = target->breakpoints;
1436
1437 /* set any pending breakpoints */
1438 while (breakpoint)
1439 {
1440 if (breakpoint->set == 0)
1441 arm7_9_set_breakpoint(target, breakpoint);
1442 breakpoint = breakpoint->next;
1443 }
1444 }
1445
1446 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1447 {
1448 breakpoint_t *breakpoint = target->breakpoints;
1449 watchpoint_t *watchpoint = target->watchpoints;
1450
1451 /* set any pending breakpoints */
1452 while (breakpoint)
1453 {
1454 if (breakpoint->set != 0)
1455 arm7_9_unset_breakpoint(target, breakpoint);
1456 breakpoint = breakpoint->next;
1457 }
1458
1459 while (watchpoint)
1460 {
1461 if (watchpoint->set != 0)
1462 arm7_9_unset_watchpoint(target, watchpoint);
1463 watchpoint = watchpoint->next;
1464 }
1465 }
1466
1467 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1468 {
1469 armv4_5_common_t *armv4_5 = target->arch_info;
1470 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1471 breakpoint_t *breakpoint = target->breakpoints;
1472 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1473 int err;
1474
1475 LOG_DEBUG("-");
1476
1477 if (target->state != TARGET_HALTED)
1478 {
1479 LOG_WARNING("target not halted");
1480 return ERROR_TARGET_NOT_HALTED;
1481 }
1482
1483 if (!debug_execution)
1484 {
1485 target_free_all_working_areas(target);
1486 }
1487
1488 /* current = 1: continue on current pc, otherwise continue at <address> */
1489 if (!current)
1490 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1491
1492 /* the front-end may request us not to handle breakpoints */
1493 if (handle_breakpoints)
1494 {
1495 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1496 {
1497 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1498 arm7_9_unset_breakpoint(target, breakpoint);
1499
1500 LOG_DEBUG("enable single-step");
1501 arm7_9->enable_single_step(target);
1502
1503 target->debug_reason = DBG_REASON_SINGLESTEP;
1504
1505 arm7_9_restore_context(target);
1506
1507 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1508 arm7_9->branch_resume(target);
1509 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1510 {
1511 arm7_9->branch_resume_thumb(target);
1512 }
1513 else
1514 {
1515 LOG_ERROR("unhandled core state");
1516 return ERROR_FAIL;
1517 }
1518
1519 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1520 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1521 err = arm7_9_execute_sys_speed(target);
1522
1523 LOG_DEBUG("disable single-step");
1524 arm7_9->disable_single_step(target);
1525
1526 if (err != ERROR_OK)
1527 {
1528 arm7_9_set_breakpoint(target, breakpoint);
1529 target->state = TARGET_UNKNOWN;
1530 return err;
1531 }
1532
1533 arm7_9_debug_entry(target);
1534 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1535
1536 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1537 arm7_9_set_breakpoint(target, breakpoint);
1538 }
1539 }
1540
1541 /* enable any pending breakpoints and watchpoints */
1542 arm7_9_enable_breakpoints(target);
1543 arm7_9_enable_watchpoints(target);
1544
1545 arm7_9_restore_context(target);
1546
1547 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1548 {
1549 arm7_9->branch_resume(target);
1550 }
1551 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1552 {
1553 arm7_9->branch_resume_thumb(target);
1554 }
1555 else
1556 {
1557 LOG_ERROR("unhandled core state");
1558 return ERROR_FAIL;
1559 }
1560
1561 /* deassert DBGACK and INTDIS */
1562 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1563 /* INTDIS only when we really resume, not during debug execution */
1564 if (!debug_execution)
1565 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1566 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1567
1568 arm7_9_restart_core(target);
1569
1570 target->debug_reason = DBG_REASON_NOTHALTED;
1571
1572 if (!debug_execution)
1573 {
1574 /* registers are now invalid */
1575 armv4_5_invalidate_core_regs(target);
1576 target->state = TARGET_RUNNING;
1577 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1578 }
1579 else
1580 {
1581 target->state = TARGET_DEBUG_RUNNING;
1582 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1583 }
1584
1585 LOG_DEBUG("target resumed");
1586
1587 return ERROR_OK;
1588 }
1589
1590 void arm7_9_enable_eice_step(target_t *target)
1591 {
1592 armv4_5_common_t *armv4_5 = target->arch_info;
1593 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1594
1595 /* setup an inverse breakpoint on the current PC
1596 * - comparator 1 matches the current address
1597 * - rangeout from comparator 1 is connected to comparator 0 rangein
1598 * - comparator 0 matches any address, as long as rangein is low */
1599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1600 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1601 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1602 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
1603 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1604 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1605 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1606 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1607 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1608 }
1609
1610 void arm7_9_disable_eice_step(target_t *target)
1611 {
1612 armv4_5_common_t *armv4_5 = target->arch_info;
1613 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1614
1615 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1616 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1617 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1618 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1619 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1620 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1621 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1622 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1623 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1624 }
1625
1626 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1627 {
1628 armv4_5_common_t *armv4_5 = target->arch_info;
1629 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1630 breakpoint_t *breakpoint = NULL;
1631 int err;
1632
1633 if (target->state != TARGET_HALTED)
1634 {
1635 LOG_WARNING("target not halted");
1636 return ERROR_TARGET_NOT_HALTED;
1637 }
1638
1639 /* current = 1: continue on current pc, otherwise continue at <address> */
1640 if (!current)
1641 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1642
1643 /* the front-end may request us not to handle breakpoints */
1644 if (handle_breakpoints)
1645 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1646 arm7_9_unset_breakpoint(target, breakpoint);
1647
1648 target->debug_reason = DBG_REASON_SINGLESTEP;
1649
1650 arm7_9_restore_context(target);
1651
1652 arm7_9->enable_single_step(target);
1653
1654 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1655 {
1656 arm7_9->branch_resume(target);
1657 }
1658 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1659 {
1660 arm7_9->branch_resume_thumb(target);
1661 }
1662 else
1663 {
1664 LOG_ERROR("unhandled core state");
1665 return ERROR_FAIL;
1666 }
1667
1668 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1669
1670 err = arm7_9_execute_sys_speed(target);
1671 arm7_9->disable_single_step(target);
1672
1673 /* registers are now invalid */
1674 armv4_5_invalidate_core_regs(target);
1675
1676 if (err != ERROR_OK)
1677 {
1678 target->state = TARGET_UNKNOWN;
1679 } else {
1680 arm7_9_debug_entry(target);
1681 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1682 LOG_DEBUG("target stepped");
1683 }
1684
1685 if (breakpoint)
1686 arm7_9_set_breakpoint(target, breakpoint);
1687
1688 return err;
1689
1690 }
1691
1692 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1693 {
1694 u32* reg_p[16];
1695 u32 value;
1696 int retval;
1697 armv4_5_common_t *armv4_5 = target->arch_info;
1698 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1699
1700 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1701 return ERROR_FAIL;
1702
1703 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1704
1705 if ((num < 0) || (num > 16))
1706 return ERROR_INVALID_ARGUMENTS;
1707
1708 if ((mode != ARMV4_5_MODE_ANY)
1709 && (mode != armv4_5->core_mode)
1710 && (reg_mode != ARMV4_5_MODE_ANY))
1711 {
1712 u32 tmp_cpsr;
1713
1714 /* change processor mode (mask T bit) */
1715 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1716 tmp_cpsr |= mode;
1717 tmp_cpsr &= ~0x20;
1718 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1719 }
1720
1721 if ((num >= 0) && (num <= 15))
1722 {
1723 /* read a normal core register */
1724 reg_p[num] = &value;
1725
1726 arm7_9->read_core_regs(target, 1 << num, reg_p);
1727 }
1728 else
1729 {
1730 /* read a program status register
1731 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1732 */
1733 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1734 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1735
1736 arm7_9->read_xpsr(target, &value, spsr);
1737 }
1738
1739 if ((retval = jtag_execute_queue()) != ERROR_OK)
1740 {
1741 return retval;
1742 }
1743
1744 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1745 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1746 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1747
1748 if ((mode != ARMV4_5_MODE_ANY)
1749 && (mode != armv4_5->core_mode)
1750 && (reg_mode != ARMV4_5_MODE_ANY)) {
1751 /* restore processor mode (mask T bit) */
1752 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1753 }
1754
1755 return ERROR_OK;
1756
1757 }
1758
1759 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1760 {
1761 u32 reg[16];
1762 armv4_5_common_t *armv4_5 = target->arch_info;
1763 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1764
1765 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1766 return ERROR_FAIL;
1767
1768 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1769
1770 if ((num < 0) || (num > 16))
1771 return ERROR_INVALID_ARGUMENTS;
1772
1773 if ((mode != ARMV4_5_MODE_ANY)
1774 && (mode != armv4_5->core_mode)
1775 && (reg_mode != ARMV4_5_MODE_ANY)) {
1776 u32 tmp_cpsr;
1777
1778 /* change processor mode (mask T bit) */
1779 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1780 tmp_cpsr |= mode;
1781 tmp_cpsr &= ~0x20;
1782 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1783 }
1784
1785 if ((num >= 0) && (num <= 15))
1786 {
1787 /* write a normal core register */
1788 reg[num] = value;
1789
1790 arm7_9->write_core_regs(target, 1 << num, reg);
1791 }
1792 else
1793 {
1794 /* write a program status register
1795 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1796 */
1797 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1798 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1799
1800 /* if we're writing the CPSR, mask the T bit */
1801 if (!spsr)
1802 value &= ~0x20;
1803
1804 arm7_9->write_xpsr(target, value, spsr);
1805 }
1806
1807 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1808 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1809
1810 if ((mode != ARMV4_5_MODE_ANY)
1811 && (mode != armv4_5->core_mode)
1812 && (reg_mode != ARMV4_5_MODE_ANY)) {
1813 /* restore processor mode (mask T bit) */
1814 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1815 }
1816
1817 return jtag_execute_queue();
1818 }
1819
1820 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1821 {
1822 armv4_5_common_t *armv4_5 = target->arch_info;
1823 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1824
1825 u32 reg[16];
1826 int num_accesses = 0;
1827 int thisrun_accesses;
1828 int i;
1829 u32 cpsr;
1830 int retval;
1831 int last_reg = 0;
1832
1833 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1834
1835 if (target->state != TARGET_HALTED)
1836 {
1837 LOG_WARNING("target not halted");
1838 return ERROR_TARGET_NOT_HALTED;
1839 }
1840
1841 /* sanitize arguments */
1842 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1843 return ERROR_INVALID_ARGUMENTS;
1844
1845 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1846 return ERROR_TARGET_UNALIGNED_ACCESS;
1847
1848 /* load the base register with the address of the first word */
1849 reg[0] = address;
1850 arm7_9->write_core_regs(target, 0x1, reg);
1851
1852 switch (size)
1853 {
1854 case 4:
1855 while (num_accesses < count)
1856 {
1857 u32 reg_list;
1858 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1859 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1860
1861 if (last_reg <= thisrun_accesses)
1862 last_reg = thisrun_accesses;
1863
1864 arm7_9->load_word_regs(target, reg_list);
1865
1866 /* fast memory reads are only safe when the target is running
1867 * from a sufficiently high clock (32 kHz is usually too slow)
1868 */
1869 if (arm7_9->fast_memory_access)
1870 arm7_9_execute_fast_sys_speed(target);
1871 else
1872 arm7_9_execute_sys_speed(target);
1873
1874 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1875
1876 /* advance buffer, count number of accesses */
1877 buffer += thisrun_accesses * 4;
1878 num_accesses += thisrun_accesses;
1879 }
1880 break;
1881 case 2:
1882 while (num_accesses < count)
1883 {
1884 u32 reg_list;
1885 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1886 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1887
1888 for (i = 1; i <= thisrun_accesses; i++)
1889 {
1890 if (i > last_reg)
1891 last_reg = i;
1892 arm7_9->load_hword_reg(target, i);
1893 /* fast memory reads are only safe when the target is running
1894 * from a sufficiently high clock (32 kHz is usually too slow)
1895 */
1896 if (arm7_9->fast_memory_access)
1897 arm7_9_execute_fast_sys_speed(target);
1898 else
1899 arm7_9_execute_sys_speed(target);
1900 }
1901
1902 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1903
1904 /* advance buffer, count number of accesses */
1905 buffer += thisrun_accesses * 2;
1906 num_accesses += thisrun_accesses;
1907 }
1908 break;
1909 case 1:
1910 while (num_accesses < count)
1911 {
1912 u32 reg_list;
1913 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1914 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1915
1916 for (i = 1; i <= thisrun_accesses; i++)
1917 {
1918 if (i > last_reg)
1919 last_reg = i;
1920 arm7_9->load_byte_reg(target, i);
1921 /* fast memory reads are only safe when the target is running
1922 * from a sufficiently high clock (32 kHz is usually too slow)
1923 */
1924 if (arm7_9->fast_memory_access)
1925 arm7_9_execute_fast_sys_speed(target);
1926 else
1927 arm7_9_execute_sys_speed(target);
1928 }
1929
1930 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1931
1932 /* advance buffer, count number of accesses */
1933 buffer += thisrun_accesses * 1;
1934 num_accesses += thisrun_accesses;
1935 }
1936 break;
1937 default:
1938 LOG_ERROR("BUG: we shouldn't get here");
1939 exit(-1);
1940 break;
1941 }
1942
1943 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1944 return ERROR_FAIL;
1945
1946 for (i=0; i<=last_reg; i++)
1947 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1948
1949 arm7_9->read_xpsr(target, &cpsr, 0);
1950 if ((retval = jtag_execute_queue()) != ERROR_OK)
1951 {
1952 LOG_ERROR("JTAG error while reading cpsr");
1953 return ERROR_TARGET_DATA_ABORT;
1954 }
1955
1956 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1957 {
1958 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1959
1960 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1961
1962 return ERROR_TARGET_DATA_ABORT;
1963 }
1964
1965 return ERROR_OK;
1966 }
1967
1968 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1969 {
1970 armv4_5_common_t *armv4_5 = target->arch_info;
1971 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1972 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1973
1974 u32 reg[16];
1975 int num_accesses = 0;
1976 int thisrun_accesses;
1977 int i;
1978 u32 cpsr;
1979 int retval;
1980 int last_reg = 0;
1981
1982 #ifdef _DEBUG_ARM7_9_
1983 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1984 #endif
1985
1986 if (target->state != TARGET_HALTED)
1987 {
1988 LOG_WARNING("target not halted");
1989 return ERROR_TARGET_NOT_HALTED;
1990 }
1991
1992 /* sanitize arguments */
1993 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1994 return ERROR_INVALID_ARGUMENTS;
1995
1996 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1997 return ERROR_TARGET_UNALIGNED_ACCESS;
1998
1999 /* load the base register with the address of the first word */
2000 reg[0] = address;
2001 arm7_9->write_core_regs(target, 0x1, reg);
2002
2003 /* Clear DBGACK, to make sure memory fetches work as expected */
2004 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2005 embeddedice_store_reg(dbg_ctrl);
2006
2007 switch (size)
2008 {
2009 case 4:
2010 while (num_accesses < count)
2011 {
2012 u32 reg_list;
2013 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2014 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2015
2016 for (i = 1; i <= thisrun_accesses; i++)
2017 {
2018 if (i > last_reg)
2019 last_reg = i;
2020 reg[i] = target_buffer_get_u32(target, buffer);
2021 buffer += 4;
2022 }
2023
2024 arm7_9->write_core_regs(target, reg_list, reg);
2025
2026 arm7_9->store_word_regs(target, reg_list);
2027
2028 /* fast memory writes are only safe when the target is running
2029 * from a sufficiently high clock (32 kHz is usually too slow)
2030 */
2031 if (arm7_9->fast_memory_access)
2032 arm7_9_execute_fast_sys_speed(target);
2033 else
2034 arm7_9_execute_sys_speed(target);
2035
2036 num_accesses += thisrun_accesses;
2037 }
2038 break;
2039 case 2:
2040 while (num_accesses < count)
2041 {
2042 u32 reg_list;
2043 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2044 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2045
2046 for (i = 1; i <= thisrun_accesses; i++)
2047 {
2048 if (i > last_reg)
2049 last_reg = i;
2050 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2051 buffer += 2;
2052 }
2053
2054 arm7_9->write_core_regs(target, reg_list, reg);
2055
2056 for (i = 1; i <= thisrun_accesses; i++)
2057 {
2058 arm7_9->store_hword_reg(target, i);
2059
2060 /* fast memory writes are only safe when the target is running
2061 * from a sufficiently high clock (32 kHz is usually too slow)
2062 */
2063 if (arm7_9->fast_memory_access)
2064 arm7_9_execute_fast_sys_speed(target);
2065 else
2066 arm7_9_execute_sys_speed(target);
2067 }
2068
2069 num_accesses += thisrun_accesses;
2070 }
2071 break;
2072 case 1:
2073 while (num_accesses < count)
2074 {
2075 u32 reg_list;
2076 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2077 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2078
2079 for (i = 1; i <= thisrun_accesses; i++)
2080 {
2081 if (i > last_reg)
2082 last_reg = i;
2083 reg[i] = *buffer++ & 0xff;
2084 }
2085
2086 arm7_9->write_core_regs(target, reg_list, reg);
2087
2088 for (i = 1; i <= thisrun_accesses; i++)
2089 {
2090 arm7_9->store_byte_reg(target, i);
2091 /* fast memory writes are only safe when the target is running
2092 * from a sufficiently high clock (32 kHz is usually too slow)
2093 */
2094 if (arm7_9->fast_memory_access)
2095 arm7_9_execute_fast_sys_speed(target);
2096 else
2097 arm7_9_execute_sys_speed(target);
2098 }
2099
2100 num_accesses += thisrun_accesses;
2101 }
2102 break;
2103 default:
2104 LOG_ERROR("BUG: we shouldn't get here");
2105 exit(-1);
2106 break;
2107 }
2108
2109 /* Re-Set DBGACK */
2110 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2111 embeddedice_store_reg(dbg_ctrl);
2112
2113 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2114 return ERROR_FAIL;
2115
2116 for (i=0; i<=last_reg; i++)
2117 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2118
2119 arm7_9->read_xpsr(target, &cpsr, 0);
2120 if ((retval = jtag_execute_queue()) != ERROR_OK)
2121 {
2122 LOG_ERROR("JTAG error while reading cpsr");
2123 return ERROR_TARGET_DATA_ABORT;
2124 }
2125
2126 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2127 {
2128 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2129
2130 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2131
2132 return ERROR_TARGET_DATA_ABORT;
2133 }
2134
2135 return ERROR_OK;
2136 }
2137
2138 static const u32 dcc_code[] =
2139 {
2140 /* MRC TST BNE MRC STR B */
2141 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2142 };
2143
2144 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2145 {
2146 armv4_5_common_t *armv4_5 = target->arch_info;
2147 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2148 enum armv4_5_state core_state = armv4_5->core_state;
2149 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2150 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2151 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2152 int i;
2153
2154 if (!arm7_9->dcc_downloads)
2155 return target->type->write_memory(target, address, 4, count, buffer);
2156
2157 /* regrab previously allocated working_area, or allocate a new one */
2158 if (!arm7_9->dcc_working_area)
2159 {
2160 u8 dcc_code_buf[6 * 4];
2161
2162 /* make sure we have a working area */
2163 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2164 {
2165 LOG_INFO("no working area available, falling back to memory writes");
2166 return target->type->write_memory(target, address, 4, count, buffer);
2167 }
2168
2169 /* copy target instructions to target endianness */
2170 for (i = 0; i < 6; i++)
2171 {
2172 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2173 }
2174
2175 /* write DCC code to working area */
2176 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2177 }
2178
2179 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2180 armv4_5->core_cache->reg_list[0].valid = 1;
2181 armv4_5->core_cache->reg_list[0].dirty = 1;
2182 armv4_5->core_state = ARMV4_5_STATE_ARM;
2183
2184 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2185
2186 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2187 if (count>2)
2188 {
2189 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2190 core function repeated.
2191 */
2192 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2193 buffer+=4;
2194
2195 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2196 u8 reg_addr = ice_reg->addr & 0x1f;
2197 int chain_pos = ice_reg->jtag_info->chain_pos;
2198
2199 embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
2200 buffer += (count-2)*4;
2201
2202 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2203 } else
2204 {
2205 for (i = 0; i < count; i++)
2206 {
2207 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2208 buffer += 4;
2209 }
2210 }
2211
2212 target_halt(target);
2213
2214 for (i=0; i<100; i++)
2215 {
2216 target_poll(target);
2217 if (target->state == TARGET_HALTED)
2218 break;
2219 usleep(1000); /* sleep 1ms */
2220 }
2221 if (i == 100)
2222 {
2223 LOG_ERROR("bulk write timed out, target not halted");
2224 return ERROR_TARGET_TIMEOUT;
2225 }
2226
2227 /* restore target state */
2228 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2229 armv4_5->core_cache->reg_list[0].valid = 1;
2230 armv4_5->core_cache->reg_list[0].dirty = 1;
2231 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2232 armv4_5->core_cache->reg_list[1].valid = 1;
2233 armv4_5->core_cache->reg_list[1].dirty = 1;
2234 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2235 armv4_5->core_cache->reg_list[15].valid = 1;
2236 armv4_5->core_cache->reg_list[15].dirty = 1;
2237 armv4_5->core_state = core_state;
2238
2239 return ERROR_OK;
2240 }
2241
2242 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2243 {
2244 working_area_t *crc_algorithm;
2245 armv4_5_algorithm_t armv4_5_info;
2246 reg_param_t reg_params[2];
2247 int retval;
2248
2249 u32 arm7_9_crc_code[] = {
2250 0xE1A02000, /* mov r2, r0 */
2251 0xE3E00000, /* mov r0, #0xffffffff */
2252 0xE1A03001, /* mov r3, r1 */
2253 0xE3A04000, /* mov r4, #0 */
2254 0xEA00000B, /* b ncomp */
2255 /* nbyte: */
2256 0xE7D21004, /* ldrb r1, [r2, r4] */
2257 0xE59F7030, /* ldr r7, CRC32XOR */
2258 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2259 0xE3A05000, /* mov r5, #0 */
2260 /* loop: */
2261 0xE3500000, /* cmp r0, #0 */
2262 0xE1A06080, /* mov r6, r0, asl #1 */
2263 0xE2855001, /* add r5, r5, #1 */
2264 0xE1A00006, /* mov r0, r6 */
2265 0xB0260007, /* eorlt r0, r6, r7 */
2266 0xE3550008, /* cmp r5, #8 */
2267 0x1AFFFFF8, /* bne loop */
2268 0xE2844001, /* add r4, r4, #1 */
2269 /* ncomp: */
2270 0xE1540003, /* cmp r4, r3 */
2271 0x1AFFFFF1, /* bne nbyte */
2272 /* end: */
2273 0xEAFFFFFE, /* b end */
2274 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2275 };
2276
2277 int i;
2278
2279 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2280 {
2281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2282 }
2283
2284 /* convert flash writing code into a buffer in target endianness */
2285 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2286 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2287
2288 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2289 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2290 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2291
2292 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2293 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2294
2295 buf_set_u32(reg_params[0].value, 0, 32, address);
2296 buf_set_u32(reg_params[1].value, 0, 32, count);
2297
2298 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2299 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2300 {
2301 LOG_ERROR("error executing arm7_9 crc algorithm");
2302 destroy_reg_param(&reg_params[0]);
2303 destroy_reg_param(&reg_params[1]);
2304 target_free_working_area(target, crc_algorithm);
2305 return retval;
2306 }
2307
2308 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2309
2310 destroy_reg_param(&reg_params[0]);
2311 destroy_reg_param(&reg_params[1]);
2312
2313 target_free_working_area(target, crc_algorithm);
2314
2315 return ERROR_OK;
2316 }
2317
2318 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2319 {
2320 working_area_t *erase_check_algorithm;
2321 reg_param_t reg_params[3];
2322 armv4_5_algorithm_t armv4_5_info;
2323 int retval;
2324 int i;
2325
2326 u32 erase_check_code[] =
2327 {
2328 /* loop: */
2329 0xe4d03001, /* ldrb r3, [r0], #1 */
2330 0xe0022003, /* and r2, r2, r3 */
2331 0xe2511001, /* subs r1, r1, #1 */
2332 0x1afffffb, /* bne loop */
2333 /* end: */
2334 0xeafffffe /* b end */
2335 };
2336
2337 /* make sure we have a working area */
2338 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2339 {
2340 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2341 }
2342
2343 /* convert flash writing code into a buffer in target endianness */
2344 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2345 target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
2346
2347 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2348 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2349 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2350
2351 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2352 buf_set_u32(reg_params[0].value, 0, 32, address);
2353
2354 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2355 buf_set_u32(reg_params[1].value, 0, 32, count);
2356
2357 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2358 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2359
2360 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2361 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2362 {
2363 destroy_reg_param(&reg_params[0]);
2364 destroy_reg_param(&reg_params[1]);
2365 destroy_reg_param(&reg_params[2]);
2366 target_free_working_area(target, erase_check_algorithm);
2367 return 0;
2368 }
2369
2370 *blank = buf_get_u32(reg_params[2].value, 0, 32);
2371
2372 destroy_reg_param(&reg_params[0]);
2373 destroy_reg_param(&reg_params[1]);
2374 destroy_reg_param(&reg_params[2]);
2375
2376 target_free_working_area(target, erase_check_algorithm);
2377
2378 return ERROR_OK;
2379 }
2380
2381 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2382 {
2383 command_t *arm7_9_cmd;
2384
2385 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2386
2387 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2388 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2389
2390 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2391
2392 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2393 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2394 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2395 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2396 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2397 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2398 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2399 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2400 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2401 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2402
2403 armv4_5_register_commands(cmd_ctx);
2404
2405 etm_register_commands(cmd_ctx);
2406
2407 return ERROR_OK;
2408 }
2409
2410 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2411 {
2412 u32 value;
2413 int spsr;
2414 int retval;
2415 target_t *target = get_current_target(cmd_ctx);
2416 armv4_5_common_t *armv4_5;
2417 arm7_9_common_t *arm7_9;
2418
2419 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2420 {
2421 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2422 return ERROR_OK;
2423 }
2424
2425 if (target->state != TARGET_HALTED)
2426 {
2427 command_print(cmd_ctx, "can't write registers while running");
2428 return ERROR_OK;
2429 }
2430
2431 if (argc < 2)
2432 {
2433 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2434 return ERROR_OK;
2435 }
2436
2437 value = strtoul(args[0], NULL, 0);
2438 spsr = strtol(args[1], NULL, 0);
2439
2440 /* if we're writing the CPSR, mask the T bit */
2441 if (!spsr)
2442 value &= ~0x20;
2443
2444 arm7_9->write_xpsr(target, value, spsr);
2445 if ((retval = jtag_execute_queue()) != ERROR_OK)
2446 {
2447 LOG_ERROR("JTAG error while writing to xpsr");
2448 return retval;
2449 }
2450
2451 return ERROR_OK;
2452 }
2453
2454 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2455 {
2456 u32 value;
2457 int rotate;
2458 int spsr;
2459 int retval;
2460 target_t *target = get_current_target(cmd_ctx);
2461 armv4_5_common_t *armv4_5;
2462 arm7_9_common_t *arm7_9;
2463
2464 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2465 {
2466 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2467 return ERROR_OK;
2468 }
2469
2470 if (target->state != TARGET_HALTED)
2471 {
2472 command_print(cmd_ctx, "can't write registers while running");
2473 return ERROR_OK;
2474 }
2475
2476 if (argc < 3)
2477 {
2478 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2479 return ERROR_OK;
2480 }
2481
2482 value = strtoul(args[0], NULL, 0);
2483 rotate = strtol(args[1], NULL, 0);
2484 spsr = strtol(args[2], NULL, 0);
2485
2486 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2487 if ((retval = jtag_execute_queue()) != ERROR_OK)
2488 {
2489 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2490 return retval;
2491 }
2492
2493 return ERROR_OK;
2494 }
2495
2496 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2497 {
2498 u32 value;
2499 u32 mode;
2500 int num;
2501 target_t *target = get_current_target(cmd_ctx);
2502 armv4_5_common_t *armv4_5;
2503 arm7_9_common_t *arm7_9;
2504
2505 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2506 {
2507 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2508 return ERROR_OK;
2509 }
2510
2511 if (target->state != TARGET_HALTED)
2512 {
2513 command_print(cmd_ctx, "can't write registers while running");
2514 return ERROR_OK;
2515 }
2516
2517 if (argc < 3)
2518 {
2519 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2520 return ERROR_OK;
2521 }
2522
2523 num = strtol(args[0], NULL, 0);
2524 mode = strtoul(args[1], NULL, 0);
2525 value = strtoul(args[2], NULL, 0);
2526
2527 arm7_9_write_core_reg(target, num, mode, value);
2528
2529 return ERROR_OK;
2530 }
2531
2532 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2533 {
2534 target_t *target = get_current_target(cmd_ctx);
2535 armv4_5_common_t *armv4_5;
2536 arm7_9_common_t *arm7_9;
2537
2538 if (target->state != TARGET_HALTED)
2539 {
2540 LOG_ERROR("target not halted");
2541 return ERROR_TARGET_NOT_HALTED;
2542 }
2543
2544 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2545 {
2546 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2547 return ERROR_OK;
2548 }
2549
2550 if (argc == 0)
2551 {
2552 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2553 return ERROR_OK;
2554 }
2555
2556 if (strcmp("enable", args[0]) == 0)
2557 {
2558 if (arm7_9->sw_bkpts_use_wp)
2559 {
2560 arm7_9_enable_sw_bkpts(target);
2561 }
2562 else
2563 {
2564 arm7_9->sw_bkpts_enabled = 1;
2565 }
2566 }
2567 else if (strcmp("disable", args[0]) == 0)
2568 {
2569 if (arm7_9->sw_bkpts_use_wp)
2570 {
2571 arm7_9_disable_sw_bkpts(target);
2572 }
2573 else
2574 {
2575 arm7_9->sw_bkpts_enabled = 0;
2576 }
2577 }
2578 else
2579 {
2580 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2581 }
2582
2583 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2584
2585 return ERROR_OK;
2586 }
2587
2588 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2589 {
2590 target_t *target = get_current_target(cmd_ctx);
2591 armv4_5_common_t *armv4_5;
2592 arm7_9_common_t *arm7_9;
2593
2594 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2595 {
2596 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2597 return ERROR_OK;
2598 }
2599
2600 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2601 {
2602 arm7_9->force_hw_bkpts = 1;
2603 if (arm7_9->sw_bkpts_use_wp)
2604 {
2605 arm7_9_disable_sw_bkpts(target);
2606 }
2607 }
2608 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2609 {
2610 arm7_9->force_hw_bkpts = 0;
2611 }
2612 else
2613 {
2614 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2615 }
2616
2617 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2618
2619 return ERROR_OK;
2620 }
2621
2622 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2623 {
2624 target_t *target = get_current_target(cmd_ctx);
2625 armv4_5_common_t *armv4_5;
2626 arm7_9_common_t *arm7_9;
2627
2628 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2629 {
2630 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2631 return ERROR_OK;
2632 }
2633
2634 if (argc > 0)
2635 {
2636 if (strcmp("enable", args[0]) == 0)
2637 {
2638 arm7_9->use_dbgrq = 1;
2639 }
2640 else if (strcmp("disable", args[0]) == 0)
2641 {
2642 arm7_9->use_dbgrq = 0;
2643 }
2644 else
2645 {
2646 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2647 }
2648 }
2649
2650 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2651
2652 return ERROR_OK;
2653 }
2654
2655 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2656 {
2657 target_t *target = get_current_target(cmd_ctx);
2658 armv4_5_common_t *armv4_5;
2659 arm7_9_common_t *arm7_9;
2660
2661 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2662 {
2663 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2664 return ERROR_OK;
2665 }
2666
2667 if (argc > 0)
2668 {
2669 if (strcmp("enable", args[0]) == 0)
2670 {
2671 arm7_9->fast_memory_access = 1;
2672 }
2673 else if (strcmp("disable", args[0]) == 0)
2674 {
2675 arm7_9->fast_memory_access = 0;
2676 }
2677 else
2678 {
2679 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2680 }
2681 }
2682
2683 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2684
2685 return ERROR_OK;
2686 }
2687
2688 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2689 {
2690 target_t *target = get_current_target(cmd_ctx);
2691 armv4_5_common_t *armv4_5;
2692 arm7_9_common_t *arm7_9;
2693
2694 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2695 {
2696 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2697 return ERROR_OK;
2698 }
2699
2700 if (argc > 0)
2701 {
2702 if (strcmp("enable", args[0]) == 0)
2703 {
2704 arm7_9->dcc_downloads = 1;
2705 }
2706 else if (strcmp("disable", args[0]) == 0)
2707 {
2708 arm7_9->dcc_downloads = 0;
2709 }
2710 else
2711 {
2712 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2713 }
2714 }
2715
2716 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2717
2718 return ERROR_OK;
2719 }
2720
2721 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2722 {
2723 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2724
2725 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2726
2727 arm_jtag_setup_connection(&arm7_9->jtag_info);
2728 arm7_9->wp_available = 2;
2729 arm7_9->wp0_used = 0;
2730 arm7_9->wp1_used = 0;
2731 arm7_9->force_hw_bkpts = 0;
2732 arm7_9->use_dbgrq = 0;
2733
2734 arm7_9->etm_ctx = NULL;
2735 arm7_9->has_single_step = 0;
2736 arm7_9->has_monitor_mode = 0;
2737 arm7_9->has_vector_catch = 0;
2738
2739 arm7_9->debug_entry_from_reset = 0;
2740
2741 arm7_9->dcc_working_area = NULL;
2742
2743 arm7_9->fast_memory_access = fast_and_dangerous;
2744 arm7_9->dcc_downloads = fast_and_dangerous;
2745
2746 arm7_9->need_bypass_before_restart = 0;
2747
2748 armv4_5->arch_info = arm7_9;
2749 armv4_5->read_core_reg = arm7_9_read_core_reg;
2750 armv4_5->write_core_reg = arm7_9_write_core_reg;
2751 armv4_5->full_context = arm7_9_full_context;
2752
2753 armv4_5_init_arch_info(target, armv4_5);
2754
2755 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2756
2757 return ERROR_OK;
2758 }
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