035c5fe3ab8480f01e213ebafb0e8858eef0d898
[openocd.git] / src / target / arm7_9_common.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifndef ARM7_9_COMMON_H
30 #define ARM7_9_COMMON_H
31
32 #include "breakpoints.h"
33 #include "armv4_5.h"
34
35 #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
36
37 /**
38 * Structure for items that are common between both ARM7 and ARM9 targets.
39 */
40 struct arm7_9_common
41 {
42 struct arm armv4_5_common;
43 uint32_t common_magic;
44
45 struct arm_jtag jtag_info; /**< JTAG information for target */
46 struct reg_cache *eice_cache; /**< Embedded ICE register cache */
47
48 uint32_t arm_bkpt; /**< ARM breakpoint instruction */
49 uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
50
51 int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
52 int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
53 int breakpoint_count; /**< Current number of set breakpoints */
54 int wp_available; /**< Current number of available watchpoint units */
55 int wp_available_max; /**< Maximum number of available watchpoint units */
56 int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
57 int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
58 int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
59 int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
60 bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
61 bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
62
63 bool has_single_step;
64 bool has_monitor_mode;
65 bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
66
67 bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
68
69 bool fast_memory_access;
70 bool dcc_downloads;
71
72 struct working_area *dcc_working_area;
73
74 int (*examine_debug_reason)(struct target *target); /**< Function for determining why debug state was entered */
75
76 void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
77
78 void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
79 void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size);
80 void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
81
82 void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
83 void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
84 void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
85
86 void (*load_word_regs)(struct target *target, uint32_t mask);
87 void (*load_hword_reg)(struct target *target, int num);
88 void (*load_byte_reg)(struct target *target, int num);
89
90 void (*store_word_regs)(struct target *target, uint32_t mask);
91 void (*store_hword_reg)(struct target *target, int num);
92 void (*store_byte_reg)(struct target *target, int num);
93
94 void (*write_pc)(struct target *target, uint32_t pc); /**< Function for writing to the program counter */
95 void (*branch_resume)(struct target *target);
96 void (*branch_resume_thumb)(struct target *target);
97
98 void (*enable_single_step)(struct target *target, uint32_t next_pc);
99 void (*disable_single_step)(struct target *target);
100
101 void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */
102
103 void (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
104
105 void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */
106 void (*post_restore_context)(struct target *target); /**< Callback function called after restoring the processor context */
107
108
109 };
110
111 static inline struct arm7_9_common *
112 target_to_arm7_9(struct target *target)
113 {
114 return container_of(target->arch_info, struct arm7_9_common,
115 armv4_5_common);
116 }
117
118 int arm7_9_register_commands(struct command_context *cmd_ctx);
119
120 int arm7_9_poll(struct target *target);
121
122 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
123
124 int arm7_9_setup(struct target *target);
125 int arm7_9_assert_reset(struct target *target);
126 int arm7_9_deassert_reset(struct target *target);
127 int arm7_9_reset_request_halt(struct target *target);
128 int arm7_9_early_halt(struct target *target);
129 int arm7_9_soft_reset_halt(struct target *target);
130 int arm7_9_prepare_reset_halt(struct target *target);
131
132 int arm7_9_halt(struct target *target);
133 int arm7_9_full_context(struct target *target);
134 int arm7_9_restore_context(struct target *target);
135 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
136 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
137 int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode);
138 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
139 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
140 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
141 int arm7_9_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum);
142 int arm7_9_blank_check_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* blank);
143
144 int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
145
146 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
147 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
148 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
149 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
150
151 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
152 void arm7_9_disable_eice_step(struct target *target);
153
154 int arm7_9_execute_sys_speed(struct target *target);
155
156 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
157 int arm7_9_get_arch_pointers(struct target *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p);
158
159 #endif /* ARM7_9_COMMON_H */

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)