src/target/arm7_9_common.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  12  *   hontor@126.com                                                        *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifndef ARM7_9_COMMON_H
  30 #define ARM7_9_COMMON_H
  31
  32 #include "breakpoints.h"
  33 #include "etm.h"
  34
  35 #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
  36
  37 /**
  38  * Structure for items that are common between both ARM7 and ARM9 targets.
  39  */
  40 typedef struct arm7_9_common_s
  41 {
  42         u32 common_magic;
  43
  44         arm_jtag_t jtag_info; /**< JTAG information for target */
  45         reg_cache_t *eice_cache; /**< Embedded ICE register cache */
  46
  47         u32 arm_bkpt; /**< ARM breakpoint instruction */
  48         u16 thumb_bkpt; /**< Thumb breakpoint instruction */
  49         int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
  50         int breakpoint_count; /**< Current number of set breakpoints */
  51         int wp_available; /**< Current number of available watchpoint units */
  52         int wp_available_max; /**< Maximum number of available watchpoint units */
  53         int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
  54         int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
  55         int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
  56         int force_hw_bkpts;
  57         int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
  58         int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
  59         int need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
  60
  61         etm_context_t *etm_ctx;
  62
  63         int has_single_step;
  64         int has_monitor_mode;
  65         int has_vector_catch; /**< Specifies if the target has a reset vector catch */
  66
  67         int debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
  68
  69         struct working_area_s *dcc_working_area;
  70
  71         int fast_memory_access;
  72         int dcc_downloads;
  73
  74         int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
  75
  76         void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc); /**< Function for changing from Thumb to ARM mode */
  77
  78         void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]); /**< Function for reading the core registers */
  79         void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
  80         void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
  81
  82         void (*write_xpsr)(target_t *target, u32 xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
  83         void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
  84         void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
  85
  86         void (*load_word_regs)(target_t *target, u32 mask);
  87         void (*load_hword_reg)(target_t *target, int num);
  88         void (*load_byte_reg)(target_t *target, int num);
  89
  90         void (*store_word_regs)(target_t *target, u32 mask);
  91         void (*store_hword_reg)(target_t *target, int num);
  92         void (*store_byte_reg)(target_t *target, int num);
  93
  94         void (*write_pc)(target_t *target, u32 pc); /**< Function for writing to the program counter */
  95         void (*branch_resume)(target_t *target);
  96         void (*branch_resume_thumb)(target_t *target);
  97
  98         void (*enable_single_step)(target_t *target, u32 next_pc);
  99         void (*disable_single_step)(target_t *target);
 100
 101         void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
 102
 103         void (*pre_debug_entry)(target_t *target); /**< Callback function called before entering debug mode */
 104         void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
 105
 106         void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
 107         void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
 108
 109         armv4_5_common_t armv4_5_common;
 110         void *arch_info;
 111
 112 } arm7_9_common_t;
 113
 114 int arm7_9_register_commands(struct command_context_s *cmd_ctx);
 115
 116 int arm7_9_poll(target_t *target);
 117
 118 int arm7_9_target_request_data(target_t *target, u32 size, uint8_t *buffer);
 119
 120 int arm7_9_setup(target_t *target);
 121 int arm7_9_assert_reset(target_t *target);
 122 int arm7_9_deassert_reset(target_t *target);
 123 int arm7_9_reset_request_halt(target_t *target);
 124 int arm7_9_early_halt(target_t *target);
 125 int arm7_9_soft_reset_halt(struct target_s *target);
 126 int arm7_9_prepare_reset_halt(struct target_s *target);
 127
 128 int arm7_9_halt(target_t *target);
 129 int arm7_9_full_context(target_t *target);
 130 int arm7_9_restore_context(target_t *target);
 131 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 132 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 133 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
 134 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
 135 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
 136 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer);
 137 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 138 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
 139
 140 int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, u32 entry_point, void *arch_info);
 141
 142 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 143 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 144 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 145 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 146
 147 void arm7_9_enable_eice_step(target_t *target, u32 next_pc);
 148 void arm7_9_disable_eice_step(target_t *target);
 149
 150 int arm7_9_execute_sys_speed(struct target_s *target);
 151
 152 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
 153 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
 154
 155 #endif /* ARM7_9_COMMON_H */