src/target/arm7_9_common.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  12  *   hontor@126.com                                                        *
  13  *                                                                         *
  14  *   This program is free software; you can redistribute it and/or modify  *
  15  *   it under the terms of the GNU General Public License as published by  *
  16  *   the Free Software Foundation; either version 2 of the License, or     *
  17  *   (at your option) any later version.                                   *
  18  *                                                                         *
  19  *   This program is distributed in the hope that it will be useful,       *
  20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  22  *   GNU General Public License for more details.                          *
  23  *                                                                         *
  24  *   You should have received a copy of the GNU General Public License     *
  25  *   along with this program; if not, write to the                         *
  26  *   Free Software Foundation, Inc.,                                       *
  27  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  28  ***************************************************************************/
  29 #ifndef ARM7_9_COMMON_H
  30 #define ARM7_9_COMMON_H
  31
  32 #include "breakpoints.h"
  33 #include "etm.h"
  34
  35 #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
  36
  37 /**
  38  * Structure for items that are common between both ARM7 and ARM9 targets.
  39  */
  40 typedef struct arm7_9_common_s
  41 {
  42         armv4_5_common_t armv4_5_common;
  43         uint32_t common_magic;
  44
  45         arm_jtag_t jtag_info; /**< JTAG information for target */
  46         reg_cache_t *eice_cache; /**< Embedded ICE register cache */
  47
  48         uint32_t arm_bkpt; /**< ARM breakpoint instruction */
  49         uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
  50
  51         int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
  52         int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
  53         int breakpoint_count; /**< Current number of set breakpoints */
  54         int wp_available; /**< Current number of available watchpoint units */
  55         int wp_available_max; /**< Maximum number of available watchpoint units */
  56         int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
  57         int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
  58         int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
  59         int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
  60         bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
  61         bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
  62
  63         bool has_single_step;
  64         bool has_monitor_mode;
  65         bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
  66
  67         bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
  68
  69         bool fast_memory_access;
  70         bool dcc_downloads;
  71
  72         etm_context_t *etm_ctx;
  73
  74         struct working_area_s *dcc_working_area;
  75
  76         int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
  77
  78         void (*change_to_arm)(target_t *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
  79
  80         void (*read_core_regs)(target_t *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
  81         void (*read_core_regs_target_buffer)(target_t *target, uint32_t mask, void *buffer, int size);
  82         void (*read_xpsr)(target_t *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
  83
  84         void (*write_xpsr)(target_t *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
  85         void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
  86         void (*write_core_regs)(target_t *target, uint32_t mask, uint32_t core_regs[16]);
  87
  88         void (*load_word_regs)(target_t *target, uint32_t mask);
  89         void (*load_hword_reg)(target_t *target, int num);
  90         void (*load_byte_reg)(target_t *target, int num);
  91
  92         void (*store_word_regs)(target_t *target, uint32_t mask);
  93         void (*store_hword_reg)(target_t *target, int num);
  94         void (*store_byte_reg)(target_t *target, int num);
  95
  96         void (*write_pc)(target_t *target, uint32_t pc); /**< Function for writing to the program counter */
  97         void (*branch_resume)(target_t *target);
  98         void (*branch_resume_thumb)(target_t *target);
  99
 100         void (*enable_single_step)(target_t *target, uint32_t next_pc);
 101         void (*disable_single_step)(target_t *target);
 102
 103         void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
 104
 105         void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
 106
 107         void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
 108         void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
 109
 110
 111 } arm7_9_common_t;
 112
 113 static inline struct arm7_9_common_s *
 114 target_to_arm7_9(struct target_s *target)
 115 {
 116         return container_of(target->arch_info, struct arm7_9_common_s,
 117                         armv4_5_common);
 118 }
 119
 120 int arm7_9_register_commands(struct command_context_s *cmd_ctx);
 121
 122 int arm7_9_poll(target_t *target);
 123
 124 int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer);
 125
 126 int arm7_9_setup(target_t *target);
 127 int arm7_9_assert_reset(target_t *target);
 128 int arm7_9_deassert_reset(target_t *target);
 129 int arm7_9_reset_request_halt(target_t *target);
 130 int arm7_9_early_halt(target_t *target);
 131 int arm7_9_soft_reset_halt(struct target_s *target);
 132 int arm7_9_prepare_reset_halt(struct target_s *target);
 133
 134 int arm7_9_halt(target_t *target);
 135 int arm7_9_full_context(target_t *target);
 136 int arm7_9_restore_context(target_t *target);
 137 int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
 138 int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
 139 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
 140 int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 141 int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 142 int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
 143 int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
 144 int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
 145
 146 int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, uint32_t entry_point, void *arch_info);
 147
 148 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 149 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 150 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 151 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 152
 153 void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc);
 154 void arm7_9_disable_eice_step(target_t *target);
 155
 156 int arm7_9_execute_sys_speed(struct target_s *target);
 157
 158 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
 159 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
 160
 161 #endif /* ARM7_9_COMMON_H */