src/target/arm7tdmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm7tdmi.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "etm.h"
  32 #include "log.h"
  33 #include "jtag.h"
  34 #include "arm_jtag.h"
  35
  36 #include <stdlib.h>
  37 #include <string.h>
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 /* cli handling */
  44 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
  45
  46 /* forward declarations */
  47 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  48 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  49 int arm7tdmi_quit();
  50
  51 /* target function declarations */
  52 enum target_state arm7tdmi_poll(struct target_s *target);
  53 int arm7tdmi_halt(target_t *target);
  54
  55 target_type_t arm7tdmi_target =
  56 {
  57         .name = "arm7tdmi",
  58
  59         .poll = arm7_9_poll,
  60         .arch_state = armv4_5_arch_state,
  61
  62         .target_request_data = arm7_9_target_request_data,
  63
  64         .halt = arm7_9_halt,
  65         .resume = arm7_9_resume,
  66         .step = arm7_9_step,
  67
  68         .assert_reset = arm7_9_assert_reset,
  69         .deassert_reset = arm7_9_deassert_reset,
  70         .soft_reset_halt = arm7_9_soft_reset_halt,
  71         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  72
  73         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  74
  75         .read_memory = arm7_9_read_memory,
  76         .write_memory = arm7_9_write_memory,
  77         .bulk_write_memory = arm7_9_bulk_write_memory,
  78         .checksum_memory = arm7_9_checksum_memory,
  79
  80         .run_algorithm = armv4_5_run_algorithm,
  81
  82         .add_breakpoint = arm7_9_add_breakpoint,
  83         .remove_breakpoint = arm7_9_remove_breakpoint,
  84         .add_watchpoint = arm7_9_add_watchpoint,
  85         .remove_watchpoint = arm7_9_remove_watchpoint,
  86
  87         .register_commands = arm7tdmi_register_commands,
  88         .target_command = arm7tdmi_target_command,
  89         .init_target = arm7tdmi_init_target,
  90         .quit = arm7tdmi_quit
  91 };
  92
  93 int arm7tdmi_examine_debug_reason(target_t *target)
  94 {
  95         /* get pointers to arch-specific information */
  96         armv4_5_common_t *armv4_5 = target->arch_info;
  97         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  98
  99         /* only check the debug reason if we don't know it already */
 100         if ((target->debug_reason != DBG_REASON_DBGRQ)
 101                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 102         {
 103                 scan_field_t fields[2];
 104                 u8 databus[4];
 105                 u8 breakpoint;
 106
 107                 jtag_add_end_state(TAP_PD);
 108
 109                 fields[0].device = arm7_9->jtag_info.chain_pos;
 110                 fields[0].num_bits = 1;
 111                 fields[0].out_value = NULL;
 112                 fields[0].out_mask = NULL;
 113                 fields[0].in_value = &breakpoint;
 114                 fields[0].in_check_value = NULL;
 115                 fields[0].in_check_mask = NULL;
 116                 fields[0].in_handler = NULL;
 117                 fields[0].in_handler_priv = NULL;
 118
 119                 fields[1].device = arm7_9->jtag_info.chain_pos;
 120                 fields[1].num_bits = 32;
 121                 fields[1].out_value = NULL;
 122                 fields[1].out_mask = NULL;
 123                 fields[1].in_value = databus;
 124                 fields[1].in_check_value = NULL;
 125                 fields[1].in_check_mask = NULL;
 126                 fields[1].in_handler = NULL;
 127                 fields[1].in_handler_priv = NULL;
 128
 129                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 131
 132                 jtag_add_dr_scan(2, fields, TAP_PD, NULL);
 133                 jtag_execute_queue();
 134
 135                 fields[0].in_value = NULL;
 136                 fields[0].out_value = &breakpoint;
 137                 fields[1].in_value = NULL;
 138                 fields[1].out_value = databus;
 139
 140                 jtag_add_dr_scan(2, fields, TAP_PD, NULL);
 141
 142                 if (breakpoint & 1)
 143                         target->debug_reason = DBG_REASON_WATCHPOINT;
 144                 else
 145                         target->debug_reason = DBG_REASON_BREAKPOINT;
 146         }
 147
 148         return ERROR_OK;
 149 }
 150
 151 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
 152 int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
 153 {
 154         scan_field_t fields[2];
 155         u8 out_buf[4];
 156         u8 breakpoint_buf;
 157
 158         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 159         buf_set_u32(&breakpoint_buf, 0, 1, breakpoint);
 160
 161         jtag_add_end_state(TAP_PD);
 162         arm_jtag_scann(jtag_info, 0x1);
 163         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 164
 165         fields[0].device = jtag_info->chain_pos;
 166         fields[0].num_bits = 1;
 167         fields[0].out_value = &breakpoint_buf;
 168         fields[0].out_mask = NULL;
 169         fields[0].in_value = NULL;
 170         fields[0].in_check_value = NULL;
 171         fields[0].in_check_mask = NULL;
 172         fields[0].in_handler = NULL;
 173         fields[0].in_handler_priv = NULL;
 174
 175         fields[1].device = jtag_info->chain_pos;
 176         fields[1].num_bits = 32;
 177         fields[1].out_value = out_buf;
 178         fields[1].out_mask = NULL;
 179         fields[1].in_value = NULL;
 180         if (in)
 181         {
 182                 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
 183                 fields[1].in_handler_priv = in;
 184         }
 185         else
 186         {
 187                 fields[1].in_handler = NULL;
 188                 fields[1].in_handler_priv = NULL;
 189         }
 190         fields[1].in_check_value = NULL;
 191         fields[1].in_check_mask = NULL;
 192
 193         jtag_add_dr_scan(2, fields, -1, NULL);
 194
 195         jtag_add_runtest(0, -1);
 196
 197 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 198 {
 199                 jtag_execute_queue();
 200
 201                 if (in)
 202                 {
 203                         DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in);
 204                 }
 205                 else
 206                         DEBUG("out: 0x%8.8x", out);
 207 }
 208 #endif
 209
 210         return ERROR_OK;
 211 }
 212
 213 /* clock the target, reading the databus */
 214 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 215 {
 216         scan_field_t fields[2];
 217
 218         jtag_add_end_state(TAP_PD);
 219         arm_jtag_scann(jtag_info, 0x1);
 220         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 221
 222         fields[0].device = jtag_info->chain_pos;
 223         fields[0].num_bits = 1;
 224         fields[0].out_value = NULL;
 225         fields[0].out_mask = NULL;
 226         fields[0].in_value = NULL;
 227         fields[0].in_check_value = NULL;
 228         fields[0].in_check_mask = NULL;
 229         fields[0].in_handler = NULL;
 230         fields[0].in_handler_priv = NULL;
 231
 232         fields[1].device = jtag_info->chain_pos;
 233         fields[1].num_bits = 32;
 234         fields[1].out_value = NULL;
 235         fields[1].out_mask = NULL;
 236         fields[1].in_value = NULL;
 237         fields[1].in_handler = arm_jtag_buf_to_u32_flip;
 238         fields[1].in_handler_priv = in;
 239         fields[1].in_check_value = NULL;
 240         fields[1].in_check_mask = NULL;
 241
 242         jtag_add_dr_scan(2, fields, -1, NULL);
 243
 244         jtag_add_runtest(0, -1);
 245
 246 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 247 {
 248                 jtag_execute_queue();
 249
 250                 if (in)
 251                 {
 252                         DEBUG("in: 0x%8.8x", *in);
 253                 }
 254                 else
 255                 {
 256                         ERROR("BUG: called with in == NULL");
 257                 }
 258 }
 259 #endif
 260
 261         return ERROR_OK;
 262 }
 263
 264 /* clock the target, and read the databus
 265  * the *in pointer points to a buffer where elements of 'size' bytes
 266  * are stored in big (be==1) or little (be==0) endianness
 267  */
 268 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 269 {
 270         scan_field_t fields[2];
 271
 272         jtag_add_end_state(TAP_PD);
 273         arm_jtag_scann(jtag_info, 0x1);
 274         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 275
 276         fields[0].device = jtag_info->chain_pos;
 277         fields[0].num_bits = 1;
 278         fields[0].out_value = NULL;
 279         fields[0].out_mask = NULL;
 280         fields[0].in_value = NULL;
 281         fields[0].in_check_value = NULL;
 282         fields[0].in_check_mask = NULL;
 283         fields[0].in_handler = NULL;
 284         fields[0].in_handler_priv = NULL;
 285
 286         fields[1].device = jtag_info->chain_pos;
 287         fields[1].num_bits = 32;
 288         fields[1].out_value = NULL;
 289         fields[1].out_mask = NULL;
 290         fields[1].in_value = NULL;
 291         switch (size)
 292         {
 293                 case 4:
 294                         fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip;
 295                         break;
 296                 case 2:
 297                         fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip;
 298                         break;
 299                 case 1:
 300                         fields[1].in_handler = arm_jtag_buf_to_8_flip;
 301                         break;
 302         }
 303         fields[1].in_handler_priv = in;
 304         fields[1].in_check_value = NULL;
 305         fields[1].in_check_mask = NULL;
 306
 307         jtag_add_dr_scan(2, fields, -1, NULL);
 308
 309         jtag_add_runtest(0, -1);
 310
 311 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 312 {
 313                 jtag_execute_queue();
 314
 315                 if (in)
 316                 {
 317                         DEBUG("in: 0x%8.8x", *in);
 318                 }
 319                 else
 320                 {
 321                         ERROR("BUG: called with in == NULL");
 322                 }
 323 }
 324 #endif
 325
 326         return ERROR_OK;
 327 }
 328
 329 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 330 {
 331         /* get pointers to arch-specific information */
 332         armv4_5_common_t *armv4_5 = target->arch_info;
 333         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 334         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 335
 336         /* save r0 before using it and put system in ARM state
 337          * to allow common handling of ARM and THUMB debugging */
 338
 339         /* fetch STR r0, [r0] */
 340         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 341         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 342         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 343         /* nothing fetched, STR r0, [r0] in Execute (2) */
 344         arm7tdmi_clock_data_in(jtag_info, r0);
 345
 346         /* MOV r0, r15 fetched, STR in Decode */
 347         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
 348         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 349         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 350         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 351         /* nothing fetched, STR r0, [r0] in Execute (2) */
 352         arm7tdmi_clock_data_in(jtag_info, pc);
 353
 354         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 355         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 356         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 357         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 358         /* nothing fetched, data for LDR r0, [PC, #0] */
 359         arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
 360         /* nothing fetched, data from previous cycle is written to register */
 361         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 362
 363         /* fetch BX */
 364         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
 365         /* NOP fetched, BX in Decode, MOV in Execute */
 366         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 367         /* NOP fetched, BX in Execute (1) */
 368         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 369
 370         jtag_execute_queue();
 371
 372         /* fix program counter:
 373          * MOV r0, r15 was the 4th instruction (+6)
 374          * reading PC in Thumb state gives address of instruction + 4
 375          */
 376         *pc -= 0xa;
 377
 378 }
 379
 380 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 381 {
 382         int i;
 383         /* get pointers to arch-specific information */
 384         armv4_5_common_t *armv4_5 = target->arch_info;
 385         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 386         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 387
 388         /* STMIA r0-15, [r0] at debug speed
 389          * register values will start to appear on 4th DCLK
 390          */
 391         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 392
 393         /* fetch NOP, STM in DECODE stage */
 394         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 395         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 396         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 397
 398         for (i = 0; i <= 15; i++)
 399         {
 400                 if (mask & (1 << i))
 401                         /* nothing fetched, STM still in EXECUTE (1+i cycle) */
 402                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 403         }
 404
 405 }
 406
 407 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 408 {
 409         int i;
 410         /* get pointers to arch-specific information */
 411         armv4_5_common_t *armv4_5 = target->arch_info;
 412         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 413         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 414         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 415         u32 *buf_u32 = buffer;
 416         u16 *buf_u16 = buffer;
 417         u8 *buf_u8 = buffer;
 418
 419         /* STMIA r0-15, [r0] at debug speed
 420          * register values will start to appear on 4th DCLK
 421          */
 422         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 423
 424         /* fetch NOP, STM in DECODE stage */
 425         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 426         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 427         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 428
 429         for (i = 0; i <= 15; i++)
 430         {
 431                 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
 432                 if (mask & (1 << i))
 433                 {
 434                         switch (size)
 435                         {
 436                                 case 4:
 437                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 438                                         break;
 439                                 case 2:
 440                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 441                                         break;
 442                                 case 1:
 443                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 444                                         break;
 445                         }
 446                 }
 447         }
 448
 449 }
 450
 451 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 452 {
 453         /* get pointers to arch-specific information */
 454         armv4_5_common_t *armv4_5 = target->arch_info;
 455         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 456         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 457
 458         /* MRS r0, cpsr */
 459         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
 460
 461         /* STR r0, [r15] */
 462         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
 463         /* fetch NOP, STR in DECODE stage */
 464         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 465         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 466         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 467         /* nothing fetched, STR still in EXECUTE (2nd cycle) */
 468         arm7tdmi_clock_data_in(jtag_info, xpsr);
 469
 470 }
 471
 472 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 473 {
 474         /* get pointers to arch-specific information */
 475         armv4_5_common_t *armv4_5 = target->arch_info;
 476         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 477         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 478
 479         DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 480
 481         /* MSR1 fetched */
 482         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
 483         /* MSR2 fetched, MSR1 in DECODE */
 484         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
 485         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 486         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
 487         /* nothing fetched, MSR1 in EXECUTE (2) */
 488         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 489         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 490         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
 491         /* nothing fetched, MSR2 in EXECUTE (2) */
 492         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 493         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 494         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 495         /* nothing fetched, MSR3 in EXECUTE (2) */
 496         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 497         /* NOP fetched, MSR4 in EXECUTE (1) */
 498         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 499         /* nothing fetched, MSR4 in EXECUTE (2) */
 500         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 501 }
 502
 503 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 504 {
 505         /* get pointers to arch-specific information */
 506         armv4_5_common_t *armv4_5 = target->arch_info;
 507         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 508         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 509
 510         DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 511
 512         /* MSR fetched */
 513         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
 514         /* NOP fetched, MSR in DECODE */
 515         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 516         /* NOP fetched, MSR in EXECUTE (1) */
 517         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 518         /* nothing fetched, MSR in EXECUTE (2) */
 519         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 520
 521 }
 522
 523 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 524 {
 525         int i;
 526         /* get pointers to arch-specific information */
 527         armv4_5_common_t *armv4_5 = target->arch_info;
 528         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 529         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 530
 531         /* LDMIA r0-15, [r0] at debug speed
 532         * register values will start to appear on 4th DCLK
 533         */
 534         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 535
 536         /* fetch NOP, LDM in DECODE stage */
 537         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 538         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 539         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 540
 541         for (i = 0; i <= 15; i++)
 542         {
 543                 if (mask & (1 << i))
 544                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 545                         arm7tdmi_clock_out(jtag_info, core_regs[i], NULL, 0);
 546         }
 547         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 548
 549 }
 550
 551 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
 552 {
 553         /* get pointers to arch-specific information */
 554         armv4_5_common_t *armv4_5 = target->arch_info;
 555         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 556         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 557
 558         /* put system-speed load-multiple into the pipeline */
 559         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 560         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 561         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
 562
 563 }
 564
 565 void arm7tdmi_load_hword_reg(target_t *target, int num)
 566 {
 567         /* get pointers to arch-specific information */
 568         armv4_5_common_t *armv4_5 = target->arch_info;
 569         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 570         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 571
 572         /* put system-speed load half-word into the pipeline */
 573         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 574         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 575         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
 576
 577 }
 578
 579 void arm7tdmi_load_byte_reg(target_t *target, int num)
 580 {
 581         /* get pointers to arch-specific information */
 582         armv4_5_common_t *armv4_5 = target->arch_info;
 583         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 584         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 585
 586         /* put system-speed load byte into the pipeline */
 587         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 588         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 589         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 590
 591 }
 592
 593 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
 594 {
 595         /* get pointers to arch-specific information */
 596         armv4_5_common_t *armv4_5 = target->arch_info;
 597         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 598         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 599
 600         /* put system-speed store-multiple into the pipeline */
 601         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 602         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 603         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
 604
 605 }
 606
 607 void arm7tdmi_store_hword_reg(target_t *target, int num)
 608 {
 609         /* get pointers to arch-specific information */
 610         armv4_5_common_t *armv4_5 = target->arch_info;
 611         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 612         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 613
 614         /* put system-speed store half-word into the pipeline */
 615         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 616         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 617         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
 618
 619 }
 620
 621 void arm7tdmi_store_byte_reg(target_t *target, int num)
 622 {
 623         /* get pointers to arch-specific information */
 624         armv4_5_common_t *armv4_5 = target->arch_info;
 625         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 626         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 627
 628         /* put system-speed store byte into the pipeline */
 629         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 630         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 631         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 632
 633 }
 634
 635 void arm7tdmi_write_pc(target_t *target, u32 pc)
 636 {
 637         /* get pointers to arch-specific information */
 638         armv4_5_common_t *armv4_5 = target->arch_info;
 639         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 640         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 641
 642         /* LDMIA r0-15, [r0] at debug speed
 643          * register values will start to appear on 4th DCLK
 644          */
 645         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
 646         /* fetch NOP, LDM in DECODE stage */
 647         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 648         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 649         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 650         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
 651         arm7tdmi_clock_out(jtag_info, pc, NULL, 0);
 652         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
 653         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 654         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
 655         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 656         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 657         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 658         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 659         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 660 }
 661
 662 void arm7tdmi_branch_resume(target_t *target)
 663 {
 664         /* get pointers to arch-specific information */
 665         armv4_5_common_t *armv4_5 = target->arch_info;
 666         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 667         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 668
 669         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 670         arm7tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffa, 0), NULL, 0);
 671
 672 }
 673
 674 void arm7tdmi_branch_resume_thumb(target_t *target)
 675 {
 676         DEBUG("-");
 677
 678         /* get pointers to arch-specific information */
 679         armv4_5_common_t *armv4_5 = target->arch_info;
 680         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 681         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 682         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 683
 684         /* LDMIA r0, [r0] at debug speed
 685          * register values will start to appear on 4th DCLK
 686          */
 687         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
 688
 689         /* fetch NOP, LDM in DECODE stage */
 690         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 691         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 692         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 693         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 694         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 695         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 696         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 697
 698         /* Branch and eXchange */
 699         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
 700
 701         embeddedice_read_reg(dbg_stat);
 702
 703         /* fetch NOP, BX in DECODE stage */
 704         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 705
 706         /* target is now in Thumb state */
 707         embeddedice_read_reg(dbg_stat);
 708
 709         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 710         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 711
 712         /* target is now in Thumb state */
 713         embeddedice_read_reg(dbg_stat);
 714
 715         /* load r0 value */
 716         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 717         /* fetch NOP, LDR in Decode */
 718         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 719         /* fetch NOP, LDR in Execute */
 720         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 721         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 722         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 723         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 724         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 725
 726         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 727         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 728
 729         embeddedice_read_reg(dbg_stat);
 730
 731         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 732         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
 733
 734 }
 735
 736 void arm7tdmi_build_reg_cache(target_t *target)
 737 {
 738         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 739         /* get pointers to arch-specific information */
 740         armv4_5_common_t *armv4_5 = target->arch_info;
 741         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 742         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 743
 744         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 745         armv4_5->core_cache = (*cache_p);
 746
 747         (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
 748         arm7_9->eice_cache = (*cache_p)->next;
 749
 750         if (arm7_9->etm_ctx)
 751         {
 752                 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 753                 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
 754         }
 755 }
 756
 757 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 758 {
 759
 760         arm7tdmi_build_reg_cache(target);
 761
 762         return ERROR_OK;
 763
 764 }
 765
 766 int arm7tdmi_quit()
 767 {
 768
 769         return ERROR_OK;
 770 }
 771
 772 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant)
 773 {
 774         armv4_5_common_t *armv4_5;
 775         arm7_9_common_t *arm7_9;
 776
 777         arm7_9 = &arm7tdmi->arm7_9_common;
 778         armv4_5 = &arm7_9->armv4_5_common;
 779
 780         /* prepare JTAG information for the new target */
 781         arm7_9->jtag_info.chain_pos = chain_pos;
 782         arm7_9->jtag_info.scann_size = 4;
 783
 784         /* register arch-specific functions */
 785         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
 786         arm7_9->change_to_arm = arm7tdmi_change_to_arm;
 787         arm7_9->read_core_regs = arm7tdmi_read_core_regs;
 788         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
 789         arm7_9->read_xpsr = arm7tdmi_read_xpsr;
 790
 791         arm7_9->write_xpsr = arm7tdmi_write_xpsr;
 792         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
 793         arm7_9->write_core_regs = arm7tdmi_write_core_regs;
 794
 795         arm7_9->load_word_regs = arm7tdmi_load_word_regs;
 796         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
 797         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
 798
 799         arm7_9->store_word_regs = arm7tdmi_store_word_regs;
 800         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
 801         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
 802
 803         arm7_9->write_pc = arm7tdmi_write_pc;
 804         arm7_9->branch_resume = arm7tdmi_branch_resume;
 805         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
 806
 807         arm7_9->enable_single_step = arm7_9_enable_eice_step;
 808         arm7_9->disable_single_step = arm7_9_disable_eice_step;
 809
 810         arm7_9->pre_debug_entry = NULL;
 811         arm7_9->post_debug_entry = NULL;
 812
 813         arm7_9->pre_restore_context = NULL;
 814         arm7_9->post_restore_context = NULL;
 815
 816         /* initialize arch-specific breakpoint handling */
 817         arm7_9->arm_bkpt = 0xdeeedeee;
 818         arm7_9->thumb_bkpt = 0xdeee;
 819
 820         arm7_9->sw_bkpts_use_wp = 1;
 821         arm7_9->sw_bkpts_enabled = 0;
 822         arm7_9->dbgreq_adjust_pc = 2;
 823         arm7_9->arch_info = arm7tdmi;
 824
 825         arm7tdmi->arch_info = NULL;
 826         arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 827
 828         if (variant)
 829         {
 830                 arm7tdmi->variant = strdup(variant);
 831         }
 832         else
 833         {
 834                 arm7tdmi->variant = strdup("");
 835         }
 836
 837         arm7_9_init_arch_info(target, arm7_9);
 838
 839         return ERROR_OK;
 840 }
 841
 842 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
 843 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 844 {
 845         int chain_pos;
 846         char *variant = NULL;
 847         arm7tdmi_common_t *arm7tdmi = malloc(sizeof(arm7tdmi_common_t));
 848
 849         if (argc < 4)
 850         {
 851                 ERROR("'target arm7tdmi' requires at least one additional argument");
 852                 exit(-1);
 853         }
 854
 855         chain_pos = strtoul(args[3], NULL, 0);
 856
 857         if (argc >= 5)
 858                 variant = args[4];
 859
 860         arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
 861
 862         return ERROR_OK;
 863 }
 864
 865 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 866 {
 867         int retval;
 868
 869         retval = arm7_9_register_commands(cmd_ctx);
 870
 871         return ERROR_OK;
 872
 873 }
 874