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From Michael Bruck
[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35 /* cli handling */
36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
37
38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44
45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm920t_quit();
52 int arm920t_arch_state(struct target_s *target);
53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm920t_soft_reset_halt(struct target_s *target);
56
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
58
59 target_type_t arm920t_target =
60 {
61 .name = "arm920t",
62
63 .poll = arm7_9_poll,
64 .arch_state = arm920t_arch_state,
65
66 .target_request_data = arm7_9_target_request_data,
67
68 .halt = arm7_9_halt,
69 .resume = arm7_9_resume,
70 .step = arm7_9_step,
71
72 .assert_reset = arm7_9_assert_reset,
73 .deassert_reset = arm7_9_deassert_reset,
74 .soft_reset_halt = arm920t_soft_reset_halt,
75 .prepare_reset_halt = arm7_9_prepare_reset_halt,
76
77 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78
79 .read_memory = arm920t_read_memory,
80 .write_memory = arm920t_write_memory,
81 .bulk_write_memory = arm7_9_bulk_write_memory,
82 .checksum_memory = arm7_9_checksum_memory,
83
84 .run_algorithm = armv4_5_run_algorithm,
85
86 .add_breakpoint = arm7_9_add_breakpoint,
87 .remove_breakpoint = arm7_9_remove_breakpoint,
88 .add_watchpoint = arm7_9_add_watchpoint,
89 .remove_watchpoint = arm7_9_remove_watchpoint,
90
91 .register_commands = arm920t_register_commands,
92 .target_command = arm920t_target_command,
93 .init_target = arm920t_init_target,
94 .quit = arm920t_quit
95 };
96
97 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
98 {
99 armv4_5_common_t *armv4_5 = target->arch_info;
100 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
101 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
102 scan_field_t fields[4];
103 u8 access_type_buf = 1;
104 u8 reg_addr_buf = reg_addr & 0x3f;
105 u8 nr_w_buf = 0;
106
107 jtag_add_end_state(TAP_RTI);
108 arm_jtag_scann(jtag_info, 0xf);
109 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
110
111 fields[0].device = jtag_info->chain_pos;
112 fields[0].num_bits = 1;
113 fields[0].out_value = &access_type_buf;
114 fields[0].out_mask = NULL;
115 fields[0].in_value = NULL;
116 fields[0].in_check_value = NULL;
117 fields[0].in_check_mask = NULL;
118 fields[0].in_handler = NULL;
119 fields[0].in_handler_priv = NULL;
120
121 fields[1].device = jtag_info->chain_pos;
122 fields[1].num_bits = 32;
123 fields[1].out_value = NULL;
124 fields[1].out_mask = NULL;
125 fields[1].in_value = NULL;
126 fields[1].in_check_value = NULL;
127 fields[1].in_check_mask = NULL;
128 fields[1].in_handler = NULL;
129 fields[1].in_handler_priv = NULL;
130
131 fields[2].device = jtag_info->chain_pos;
132 fields[2].num_bits = 6;
133 fields[2].out_value = &reg_addr_buf;
134 fields[2].out_mask = NULL;
135 fields[2].in_value = NULL;
136 fields[2].in_check_value = NULL;
137 fields[2].in_check_mask = NULL;
138 fields[2].in_handler = NULL;
139 fields[2].in_handler_priv = NULL;
140
141 fields[3].device = jtag_info->chain_pos;
142 fields[3].num_bits = 1;
143 fields[3].out_value = &nr_w_buf;
144 fields[3].out_mask = NULL;
145 fields[3].in_value = NULL;
146 fields[3].in_check_value = NULL;
147 fields[3].in_check_mask = NULL;
148 fields[3].in_handler = NULL;
149 fields[3].in_handler_priv = NULL;
150
151 jtag_add_dr_scan(4, fields, -1);
152
153 fields[1].in_handler_priv = value;
154 fields[1].in_handler = arm_jtag_buf_to_u32;
155
156 jtag_add_dr_scan(4, fields, -1);
157
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 jtag_execute_queue();
160 DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
161 #endif
162
163 return ERROR_OK;
164 }
165
166 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
167 {
168 armv4_5_common_t *armv4_5 = target->arch_info;
169 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
170 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
171 scan_field_t fields[4];
172 u8 access_type_buf = 1;
173 u8 reg_addr_buf = reg_addr & 0x3f;
174 u8 nr_w_buf = 1;
175 u8 value_buf[4];
176
177 buf_set_u32(value_buf, 0, 32, value);
178
179 jtag_add_end_state(TAP_RTI);
180 arm_jtag_scann(jtag_info, 0xf);
181 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
182
183 fields[0].device = jtag_info->chain_pos;
184 fields[0].num_bits = 1;
185 fields[0].out_value = &access_type_buf;
186 fields[0].out_mask = NULL;
187 fields[0].in_value = NULL;
188 fields[0].in_check_value = NULL;
189 fields[0].in_check_mask = NULL;
190 fields[0].in_handler = NULL;
191 fields[0].in_handler_priv = NULL;
192
193 fields[1].device = jtag_info->chain_pos;
194 fields[1].num_bits = 32;
195 fields[1].out_value = value_buf;
196 fields[1].out_mask = NULL;
197 fields[1].in_value = NULL;
198 fields[1].in_check_value = NULL;
199 fields[1].in_check_mask = NULL;
200 fields[1].in_handler = NULL;
201 fields[1].in_handler_priv = NULL;
202
203 fields[2].device = jtag_info->chain_pos;
204 fields[2].num_bits = 6;
205 fields[2].out_value = &reg_addr_buf;
206 fields[2].out_mask = NULL;
207 fields[2].in_value = NULL;
208 fields[2].in_check_value = NULL;
209 fields[2].in_check_mask = NULL;
210 fields[2].in_handler = NULL;
211 fields[2].in_handler_priv = NULL;
212
213 fields[3].device = jtag_info->chain_pos;
214 fields[3].num_bits = 1;
215 fields[3].out_value = &nr_w_buf;
216 fields[3].out_mask = NULL;
217 fields[3].in_value = NULL;
218 fields[3].in_check_value = NULL;
219 fields[3].in_check_mask = NULL;
220 fields[3].in_handler = NULL;
221 fields[3].in_handler_priv = NULL;
222
223 jtag_add_dr_scan(4, fields, -1);
224
225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
226 DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
227 #endif
228
229 return ERROR_OK;
230 }
231
232 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
233 {
234 armv4_5_common_t *armv4_5 = target->arch_info;
235 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
236 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
237 scan_field_t fields[4];
238 u8 access_type_buf = 0; /* interpreted access */
239 u8 reg_addr_buf = 0x0;
240 u8 nr_w_buf = 0;
241 u8 cp15_opcode_buf[4];
242
243 jtag_add_end_state(TAP_RTI);
244 arm_jtag_scann(jtag_info, 0xf);
245 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
246
247 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
248
249 fields[0].device = jtag_info->chain_pos;
250 fields[0].num_bits = 1;
251 fields[0].out_value = &access_type_buf;
252 fields[0].out_mask = NULL;
253 fields[0].in_value = NULL;
254 fields[0].in_check_value = NULL;
255 fields[0].in_check_mask = NULL;
256 fields[0].in_handler = NULL;
257 fields[0].in_handler_priv = NULL;
258
259 fields[1].device = jtag_info->chain_pos;
260 fields[1].num_bits = 32;
261 fields[1].out_value = cp15_opcode_buf;
262 fields[1].out_mask = NULL;
263 fields[1].in_value = NULL;
264 fields[1].in_check_value = NULL;
265 fields[1].in_check_mask = NULL;
266 fields[1].in_handler = NULL;
267 fields[1].in_handler_priv = NULL;
268
269 fields[2].device = jtag_info->chain_pos;
270 fields[2].num_bits = 6;
271 fields[2].out_value = &reg_addr_buf;
272 fields[2].out_mask = NULL;
273 fields[2].in_value = NULL;
274 fields[2].in_check_value = NULL;
275 fields[2].in_check_mask = NULL;
276 fields[2].in_handler = NULL;
277 fields[2].in_handler_priv = NULL;
278
279 fields[3].device = jtag_info->chain_pos;
280 fields[3].num_bits = 1;
281 fields[3].out_value = &nr_w_buf;
282 fields[3].out_mask = NULL;
283 fields[3].in_value = NULL;
284 fields[3].in_check_value = NULL;
285 fields[3].in_check_mask = NULL;
286 fields[3].in_handler = NULL;
287 fields[3].in_handler_priv = NULL;
288
289 jtag_add_dr_scan(4, fields, -1);
290
291 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
293 arm7_9_execute_sys_speed(target);
294
295 if (jtag_execute_queue() != ERROR_OK)
296 {
297 ERROR("failed executing JTAG queue, exiting");
298 exit(-1);
299 }
300
301 return ERROR_OK;
302 }
303
304 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
305 {
306 armv4_5_common_t *armv4_5 = target->arch_info;
307 u32* regs_p[1];
308 u32 regs[2];
309 u32 cp15c15 = 0x0;
310
311 /* load address into R1 */
312 regs[1] = address;
313 arm9tdmi_write_core_regs(target, 0x2, regs);
314
315 /* read-modify-write CP15 test state register
316 * to enable interpreted access mode */
317 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
318 jtag_execute_queue();
319 cp15c15 |= 1; /* set interpret mode */
320 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
321
322 /* execute CP15 instruction and ARM load (reading from coprocessor) */
323 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
324
325 /* disable interpreted access mode */
326 cp15c15 &= ~1U; /* clear interpret mode */
327 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
328
329 /* retrieve value from R0 */
330 regs_p[0] = value;
331 arm9tdmi_read_core_regs(target, 0x1, regs_p);
332 jtag_execute_queue();
333
334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
335 DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
336 #endif
337
338 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
339 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
340
341 return ERROR_OK;
342 }
343
344 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
345 {
346 u32 cp15c15 = 0x0;
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 u32 regs[2];
349
350 /* load value, address into R0, R1 */
351 regs[0] = value;
352 regs[1] = address;
353 arm9tdmi_write_core_regs(target, 0x3, regs);
354
355 /* read-modify-write CP15 test state register
356 * to enable interpreted access mode */
357 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
358 jtag_execute_queue();
359 cp15c15 |= 1; /* set interpret mode */
360 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
361
362 /* execute CP15 instruction and ARM store (writing to coprocessor) */
363 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
364
365 /* disable interpreted access mode */
366 cp15c15 &= ~1U; /* set interpret mode */
367 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
368
369 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
370 DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
371 #endif
372
373 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
374 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
375
376 return ERROR_OK;
377 }
378
379 u32 arm920t_get_ttb(target_t *target)
380 {
381 int retval;
382 u32 ttb = 0x0;
383
384 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
385 return retval;
386
387 return ttb;
388 }
389
390 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
391 {
392 u32 cp15_control;
393
394 /* read cp15 control register */
395 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
396 jtag_execute_queue();
397
398 if (mmu)
399 cp15_control &= ~0x1U;
400
401 if (d_u_cache)
402 cp15_control &= ~0x4U;
403
404 if (i_cache)
405 cp15_control &= ~0x1000U;
406
407 arm920t_write_cp15_physical(target, 0x2, cp15_control);
408 }
409
410 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
411 {
412 u32 cp15_control;
413
414 /* read cp15 control register */
415 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
416 jtag_execute_queue();
417
418 if (mmu)
419 cp15_control |= 0x1U;
420
421 if (d_u_cache)
422 cp15_control |= 0x4U;
423
424 if (i_cache)
425 cp15_control |= 0x1000U;
426
427 arm920t_write_cp15_physical(target, 0x2, cp15_control);
428 }
429
430 void arm920t_post_debug_entry(target_t *target)
431 {
432 u32 cp15c15;
433 armv4_5_common_t *armv4_5 = target->arch_info;
434 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
435 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
436 arm920t_common_t *arm920t = arm9tdmi->arch_info;
437
438 /* examine cp15 control reg */
439 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
440 jtag_execute_queue();
441 DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
442
443 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
444 {
445 u32 cache_type_reg;
446 /* identify caches */
447 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
448 jtag_execute_queue();
449 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
450 }
451
452 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
453 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
454 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
455
456 /* save i/d fault status and address register */
457 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
458 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
459 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
460 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
461
462 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
463 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
464
465 if (arm920t->preserve_cache)
466 {
467 /* read-modify-write CP15 test state register
468 * to disable I/D-cache linefills */
469 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
470 jtag_execute_queue();
471 cp15c15 |= 0x600;
472 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
473 }
474 }
475
476 void arm920t_pre_restore_context(target_t *target)
477 {
478 u32 cp15c15;
479 armv4_5_common_t *armv4_5 = target->arch_info;
480 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
481 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
482 arm920t_common_t *arm920t = arm9tdmi->arch_info;
483
484 /* restore i/d fault status and address register */
485 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
486 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
487 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
488 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
489
490 /* read-modify-write CP15 test state register
491 * to reenable I/D-cache linefills */
492 if (arm920t->preserve_cache)
493 {
494 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
495 jtag_execute_queue();
496 cp15c15 &= ~0x600U;
497 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
498 }
499 }
500
501 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
502 {
503 armv4_5_common_t *armv4_5 = target->arch_info;
504 arm7_9_common_t *arm7_9;
505 arm9tdmi_common_t *arm9tdmi;
506 arm920t_common_t *arm920t;
507
508 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
509 {
510 return -1;
511 }
512
513 arm7_9 = armv4_5->arch_info;
514 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
515 {
516 return -1;
517 }
518
519 arm9tdmi = arm7_9->arch_info;
520 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
521 {
522 return -1;
523 }
524
525 arm920t = arm9tdmi->arch_info;
526 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
527 {
528 return -1;
529 }
530
531 *armv4_5_p = armv4_5;
532 *arm7_9_p = arm7_9;
533 *arm9tdmi_p = arm9tdmi;
534 *arm920t_p = arm920t;
535
536 return ERROR_OK;
537 }
538
539 int arm920t_arch_state(struct target_s *target)
540 {
541 armv4_5_common_t *armv4_5 = target->arch_info;
542 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
543 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
544 arm920t_common_t *arm920t = arm9tdmi->arch_info;
545
546 char *state[] =
547 {
548 "disabled", "enabled"
549 };
550
551 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
552 {
553 ERROR("BUG: called for a non-ARMv4/5 target");
554 exit(-1);
555 }
556
557 USER( "target halted in %s state due to %s, current mode: %s\n"
558 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
559 "MMU: %s, D-Cache: %s, I-Cache: %s",
560 armv4_5_state_strings[armv4_5->core_state],
561 target_debug_reason_strings[target->debug_reason],
562 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
563 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
564 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
565 state[arm920t->armv4_5_mmu.mmu_enabled],
566 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
567 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
568
569 return ERROR_OK;
570 }
571
572 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
573 {
574 int retval;
575
576 retval = arm7_9_read_memory(target, address, size, count, buffer);
577
578 return retval;
579 }
580
581 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
582 {
583 int retval;
584 armv4_5_common_t *armv4_5 = target->arch_info;
585 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
586 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
587 arm920t_common_t *arm920t = arm9tdmi->arch_info;
588
589 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
590 return retval;
591
592 if (((size == 4) || (size == 2)) && (count == 1))
593 {
594 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
595 {
596 DEBUG("D-Cache enabled, writing through to main memory");
597 u32 pa, cb, ap;
598 int type, domain;
599
600 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
601 if (type == -1)
602 return ERROR_OK;
603 /* cacheable & bufferable means write-back region */
604 if (cb == 3)
605 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
606 }
607
608 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
609 {
610 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
611 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
612 }
613 }
614
615 return retval;
616 }
617
618 int arm920t_soft_reset_halt(struct target_s *target)
619 {
620 armv4_5_common_t *armv4_5 = target->arch_info;
621 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
622 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
623 arm920t_common_t *arm920t = arm9tdmi->arch_info;
624 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
625
626 if (target->state == TARGET_RUNNING)
627 {
628 target->type->halt(target);
629 }
630
631 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
632 {
633 embeddedice_read_reg(dbg_stat);
634 jtag_execute_queue();
635 }
636
637 target->state = TARGET_HALTED;
638
639 /* SVC, ARM state, IRQ and FIQ disabled */
640 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
641 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
642 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
643
644 /* start fetching from 0x0 */
645 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
646 armv4_5->core_cache->reg_list[15].dirty = 1;
647 armv4_5->core_cache->reg_list[15].valid = 1;
648
649 armv4_5->core_mode = ARMV4_5_MODE_SVC;
650 armv4_5->core_state = ARMV4_5_STATE_ARM;
651
652 arm920t_disable_mmu_caches(target, 1, 1, 1);
653 arm920t->armv4_5_mmu.mmu_enabled = 0;
654 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
655 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
656
657 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
658
659 return ERROR_OK;
660 }
661
662 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
663 {
664 arm9tdmi_init_target(cmd_ctx, target);
665
666 return ERROR_OK;
667
668 }
669
670 int arm920t_quit()
671 {
672
673 return ERROR_OK;
674 }
675
676 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
677 {
678 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
679 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
680
681 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
682 */
683 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
684
685 arm9tdmi->arch_info = arm920t;
686 arm920t->common_magic = ARM920T_COMMON_MAGIC;
687
688 arm7_9->post_debug_entry = arm920t_post_debug_entry;
689 arm7_9->pre_restore_context = arm920t_pre_restore_context;
690
691 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
692 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
693 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
694 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
695 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
696 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
697 arm920t->armv4_5_mmu.has_tiny_pages = 1;
698 arm920t->armv4_5_mmu.mmu_enabled = 0;
699
700 /* disabling linefills leads to lockups, so keep them enabled for now
701 * this doesn't affect correctness, but might affect timing issues, if
702 * important data is evicted from the cache during the debug session
703 * */
704 arm920t->preserve_cache = 0;
705
706 /* override hw single-step capability from ARM9TDMI */
707 arm7_9->has_single_step = 1;
708
709 return ERROR_OK;
710 }
711
712 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
713 {
714 int chain_pos;
715 char *variant = NULL;
716 arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
717
718 if (argc < 4)
719 {
720 ERROR("'target arm920t' requires at least one additional argument");
721 exit(-1);
722 }
723
724 chain_pos = strtoul(args[3], NULL, 0);
725
726 if (argc >= 5)
727 variant = args[4];
728
729 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
730
731 arm920t_init_arch_info(target, arm920t, chain_pos, variant);
732
733 return ERROR_OK;
734 }
735
736 int arm920t_register_commands(struct command_context_s *cmd_ctx)
737 {
738 int retval;
739 command_t *arm920t_cmd;
740
741
742 retval = arm9tdmi_register_commands(cmd_ctx);
743
744 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
745
746 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
747 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
748 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
749 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
750
751 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
752 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
753 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
754
755 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
756 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
757 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
758
759 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
760 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
761
762 return ERROR_OK;
763 }
764
765 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
766 {
767 target_t *target = get_current_target(cmd_ctx);
768 armv4_5_common_t *armv4_5;
769 arm7_9_common_t *arm7_9;
770 arm9tdmi_common_t *arm9tdmi;
771 arm920t_common_t *arm920t;
772 arm_jtag_t *jtag_info;
773 u32 cp15c15;
774 u32 cp15_ctrl, cp15_ctrl_saved;
775 u32 regs[16];
776 u32 *regs_p[16];
777 u32 C15_C_D_Ind, C15_C_I_Ind;
778 int i;
779 FILE *output;
780 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
781 int segment, index;
782
783 if (argc != 1)
784 {
785 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
786 return ERROR_OK;
787 }
788
789 if ((output = fopen(args[0], "w")) == NULL)
790 {
791 DEBUG("error opening cache content file");
792 return ERROR_OK;
793 }
794
795 for (i = 0; i < 16; i++)
796 regs_p[i] = &regs[i];
797
798 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
799 {
800 command_print(cmd_ctx, "current target isn't an ARM920t target");
801 return ERROR_OK;
802 }
803
804 jtag_info = &arm7_9->jtag_info;
805
806 /* disable MMU and Caches */
807 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
808 jtag_execute_queue();
809 cp15_ctrl_saved = cp15_ctrl;
810 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
811 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
812
813 /* read CP15 test state register */
814 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
815 jtag_execute_queue();
816
817 /* read DCache content */
818 fprintf(output, "DCache:\n");
819
820 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
821 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
822 {
823 fprintf(output, "\nsegment: %i\n----------", segment);
824
825 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
826 regs[0] = 0x0 | (segment << 5);
827 arm9tdmi_write_core_regs(target, 0x1, regs);
828
829 /* set interpret mode */
830 cp15c15 |= 0x1;
831 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
832
833 /* D CAM Read, loads current victim into C15.C.D.Ind */
834 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
835
836 /* read current victim */
837 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
838
839 /* clear interpret mode */
840 cp15c15 &= ~0x1;
841 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
842
843 for (index = 0; index < 64; index++)
844 {
845 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
846 regs[0] = 0x0 | (segment << 5) | (index << 26);
847 arm9tdmi_write_core_regs(target, 0x1, regs);
848
849 /* set interpret mode */
850 cp15c15 |= 0x1;
851 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
852
853 /* Write DCache victim */
854 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
855
856 /* Read D RAM */
857 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
858
859 /* Read D CAM */
860 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
861
862 /* clear interpret mode */
863 cp15c15 &= ~0x1;
864 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
865
866 /* read D RAM and CAM content */
867 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
868 jtag_execute_queue();
869
870 d_cache[segment][index].cam = regs[9];
871
872 /* mask LFSR[6] */
873 regs[9] &= 0xfffffffe;
874 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
875
876 for (i = 1; i < 9; i++)
877 {
878 d_cache[segment][index].data[i] = regs[i];
879 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
880 }
881
882 }
883
884 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
885 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
886 arm9tdmi_write_core_regs(target, 0x1, regs);
887
888 /* set interpret mode */
889 cp15c15 |= 0x1;
890 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
891
892 /* Write DCache victim */
893 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
894
895 /* clear interpret mode */
896 cp15c15 &= ~0x1;
897 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
898 }
899
900 /* read ICache content */
901 fprintf(output, "ICache:\n");
902
903 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
904 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
905 {
906 fprintf(output, "segment: %i\n----------", segment);
907
908 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
909 regs[0] = 0x0 | (segment << 5);
910 arm9tdmi_write_core_regs(target, 0x1, regs);
911
912 /* set interpret mode */
913 cp15c15 |= 0x1;
914 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
915
916 /* I CAM Read, loads current victim into C15.C.I.Ind */
917 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
918
919 /* read current victim */
920 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
921
922 /* clear interpret mode */
923 cp15c15 &= ~0x1;
924 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
925
926 for (index = 0; index < 64; index++)
927 {
928 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
929 regs[0] = 0x0 | (segment << 5) | (index << 26);
930 arm9tdmi_write_core_regs(target, 0x1, regs);
931
932 /* set interpret mode */
933 cp15c15 |= 0x1;
934 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
935
936 /* Write ICache victim */
937 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
938
939 /* Read I RAM */
940 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
941
942 /* Read I CAM */
943 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
944
945 /* clear interpret mode */
946 cp15c15 &= ~0x1;
947 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
948
949 /* read I RAM and CAM content */
950 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
951 jtag_execute_queue();
952
953 i_cache[segment][index].cam = regs[9];
954
955 /* mask LFSR[6] */
956 regs[9] &= 0xfffffffe;
957 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
958
959 for (i = 1; i < 9; i++)
960 {
961 i_cache[segment][index].data[i] = regs[i];
962 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
963 }
964
965 }
966
967
968 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
969 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
970 arm9tdmi_write_core_regs(target, 0x1, regs);
971
972 /* set interpret mode */
973 cp15c15 |= 0x1;
974 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
975
976 /* Write ICache victim */
977 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
978
979 /* clear interpret mode */
980 cp15c15 &= ~0x1;
981 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
982 }
983
984 /* restore CP15 MMU and Cache settings */
985 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
986
987 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
988
989 fclose(output);
990
991 /* mark registers dirty. */
992 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
993 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
994 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
995 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
996 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
997 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
998 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
999 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1000 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1001 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1002
1003 return ERROR_OK;
1004 }
1005
1006 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1007 {
1008 target_t *target = get_current_target(cmd_ctx);
1009 armv4_5_common_t *armv4_5;
1010 arm7_9_common_t *arm7_9;
1011 arm9tdmi_common_t *arm9tdmi;
1012 arm920t_common_t *arm920t;
1013 arm_jtag_t *jtag_info;
1014 u32 cp15c15;
1015 u32 cp15_ctrl, cp15_ctrl_saved;
1016 u32 regs[16];
1017 u32 *regs_p[16];
1018 int i;
1019 FILE *output;
1020 u32 Dlockdown, Ilockdown;
1021 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1022 int victim;
1023
1024 if (argc != 1)
1025 {
1026 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1027 return ERROR_OK;
1028 }
1029
1030 if ((output = fopen(args[0], "w")) == NULL)
1031 {
1032 DEBUG("error opening mmu content file");
1033 return ERROR_OK;
1034 }
1035
1036 for (i = 0; i < 16; i++)
1037 regs_p[i] = &regs[i];
1038
1039 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1040 {
1041 command_print(cmd_ctx, "current target isn't an ARM920t target");
1042 return ERROR_OK;
1043 }
1044
1045 jtag_info = &arm7_9->jtag_info;
1046
1047 /* disable MMU and Caches */
1048 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1049 jtag_execute_queue();
1050 cp15_ctrl_saved = cp15_ctrl;
1051 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1052 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1053
1054 /* read CP15 test state register */
1055 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1056 jtag_execute_queue();
1057
1058 /* prepare reading D TLB content
1059 * */
1060
1061 /* set interpret mode */
1062 cp15c15 |= 0x1;
1063 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1064
1065 /* Read D TLB lockdown */
1066 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1067
1068 /* clear interpret mode */
1069 cp15c15 &= ~0x1;
1070 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1071
1072 /* read D TLB lockdown stored to r1 */
1073 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1074 jtag_execute_queue();
1075 Dlockdown = regs[1];
1076
1077 for (victim = 0; victim < 64; victim += 8)
1078 {
1079 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1080 * base remains unchanged, victim goes through entries 0 to 63 */
1081 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1082 arm9tdmi_write_core_regs(target, 0x2, regs);
1083
1084 /* set interpret mode */
1085 cp15c15 |= 0x1;
1086 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1087
1088 /* Write D TLB lockdown */
1089 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1090
1091 /* Read D TLB CAM */
1092 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1093
1094 /* clear interpret mode */
1095 cp15c15 &= ~0x1;
1096 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1097
1098 /* read D TLB CAM content stored to r2-r9 */
1099 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1100 jtag_execute_queue();
1101
1102 for (i = 0; i < 8; i++)
1103 d_tlb[victim + i].cam = regs[i + 2];
1104 }
1105
1106 for (victim = 0; victim < 64; victim++)
1107 {
1108 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1109 * base remains unchanged, victim goes through entries 0 to 63 */
1110 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1111 arm9tdmi_write_core_regs(target, 0x2, regs);
1112
1113 /* set interpret mode */
1114 cp15c15 |= 0x1;
1115 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1116
1117 /* Write D TLB lockdown */
1118 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1119
1120 /* Read D TLB RAM1 */
1121 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1122
1123 /* Read D TLB RAM2 */
1124 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1125
1126 /* clear interpret mode */
1127 cp15c15 &= ~0x1;
1128 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1129
1130 /* read D TLB RAM content stored to r2 and r3 */
1131 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1132 jtag_execute_queue();
1133
1134 d_tlb[victim].ram1 = regs[2];
1135 d_tlb[victim].ram2 = regs[3];
1136 }
1137
1138 /* restore D TLB lockdown */
1139 regs[1] = Dlockdown;
1140 arm9tdmi_write_core_regs(target, 0x2, regs);
1141
1142 /* Write D TLB lockdown */
1143 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1144
1145 /* prepare reading I TLB content
1146 * */
1147
1148 /* set interpret mode */
1149 cp15c15 |= 0x1;
1150 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1151
1152 /* Read I TLB lockdown */
1153 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1154
1155 /* clear interpret mode */
1156 cp15c15 &= ~0x1;
1157 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1158
1159 /* read I TLB lockdown stored to r1 */
1160 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1161 jtag_execute_queue();
1162 Ilockdown = regs[1];
1163
1164 for (victim = 0; victim < 64; victim += 8)
1165 {
1166 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1167 * base remains unchanged, victim goes through entries 0 to 63 */
1168 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1169 arm9tdmi_write_core_regs(target, 0x2, regs);
1170
1171 /* set interpret mode */
1172 cp15c15 |= 0x1;
1173 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1174
1175 /* Write I TLB lockdown */
1176 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1177
1178 /* Read I TLB CAM */
1179 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1180
1181 /* clear interpret mode */
1182 cp15c15 &= ~0x1;
1183 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1184
1185 /* read I TLB CAM content stored to r2-r9 */
1186 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1187 jtag_execute_queue();
1188
1189 for (i = 0; i < 8; i++)
1190 i_tlb[i + victim].cam = regs[i + 2];
1191 }
1192
1193 for (victim = 0; victim < 64; victim++)
1194 {
1195 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1196 * base remains unchanged, victim goes through entries 0 to 63 */
1197 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1198 arm9tdmi_write_core_regs(target, 0x2, regs);
1199
1200 /* set interpret mode */
1201 cp15c15 |= 0x1;
1202 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1203
1204 /* Write I TLB lockdown */
1205 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1206
1207 /* Read I TLB RAM1 */
1208 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1209
1210 /* Read I TLB RAM2 */
1211 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1212
1213 /* clear interpret mode */
1214 cp15c15 &= ~0x1;
1215 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1216
1217 /* read I TLB RAM content stored to r2 and r3 */
1218 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1219 jtag_execute_queue();
1220
1221 i_tlb[victim].ram1 = regs[2];
1222 i_tlb[victim].ram2 = regs[3];
1223 }
1224
1225 /* restore I TLB lockdown */
1226 regs[1] = Ilockdown;
1227 arm9tdmi_write_core_regs(target, 0x2, regs);
1228
1229 /* Write I TLB lockdown */
1230 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1231
1232 /* restore CP15 MMU and Cache settings */
1233 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1234
1235 /* output data to file */
1236 fprintf(output, "D TLB content:\n");
1237 for (i = 0; i < 64; i++)
1238 {
1239 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1240 }
1241
1242 fprintf(output, "\n\nI TLB content:\n");
1243 for (i = 0; i < 64; i++)
1244 {
1245 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1246 }
1247
1248 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1249
1250 fclose(output);
1251
1252 /* mark registers dirty */
1253 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1254 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1255 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1256 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1257 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1258 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1260 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1261 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1262 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1263
1264 return ERROR_OK;
1265 }
1266 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1267 {
1268 int retval;
1269 target_t *target = get_current_target(cmd_ctx);
1270 armv4_5_common_t *armv4_5;
1271 arm7_9_common_t *arm7_9;
1272 arm9tdmi_common_t *arm9tdmi;
1273 arm920t_common_t *arm920t;
1274 arm_jtag_t *jtag_info;
1275
1276 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1277 {
1278 command_print(cmd_ctx, "current target isn't an ARM920t target");
1279 return ERROR_OK;
1280 }
1281
1282 jtag_info = &arm7_9->jtag_info;
1283
1284 if (target->state != TARGET_HALTED)
1285 {
1286 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1287 return ERROR_OK;
1288 }
1289
1290 /* one or more argument, access a single register (write if second argument is given */
1291 if (argc >= 1)
1292 {
1293 int address = strtoul(args[0], NULL, 0);
1294
1295 if (argc == 1)
1296 {
1297 u32 value;
1298 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1299 {
1300 command_print(cmd_ctx, "couldn't access reg %i", address);
1301 return ERROR_OK;
1302 }
1303 jtag_execute_queue();
1304
1305 command_print(cmd_ctx, "%i: %8.8x", address, value);
1306 }
1307 else if (argc == 2)
1308 {
1309 u32 value = strtoul(args[1], NULL, 0);
1310 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1311 {
1312 command_print(cmd_ctx, "couldn't access reg %i", address);
1313 return ERROR_OK;
1314 }
1315 command_print(cmd_ctx, "%i: %8.8x", address, value);
1316 }
1317 }
1318
1319 return ERROR_OK;
1320 }
1321
1322 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1323 {
1324 int retval;
1325 target_t *target = get_current_target(cmd_ctx);
1326 armv4_5_common_t *armv4_5;
1327 arm7_9_common_t *arm7_9;
1328 arm9tdmi_common_t *arm9tdmi;
1329 arm920t_common_t *arm920t;
1330 arm_jtag_t *jtag_info;
1331
1332 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1333 {
1334 command_print(cmd_ctx, "current target isn't an ARM920t target");
1335 return ERROR_OK;
1336 }
1337
1338 jtag_info = &arm7_9->jtag_info;
1339
1340 if (target->state != TARGET_HALTED)
1341 {
1342 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1343 return ERROR_OK;
1344 }
1345
1346 /* one or more argument, access a single register (write if second argument is given */
1347 if (argc >= 1)
1348 {
1349 u32 opcode = strtoul(args[0], NULL, 0);
1350
1351 if (argc == 1)
1352 {
1353 u32 value;
1354 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1355 {
1356 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1357 return ERROR_OK;
1358 }
1359
1360 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1361 }
1362 else if (argc == 2)
1363 {
1364 u32 value = strtoul(args[1], NULL, 0);
1365 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1366 {
1367 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1368 return ERROR_OK;
1369 }
1370 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1371 }
1372 else if (argc == 3)
1373 {
1374 u32 value = strtoul(args[1], NULL, 0);
1375 u32 address = strtoul(args[2], NULL, 0);
1376 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1377 {
1378 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1379 return ERROR_OK;
1380 }
1381 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1382 }
1383 }
1384 else
1385 {
1386 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1387 }
1388
1389 return ERROR_OK;
1390 }
1391
1392 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1393 {
1394 target_t *target = get_current_target(cmd_ctx);
1395 armv4_5_common_t *armv4_5;
1396 arm7_9_common_t *arm7_9;
1397 arm9tdmi_common_t *arm9tdmi;
1398 arm920t_common_t *arm920t;
1399
1400 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1401 {
1402 command_print(cmd_ctx, "current target isn't an ARM920t target");
1403 return ERROR_OK;
1404 }
1405
1406 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1407 }
1408
1409 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1410 {
1411 target_t *target = get_current_target(cmd_ctx);
1412 armv4_5_common_t *armv4_5;
1413 arm7_9_common_t *arm7_9;
1414 arm9tdmi_common_t *arm9tdmi;
1415 arm920t_common_t *arm920t;
1416 arm_jtag_t *jtag_info;
1417
1418 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1419 {
1420 command_print(cmd_ctx, "current target isn't an ARM920t target");
1421 return ERROR_OK;
1422 }
1423
1424 jtag_info = &arm7_9->jtag_info;
1425
1426 if (target->state != TARGET_HALTED)
1427 {
1428 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1429 return ERROR_OK;
1430 }
1431
1432 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1433 }
1434
1435 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1436 {
1437 target_t *target = get_current_target(cmd_ctx);
1438 armv4_5_common_t *armv4_5;
1439 arm7_9_common_t *arm7_9;
1440 arm9tdmi_common_t *arm9tdmi;
1441 arm920t_common_t *arm920t;
1442 arm_jtag_t *jtag_info;
1443
1444 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1445 {
1446 command_print(cmd_ctx, "current target isn't an ARM920t target");
1447 return ERROR_OK;
1448 }
1449
1450 jtag_info = &arm7_9->jtag_info;
1451
1452 if (target->state != TARGET_HALTED)
1453 {
1454 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1455 return ERROR_OK;
1456 }
1457
1458 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1459 }
1460
1461 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1462 {
1463 target_t *target = get_current_target(cmd_ctx);
1464 armv4_5_common_t *armv4_5;
1465 arm7_9_common_t *arm7_9;
1466 arm9tdmi_common_t *arm9tdmi;
1467 arm920t_common_t *arm920t;
1468 arm_jtag_t *jtag_info;
1469
1470 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1471 {
1472 command_print(cmd_ctx, "current target isn't an ARM920t target");
1473 return ERROR_OK;
1474 }
1475
1476 jtag_info = &arm7_9->jtag_info;
1477
1478 if (target->state != TARGET_HALTED)
1479 {
1480 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1481 return ERROR_OK;
1482 }
1483
1484 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1485 }
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