1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
30 #define _DEBUG_INSTRUCTION_EXECUTION_
34 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
36 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
37 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
38 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 /* forward declarations */
44 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
45 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
48 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
49 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
50 int arm920t_soft_reset_halt(struct target_s
*target
);
52 target_type_t arm920t_target
=
57 .arch_state
= arm920t_arch_state
,
60 .resume
= arm7_9_resume
,
63 .assert_reset
= arm7_9_assert_reset
,
64 .deassert_reset
= arm7_9_deassert_reset
,
65 .soft_reset_halt
= arm920t_soft_reset_halt
,
67 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
69 .read_memory
= arm920t_read_memory
,
70 .write_memory
= arm920t_write_memory
,
71 .bulk_write_memory
= arm7_9_bulk_write_memory
,
73 .run_algorithm
= armv4_5_run_algorithm
,
75 .add_breakpoint
= arm7_9_add_breakpoint
,
76 .remove_breakpoint
= arm7_9_remove_breakpoint
,
77 .add_watchpoint
= arm7_9_add_watchpoint
,
78 .remove_watchpoint
= arm7_9_remove_watchpoint
,
80 .register_commands
= arm920t_register_commands
,
81 .target_command
= arm920t_target_command
,
82 .init_target
= arm920t_init_target
,
86 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
88 armv4_5_common_t
*armv4_5
= target
->arch_info
;
89 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
90 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
91 scan_field_t fields
[4];
92 u8 access_type_buf
= 1;
93 u8 reg_addr_buf
= reg_addr
& 0x3f;
96 jtag_add_end_state(TAP_RTI
);
97 arm_jtag_scann(jtag_info
, 0xf);
98 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
100 fields
[0].device
= jtag_info
->chain_pos
;
101 fields
[0].num_bits
= 1;
102 fields
[0].out_value
= &access_type_buf
;
103 fields
[0].out_mask
= NULL
;
104 fields
[0].in_value
= NULL
;
105 fields
[0].in_check_value
= NULL
;
106 fields
[0].in_check_mask
= NULL
;
107 fields
[0].in_handler
= NULL
;
108 fields
[0].in_handler_priv
= NULL
;
110 fields
[1].device
= jtag_info
->chain_pos
;
111 fields
[1].num_bits
= 32;
112 fields
[1].out_value
= NULL
;
113 fields
[1].out_mask
= NULL
;
114 fields
[1].in_value
= NULL
;
115 fields
[1].in_check_value
= NULL
;
116 fields
[1].in_check_mask
= NULL
;
117 fields
[1].in_handler
= NULL
;
118 fields
[1].in_handler_priv
= NULL
;
120 fields
[2].device
= jtag_info
->chain_pos
;
121 fields
[2].num_bits
= 6;
122 fields
[2].out_value
= ®_addr_buf
;
123 fields
[2].out_mask
= NULL
;
124 fields
[2].in_value
= NULL
;
125 fields
[2].in_check_value
= NULL
;
126 fields
[2].in_check_mask
= NULL
;
127 fields
[2].in_handler
= NULL
;
128 fields
[2].in_handler_priv
= NULL
;
130 fields
[3].device
= jtag_info
->chain_pos
;
131 fields
[3].num_bits
= 1;
132 fields
[3].out_value
= &nr_w_buf
;
133 fields
[3].out_mask
= NULL
;
134 fields
[3].in_value
= NULL
;
135 fields
[3].in_check_value
= NULL
;
136 fields
[3].in_check_mask
= NULL
;
137 fields
[3].in_handler
= NULL
;
138 fields
[3].in_handler_priv
= NULL
;
140 jtag_add_dr_scan(4, fields
, -1);
142 fields
[1].in_value
= (u8
*)value
;
144 jtag_add_dr_scan(4, fields
, -1);
149 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
151 armv4_5_common_t
*armv4_5
= target
->arch_info
;
152 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
153 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
154 scan_field_t fields
[4];
155 u8 access_type_buf
= 1;
156 u8 reg_addr_buf
= reg_addr
& 0x3f;
159 jtag_add_end_state(TAP_RTI
);
160 arm_jtag_scann(jtag_info
, 0xf);
161 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
163 fields
[0].device
= jtag_info
->chain_pos
;
164 fields
[0].num_bits
= 1;
165 fields
[0].out_value
= &access_type_buf
;
166 fields
[0].out_mask
= NULL
;
167 fields
[0].in_value
= NULL
;
168 fields
[0].in_check_value
= NULL
;
169 fields
[0].in_check_mask
= NULL
;
170 fields
[0].in_handler
= NULL
;
171 fields
[0].in_handler_priv
= NULL
;
173 fields
[1].device
= jtag_info
->chain_pos
;
174 fields
[1].num_bits
= 32;
175 fields
[1].out_value
= (u8
*)&value
;
176 fields
[1].out_mask
= NULL
;
177 fields
[1].in_value
= NULL
;
178 fields
[1].in_check_value
= NULL
;
179 fields
[1].in_check_mask
= NULL
;
180 fields
[1].in_handler
= NULL
;
181 fields
[1].in_handler_priv
= NULL
;
183 fields
[2].device
= jtag_info
->chain_pos
;
184 fields
[2].num_bits
= 6;
185 fields
[2].out_value
= ®_addr_buf
;
186 fields
[2].out_mask
= NULL
;
187 fields
[2].in_value
= NULL
;
188 fields
[2].in_check_value
= NULL
;
189 fields
[2].in_check_mask
= NULL
;
190 fields
[2].in_handler
= NULL
;
191 fields
[2].in_handler_priv
= NULL
;
193 fields
[3].device
= jtag_info
->chain_pos
;
194 fields
[3].num_bits
= 1;
195 fields
[3].out_value
= &nr_w_buf
;
196 fields
[3].out_mask
= NULL
;
197 fields
[3].in_value
= NULL
;
198 fields
[3].in_check_value
= NULL
;
199 fields
[3].in_check_mask
= NULL
;
200 fields
[3].in_handler
= NULL
;
201 fields
[3].in_handler_priv
= NULL
;
203 jtag_add_dr_scan(4, fields
, -1);
208 int arm920t_read_cp15_interpreted(target_t
*target
, u32 opcode
, u32
*value
)
211 scan_field_t fields
[4];
212 u8 access_type_buf
= 0; /* interpreted access */
213 u8 reg_addr_buf
= 0x0;
215 armv4_5_common_t
*armv4_5
= target
->arch_info
;
216 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
217 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
220 /* read-modify-write CP15 test state register
221 * to enable interpreted access mode */
222 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
223 jtag_execute_queue();
224 cp15c15
|= 1; /* set interpret mode */
225 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
227 jtag_add_end_state(TAP_RTI
);
228 arm_jtag_scann(jtag_info
, 0xf);
229 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
231 fields
[0].device
= jtag_info
->chain_pos
;
232 fields
[0].num_bits
= 1;
233 fields
[0].out_value
= &access_type_buf
;
234 fields
[0].out_mask
= NULL
;
235 fields
[0].in_value
= NULL
;
236 fields
[0].in_check_value
= NULL
;
237 fields
[0].in_check_mask
= NULL
;
238 fields
[0].in_handler
= NULL
;
239 fields
[0].in_handler_priv
= NULL
;
241 fields
[1].device
= jtag_info
->chain_pos
;
242 fields
[1].num_bits
= 32;
243 fields
[1].out_value
= (u8
*)&opcode
;
244 fields
[1].out_mask
= NULL
;
245 fields
[1].in_value
= NULL
;
246 fields
[1].in_check_value
= NULL
;
247 fields
[1].in_check_mask
= NULL
;
248 fields
[1].in_handler
= NULL
;
249 fields
[1].in_handler_priv
= NULL
;
251 fields
[2].device
= jtag_info
->chain_pos
;
252 fields
[2].num_bits
= 6;
253 fields
[2].out_value
= ®_addr_buf
;
254 fields
[2].out_mask
= NULL
;
255 fields
[2].in_value
= NULL
;
256 fields
[2].in_check_value
= NULL
;
257 fields
[2].in_check_mask
= NULL
;
258 fields
[2].in_handler
= NULL
;
259 fields
[2].in_handler_priv
= NULL
;
261 fields
[3].device
= jtag_info
->chain_pos
;
262 fields
[3].num_bits
= 1;
263 fields
[3].out_value
= &nr_w_buf
;
264 fields
[3].out_mask
= NULL
;
265 fields
[3].in_value
= NULL
;
266 fields
[3].in_check_value
= NULL
;
267 fields
[3].in_check_mask
= NULL
;
268 fields
[3].in_handler
= NULL
;
269 fields
[3].in_handler_priv
= NULL
;
271 jtag_add_dr_scan(4, fields
, -1);
273 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDR(0, 15), 0, NULL
, 0);
274 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
275 arm7_9_execute_sys_speed(target
);
276 jtag_execute_queue();
278 /* read-modify-write CP15 test state register
279 * to disable interpreted access mode */
280 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
281 jtag_execute_queue();
282 cp15c15
&= ~1U; /* clear interpret mode */
283 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
285 context_p
[0] = value
;
286 arm9tdmi_read_core_regs(target
, 0x1, context_p
);
287 jtag_execute_queue();
289 DEBUG("opcode: %8.8x, value: %8.8x", opcode
, *value
);
291 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
292 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= 1;
297 int arm920t_write_cp15_interpreted(target_t
*target
, u32 opcode
, u32 value
, u32 address
)
300 scan_field_t fields
[4];
301 u8 access_type_buf
= 0; /* interpreted access */
302 u8 reg_addr_buf
= 0x0;
304 armv4_5_common_t
*armv4_5
= target
->arch_info
;
305 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
306 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
312 arm9tdmi_write_core_regs(target
, 0x3, regs
);
314 /* read-modify-write CP15 test state register
315 * to enable interpreted access mode */
316 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
317 jtag_execute_queue();
318 cp15c15
|= 1; /* set interpret mode */
319 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
321 jtag_add_end_state(TAP_RTI
);
322 arm_jtag_scann(jtag_info
, 0xf);
323 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
);
325 fields
[0].device
= jtag_info
->chain_pos
;
326 fields
[0].num_bits
= 1;
327 fields
[0].out_value
= &access_type_buf
;
328 fields
[0].out_mask
= NULL
;
329 fields
[0].in_value
= NULL
;
330 fields
[0].in_check_value
= NULL
;
331 fields
[0].in_check_mask
= NULL
;
332 fields
[0].in_handler
= NULL
;
333 fields
[0].in_handler_priv
= NULL
;
335 fields
[1].device
= jtag_info
->chain_pos
;
336 fields
[1].num_bits
= 32;
337 fields
[1].out_value
= (u8
*)&opcode
;
338 fields
[1].out_mask
= NULL
;
339 fields
[1].in_value
= NULL
;
340 fields
[1].in_check_value
= NULL
;
341 fields
[1].in_check_mask
= NULL
;
342 fields
[1].in_handler
= NULL
;
343 fields
[1].in_handler_priv
= NULL
;
345 fields
[2].device
= jtag_info
->chain_pos
;
346 fields
[2].num_bits
= 6;
347 fields
[2].out_value
= ®_addr_buf
;
348 fields
[2].out_mask
= NULL
;
349 fields
[2].in_value
= NULL
;
350 fields
[2].in_check_value
= NULL
;
351 fields
[2].in_check_mask
= NULL
;
352 fields
[2].in_handler
= NULL
;
353 fields
[2].in_handler_priv
= NULL
;
355 fields
[3].device
= jtag_info
->chain_pos
;
356 fields
[3].num_bits
= 1;
357 fields
[3].out_value
= &nr_w_buf
;
358 fields
[3].out_mask
= NULL
;
359 fields
[3].in_value
= NULL
;
360 fields
[3].in_check_value
= NULL
;
361 fields
[3].in_check_mask
= NULL
;
362 fields
[3].in_handler
= NULL
;
363 fields
[3].in_handler_priv
= NULL
;
365 jtag_add_dr_scan(4, fields
, -1);
367 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 1), 0, NULL
, 0);
368 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
369 arm7_9_execute_sys_speed(target
);
370 jtag_execute_queue();
372 /* read-modify-write CP15 test state register
373 * to disable interpreted access mode */
374 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
375 jtag_execute_queue();
376 cp15c15
&= ~1U; /* set interpret mode */
377 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
379 DEBUG("opcode: %8.8x, value: %8.8x, address: %8.8x", opcode
, value
, address
);
384 u32
arm920t_get_ttb(target_t
*target
)
389 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, &ttb
)) != ERROR_OK
)
395 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
399 /* read cp15 control register */
400 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
401 jtag_execute_queue();
404 cp15_control
&= ~0x1U
;
407 cp15_control
&= ~0x4U
;
410 cp15_control
&= ~0x1000U
;
412 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
415 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
419 /* read cp15 control register */
420 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
421 jtag_execute_queue();
424 cp15_control
|= 0x1U
;
427 cp15_control
|= 0x4U
;
430 cp15_control
|= 0x1000U
;
432 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
435 void arm920t_post_debug_entry(target_t
*target
)
438 armv4_5_common_t
*armv4_5
= target
->arch_info
;
439 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
440 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
441 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
443 /* examine cp15 control reg */
444 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
445 jtag_execute_queue();
446 DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
448 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
451 /* identify caches */
452 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
453 jtag_execute_queue();
454 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
457 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
458 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
459 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
461 /* save i/d fault status and address register */
462 arm920t_read_cp15_interpreted(target
, 0xee150f10, &arm920t
->d_fsr
);
463 arm920t_read_cp15_interpreted(target
, 0xee150f30, &arm920t
->i_fsr
);
464 arm920t_read_cp15_interpreted(target
, 0xee160f10, &arm920t
->d_far
);
465 arm920t_read_cp15_interpreted(target
, 0xee160f30, &arm920t
->i_far
);
467 /* read-modify-write CP15 test state register
468 * to disable I/D-cache linefills */
469 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
470 jtag_execute_queue();
472 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
476 void arm920t_pre_restore_context(target_t
*target
)
479 armv4_5_common_t
*armv4_5
= target
->arch_info
;
480 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
481 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
482 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
484 /* restore i/d fault status and address register */
485 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
486 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
487 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
488 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
490 /* read-modify-write CP15 test state register
491 * to reenable I/D-cache linefills */
492 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
493 jtag_execute_queue();
495 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
499 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
501 armv4_5_common_t
*armv4_5
= target
->arch_info
;
502 arm7_9_common_t
*arm7_9
;
503 arm9tdmi_common_t
*arm9tdmi
;
504 arm920t_common_t
*arm920t
;
506 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
511 arm7_9
= armv4_5
->arch_info
;
512 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
517 arm9tdmi
= arm7_9
->arch_info
;
518 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
523 arm920t
= arm9tdmi
->arch_info
;
524 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
529 *armv4_5_p
= armv4_5
;
531 *arm9tdmi_p
= arm9tdmi
;
532 *arm920t_p
= arm920t
;
537 int arm920t_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
539 armv4_5_common_t
*armv4_5
= target
->arch_info
;
540 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
541 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
542 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
546 "disabled", "enabled"
549 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
551 ERROR("BUG: called for a non-ARMv4/5 target");
555 snprintf(buf
, buf_size
,
556 "target halted in %s state due to %s, current mode: %s\n"
557 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
558 "MMU: %s, D-Cache: %s, I-Cache: %s",
559 armv4_5_state_strings
[armv4_5
->core_state
],
560 target_debug_reason_strings
[target
->debug_reason
],
561 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
562 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
563 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
564 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
565 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
566 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
571 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
575 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
580 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
583 armv4_5_common_t
*armv4_5
= target
->arch_info
;
584 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
585 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
586 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
588 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
591 if (((size
== 4) || (size
== 2)) && (count
== 1))
593 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
595 DEBUG("D-Cache enabled, writing through to main memory");
599 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
602 /* cacheable & bufferable means write-back region */
604 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
607 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
609 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
610 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
617 int arm920t_soft_reset_halt(struct target_s
*target
)
619 armv4_5_common_t
*armv4_5
= target
->arch_info
;
620 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
621 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
622 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
623 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
625 if (target
->state
== TARGET_RUNNING
)
627 target
->type
->halt(target
);
630 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_CONTROL_DBGACK
, 1) == 0)
632 embeddedice_read_reg(dbg_stat
);
633 jtag_execute_queue();
636 target
->state
= TARGET_HALTED
;
638 /* SVC, ARM state, IRQ and FIQ disabled */
639 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
640 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
641 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
643 /* start fetching from 0x0 */
644 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
645 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
646 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
648 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
649 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
651 arm920t_disable_mmu_caches(target
, 1, 1, 1);
652 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
653 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
654 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
656 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
661 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
663 arm9tdmi_init_target(cmd_ctx
, target
);
675 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, int chain_pos
, char *variant
)
677 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
678 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
680 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
682 arm9tdmi
->arch_info
= arm920t
;
683 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
685 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
686 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
688 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
689 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
690 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
691 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
692 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
693 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
694 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
695 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
697 arm9tdmi
->has_single_step
= 1;
702 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
705 char *variant
= NULL
;
706 arm920t_common_t
*arm920t
= malloc(sizeof(arm920t_common_t
));
710 ERROR("'target arm920t' requires at least one additional argument");
714 chain_pos
= strtoul(args
[3], NULL
, 0);
717 variant
= strdup(args
[4]);
719 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
721 arm920t_init_arch_info(target
, arm920t
, chain_pos
, variant
);
726 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
729 command_t
*arm920t_cmd
;
732 retval
= arm9tdmi_register_commands(cmd_ctx
);
734 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
736 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
737 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
738 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
739 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
741 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
742 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
743 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
745 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
746 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
747 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
752 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
755 target_t
*target
= get_current_target(cmd_ctx
);
756 armv4_5_common_t
*armv4_5
;
757 arm7_9_common_t
*arm7_9
;
758 arm9tdmi_common_t
*arm9tdmi
;
759 arm920t_common_t
*arm920t
;
760 arm_jtag_t
*jtag_info
;
762 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
764 command_print(cmd_ctx
, "current target isn't an ARM920t target");
768 jtag_info
= &arm7_9
->jtag_info
;
770 if (target
->state
!= TARGET_HALTED
)
772 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
776 /* one or more argument, access a single register (write if second argument is given */
779 int address
= strtoul(args
[0], NULL
, 0);
784 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
786 command_print(cmd_ctx
, "couldn't access reg %i", address
);
789 jtag_execute_queue();
791 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
795 u32 value
= strtoul(args
[1], NULL
, 0);
796 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
798 command_print(cmd_ctx
, "couldn't access reg %i", address
);
801 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
808 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
811 target_t
*target
= get_current_target(cmd_ctx
);
812 armv4_5_common_t
*armv4_5
;
813 arm7_9_common_t
*arm7_9
;
814 arm9tdmi_common_t
*arm9tdmi
;
815 arm920t_common_t
*arm920t
;
816 arm_jtag_t
*jtag_info
;
818 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
820 command_print(cmd_ctx
, "current target isn't an ARM920t target");
824 jtag_info
= &arm7_9
->jtag_info
;
826 if (target
->state
!= TARGET_HALTED
)
828 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
832 /* one or more argument, access a single register (write if second argument is given */
835 u32 opcode
= strtoul(args
[0], NULL
, 0);
840 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, &value
)) != ERROR_OK
)
842 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
846 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
850 u32 value
= strtoul(args
[1], NULL
, 0);
851 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
853 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
856 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
860 u32 value
= strtoul(args
[1], NULL
, 0);
861 u32 address
= strtoul(args
[2], NULL
, 0);
862 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
864 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
867 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
874 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
876 target_t
*target
= get_current_target(cmd_ctx
);
877 armv4_5_common_t
*armv4_5
;
878 arm7_9_common_t
*arm7_9
;
879 arm9tdmi_common_t
*arm9tdmi
;
880 arm920t_common_t
*arm920t
;
882 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
884 command_print(cmd_ctx
, "current target isn't an ARM920t target");
888 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
891 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
893 target_t
*target
= get_current_target(cmd_ctx
);
894 armv4_5_common_t
*armv4_5
;
895 arm7_9_common_t
*arm7_9
;
896 arm9tdmi_common_t
*arm9tdmi
;
897 arm920t_common_t
*arm920t
;
898 arm_jtag_t
*jtag_info
;
900 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
902 command_print(cmd_ctx
, "current target isn't an ARM920t target");
906 jtag_info
= &arm7_9
->jtag_info
;
908 if (target
->state
!= TARGET_HALTED
)
910 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
914 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
917 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
919 target_t
*target
= get_current_target(cmd_ctx
);
920 armv4_5_common_t
*armv4_5
;
921 arm7_9_common_t
*arm7_9
;
922 arm9tdmi_common_t
*arm9tdmi
;
923 arm920t_common_t
*arm920t
;
924 arm_jtag_t
*jtag_info
;
926 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
928 command_print(cmd_ctx
, "current target isn't an ARM920t target");
932 jtag_info
= &arm7_9
->jtag_info
;
934 if (target
->state
!= TARGET_HALTED
)
936 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
940 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
943 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
945 target_t
*target
= get_current_target(cmd_ctx
);
946 armv4_5_common_t
*armv4_5
;
947 arm7_9_common_t
*arm7_9
;
948 arm9tdmi_common_t
*arm9tdmi
;
949 arm920t_common_t
*arm920t
;
950 arm_jtag_t
*jtag_info
;
952 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
954 command_print(cmd_ctx
, "current target isn't an ARM920t target");
958 jtag_info
= &arm7_9
->jtag_info
;
960 if (target
->state
!= TARGET_HALTED
)
962 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
966 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
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