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in_handler in_check_mask and in_check_value now removed from field. Last big patch...
[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "jtag.h"
26 #include "log.h"
27 #include "time_support.h"
28
29 #include <stdlib.h>
30 #include <string.h>
31
32 #if 0
33 #define _DEBUG_INSTRUCTION_EXECUTION_
34 #endif
35
36 /* cli handling */
37 int arm920t_register_commands(struct command_context_s *cmd_ctx);
38
39 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45
46 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48
49 /* forward declarations */
50 int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
51 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm920t_quit(void);
53 int arm920t_arch_state(struct target_s *target);
54 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
56 int arm920t_soft_reset_halt(struct target_s *target);
57
58 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
59
60 target_type_t arm920t_target =
61 {
62 .name = "arm920t",
63
64 .poll = arm7_9_poll,
65 .arch_state = arm920t_arch_state,
66
67 .target_request_data = arm7_9_target_request_data,
68
69 .halt = arm7_9_halt,
70 .resume = arm7_9_resume,
71 .step = arm7_9_step,
72
73 .assert_reset = arm7_9_assert_reset,
74 .deassert_reset = arm7_9_deassert_reset,
75 .soft_reset_halt = arm920t_soft_reset_halt,
76
77 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78
79 .read_memory = arm920t_read_memory,
80 .write_memory = arm920t_write_memory,
81 .bulk_write_memory = arm7_9_bulk_write_memory,
82 .checksum_memory = arm7_9_checksum_memory,
83 .blank_check_memory = arm7_9_blank_check_memory,
84
85 .run_algorithm = armv4_5_run_algorithm,
86
87 .add_breakpoint = arm7_9_add_breakpoint,
88 .remove_breakpoint = arm7_9_remove_breakpoint,
89 .add_watchpoint = arm7_9_add_watchpoint,
90 .remove_watchpoint = arm7_9_remove_watchpoint,
91
92 .register_commands = arm920t_register_commands,
93 .target_create = arm920t_target_create,
94 .init_target = arm920t_init_target,
95 .examine = arm9tdmi_examine,
96 .quit = arm920t_quit
97 };
98
99 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
100 {
101 armv4_5_common_t *armv4_5 = target->arch_info;
102 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
103 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
104 scan_field_t fields[4];
105 u8 access_type_buf = 1;
106 u8 reg_addr_buf = reg_addr & 0x3f;
107 u8 nr_w_buf = 0;
108
109 jtag_add_end_state(TAP_IDLE);
110 arm_jtag_scann(jtag_info, 0xf);
111 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
112
113 fields[0].tap = jtag_info->tap;
114 fields[0].num_bits = 1;
115 fields[0].out_value = &access_type_buf;
116 fields[0].in_value = NULL;
117
118
119 fields[1].tap = jtag_info->tap;
120 fields[1].num_bits = 32;
121 fields[1].out_value = NULL;
122 fields[1].in_value = NULL;
123
124
125 fields[2].tap = jtag_info->tap;
126 fields[2].num_bits = 6;
127 fields[2].out_value = &reg_addr_buf;
128 fields[2].in_value = NULL;
129
130
131 fields[3].tap = jtag_info->tap;
132 fields[3].num_bits = 1;
133 fields[3].out_value = &nr_w_buf;
134 fields[3].in_value = NULL;
135
136
137 jtag_add_dr_scan(4, fields, TAP_INVALID);
138
139 u8 tmp[4];
140 fields[1].in_value = tmp;
141
142 jtag_add_dr_scan_now(4, fields, TAP_INVALID);
143
144 *value=le_to_h_u32(tmp);
145
146 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
147 jtag_execute_queue();
148 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
149 #endif
150
151 return ERROR_OK;
152 }
153
154 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
155 {
156 armv4_5_common_t *armv4_5 = target->arch_info;
157 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
158 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
159 scan_field_t fields[4];
160 u8 access_type_buf = 1;
161 u8 reg_addr_buf = reg_addr & 0x3f;
162 u8 nr_w_buf = 1;
163 u8 value_buf[4];
164
165 buf_set_u32(value_buf, 0, 32, value);
166
167 jtag_add_end_state(TAP_IDLE);
168 arm_jtag_scann(jtag_info, 0xf);
169 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
170
171 fields[0].tap = jtag_info->tap;
172 fields[0].num_bits = 1;
173 fields[0].out_value = &access_type_buf;
174
175 fields[0].in_value = NULL;
176
177
178
179
180
181 fields[1].tap = jtag_info->tap;
182 fields[1].num_bits = 32;
183 fields[1].out_value = value_buf;
184
185 fields[1].in_value = NULL;
186
187
188
189
190
191 fields[2].tap = jtag_info->tap;
192 fields[2].num_bits = 6;
193 fields[2].out_value = &reg_addr_buf;
194
195 fields[2].in_value = NULL;
196
197
198
199
200
201 fields[3].tap = jtag_info->tap;
202 fields[3].num_bits = 1;
203 fields[3].out_value = &nr_w_buf;
204
205 fields[3].in_value = NULL;
206
207
208
209
210
211 jtag_add_dr_scan(4, fields, TAP_INVALID);
212
213 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
214 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
215 #endif
216
217 return ERROR_OK;
218 }
219
220 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
221 {
222 int retval;
223 armv4_5_common_t *armv4_5 = target->arch_info;
224 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
225 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
226 scan_field_t fields[4];
227 u8 access_type_buf = 0; /* interpreted access */
228 u8 reg_addr_buf = 0x0;
229 u8 nr_w_buf = 0;
230 u8 cp15_opcode_buf[4];
231
232 jtag_add_end_state(TAP_IDLE);
233 arm_jtag_scann(jtag_info, 0xf);
234 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
235
236 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
237
238 fields[0].tap = jtag_info->tap;
239 fields[0].num_bits = 1;
240 fields[0].out_value = &access_type_buf;
241
242 fields[0].in_value = NULL;
243
244
245
246
247
248 fields[1].tap = jtag_info->tap;
249 fields[1].num_bits = 32;
250 fields[1].out_value = cp15_opcode_buf;
251
252 fields[1].in_value = NULL;
253
254
255
256
257
258 fields[2].tap = jtag_info->tap;
259 fields[2].num_bits = 6;
260 fields[2].out_value = &reg_addr_buf;
261
262 fields[2].in_value = NULL;
263
264
265
266
267
268 fields[3].tap = jtag_info->tap;
269 fields[3].num_bits = 1;
270 fields[3].out_value = &nr_w_buf;
271
272 fields[3].in_value = NULL;
273
274
275
276
277
278 jtag_add_dr_scan(4, fields, TAP_INVALID);
279
280 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
281 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
282 retval = arm7_9_execute_sys_speed(target);
283 if (retval != ERROR_OK)
284 return retval;
285
286 if ((retval = jtag_execute_queue()) != ERROR_OK)
287 {
288 LOG_ERROR("failed executing JTAG queue, exiting");
289 return retval;
290 }
291
292 return ERROR_OK;
293 }
294
295 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
296 {
297 armv4_5_common_t *armv4_5 = target->arch_info;
298 u32* regs_p[1];
299 u32 regs[2];
300 u32 cp15c15 = 0x0;
301
302 /* load address into R1 */
303 regs[1] = address;
304 arm9tdmi_write_core_regs(target, 0x2, regs);
305
306 /* read-modify-write CP15 test state register
307 * to enable interpreted access mode */
308 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
309 jtag_execute_queue();
310 cp15c15 |= 1; /* set interpret mode */
311 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
312
313 /* execute CP15 instruction and ARM load (reading from coprocessor) */
314 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
315
316 /* disable interpreted access mode */
317 cp15c15 &= ~1U; /* clear interpret mode */
318 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
319
320 /* retrieve value from R0 */
321 regs_p[0] = value;
322 arm9tdmi_read_core_regs(target, 0x1, regs_p);
323 jtag_execute_queue();
324
325 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
326 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
327 #endif
328
329 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
330 return ERROR_FAIL;
331
332 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
333 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
334
335 return ERROR_OK;
336 }
337
338 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
339 {
340 u32 cp15c15 = 0x0;
341 armv4_5_common_t *armv4_5 = target->arch_info;
342 u32 regs[2];
343
344 /* load value, address into R0, R1 */
345 regs[0] = value;
346 regs[1] = address;
347 arm9tdmi_write_core_regs(target, 0x3, regs);
348
349 /* read-modify-write CP15 test state register
350 * to enable interpreted access mode */
351 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
352 jtag_execute_queue();
353 cp15c15 |= 1; /* set interpret mode */
354 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
355
356 /* execute CP15 instruction and ARM store (writing to coprocessor) */
357 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
358
359 /* disable interpreted access mode */
360 cp15c15 &= ~1U; /* set interpret mode */
361 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
362
363 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
364 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
365 #endif
366
367 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
368 return ERROR_FAIL;
369
370 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
371 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
372
373 return ERROR_OK;
374 }
375
376 u32 arm920t_get_ttb(target_t *target)
377 {
378 int retval;
379 u32 ttb = 0x0;
380
381 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
382 return retval;
383
384 return ttb;
385 }
386
387 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
388 {
389 u32 cp15_control;
390
391 /* read cp15 control register */
392 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
393 jtag_execute_queue();
394
395 if (mmu)
396 cp15_control &= ~0x1U;
397
398 if (d_u_cache)
399 cp15_control &= ~0x4U;
400
401 if (i_cache)
402 cp15_control &= ~0x1000U;
403
404 arm920t_write_cp15_physical(target, 0x2, cp15_control);
405 }
406
407 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
408 {
409 u32 cp15_control;
410
411 /* read cp15 control register */
412 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
413 jtag_execute_queue();
414
415 if (mmu)
416 cp15_control |= 0x1U;
417
418 if (d_u_cache)
419 cp15_control |= 0x4U;
420
421 if (i_cache)
422 cp15_control |= 0x1000U;
423
424 arm920t_write_cp15_physical(target, 0x2, cp15_control);
425 }
426
427 void arm920t_post_debug_entry(target_t *target)
428 {
429 u32 cp15c15;
430 armv4_5_common_t *armv4_5 = target->arch_info;
431 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
432 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
433 arm920t_common_t *arm920t = arm9tdmi->arch_info;
434
435 /* examine cp15 control reg */
436 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
437 jtag_execute_queue();
438 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
439
440 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
441 {
442 u32 cache_type_reg;
443 /* identify caches */
444 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
445 jtag_execute_queue();
446 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
447 }
448
449 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
450 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
451 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
452
453 /* save i/d fault status and address register */
454 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
455 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
456 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
457 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
458
459 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
460 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
461
462 if (arm920t->preserve_cache)
463 {
464 /* read-modify-write CP15 test state register
465 * to disable I/D-cache linefills */
466 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
467 jtag_execute_queue();
468 cp15c15 |= 0x600;
469 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
470 }
471 }
472
473 void arm920t_pre_restore_context(target_t *target)
474 {
475 u32 cp15c15;
476 armv4_5_common_t *armv4_5 = target->arch_info;
477 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
478 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
479 arm920t_common_t *arm920t = arm9tdmi->arch_info;
480
481 /* restore i/d fault status and address register */
482 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
483 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
484 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
485 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
486
487 /* read-modify-write CP15 test state register
488 * to reenable I/D-cache linefills */
489 if (arm920t->preserve_cache)
490 {
491 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
492 jtag_execute_queue();
493 cp15c15 &= ~0x600U;
494 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
495 }
496 }
497
498 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
499 {
500 armv4_5_common_t *armv4_5 = target->arch_info;
501 arm7_9_common_t *arm7_9;
502 arm9tdmi_common_t *arm9tdmi;
503 arm920t_common_t *arm920t;
504
505 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
506 {
507 return -1;
508 }
509
510 arm7_9 = armv4_5->arch_info;
511 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
512 {
513 return -1;
514 }
515
516 arm9tdmi = arm7_9->arch_info;
517 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
518 {
519 return -1;
520 }
521
522 arm920t = arm9tdmi->arch_info;
523 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
524 {
525 return -1;
526 }
527
528 *armv4_5_p = armv4_5;
529 *arm7_9_p = arm7_9;
530 *arm9tdmi_p = arm9tdmi;
531 *arm920t_p = arm920t;
532
533 return ERROR_OK;
534 }
535
536 int arm920t_arch_state(struct target_s *target)
537 {
538 armv4_5_common_t *armv4_5 = target->arch_info;
539 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
540 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
541 arm920t_common_t *arm920t = arm9tdmi->arch_info;
542
543 char *state[] =
544 {
545 "disabled", "enabled"
546 };
547
548 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
549 {
550 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
551 exit(-1);
552 }
553
554 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
555 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
556 "MMU: %s, D-Cache: %s, I-Cache: %s",
557 armv4_5_state_strings[armv4_5->core_state],
558 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
559 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
560 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
561 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
562 state[arm920t->armv4_5_mmu.mmu_enabled],
563 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
564 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
565
566 return ERROR_OK;
567 }
568
569 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
570 {
571 int retval;
572
573 retval = arm7_9_read_memory(target, address, size, count, buffer);
574
575 return retval;
576 }
577
578 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
579 {
580 int retval;
581 armv4_5_common_t *armv4_5 = target->arch_info;
582 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
583 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
584 arm920t_common_t *arm920t = arm9tdmi->arch_info;
585
586 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
587 return retval;
588
589 if (((size == 4) || (size == 2)) && (count == 1))
590 {
591 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
592 {
593 LOG_DEBUG("D-Cache enabled, writing through to main memory");
594 u32 pa, cb, ap;
595 int type, domain;
596
597 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
598 if (type == -1)
599 return ERROR_OK;
600 /* cacheable & bufferable means write-back region */
601 if (cb == 3)
602 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
603 }
604
605 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
606 {
607 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
608 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
609 }
610 }
611
612 return retval;
613 }
614
615 int arm920t_soft_reset_halt(struct target_s *target)
616 {
617 int retval = ERROR_OK;
618 armv4_5_common_t *armv4_5 = target->arch_info;
619 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
620 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
621 arm920t_common_t *arm920t = arm9tdmi->arch_info;
622 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
623
624 if((retval = target_halt(target)) != ERROR_OK)
625 {
626 return retval;
627 }
628
629 long long then=timeval_ms();
630 int timeout;
631 while (!(timeout=((timeval_ms()-then)>1000)))
632 {
633 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
634 {
635 embeddedice_read_reg(dbg_stat);
636 if((retval = jtag_execute_queue()) != ERROR_OK)
637 {
638 return retval;
639 }
640 } else
641 {
642 break;
643 }
644 if (debug_level>=3)
645 {
646 /* do not eat all CPU, time out after 1 se*/
647 alive_sleep(100);
648 } else
649 {
650 keep_alive();
651 }
652 }
653 if (timeout)
654 {
655 LOG_ERROR("Failed to halt CPU after 1 sec");
656 return ERROR_TARGET_TIMEOUT;
657 }
658
659 target->state = TARGET_HALTED;
660
661 /* SVC, ARM state, IRQ and FIQ disabled */
662 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
663 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
664 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
665
666 /* start fetching from 0x0 */
667 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
668 armv4_5->core_cache->reg_list[15].dirty = 1;
669 armv4_5->core_cache->reg_list[15].valid = 1;
670
671 armv4_5->core_mode = ARMV4_5_MODE_SVC;
672 armv4_5->core_state = ARMV4_5_STATE_ARM;
673
674 arm920t_disable_mmu_caches(target, 1, 1, 1);
675 arm920t->armv4_5_mmu.mmu_enabled = 0;
676 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
677 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
678
679 if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
680 {
681 return retval;
682 }
683
684 return ERROR_OK;
685 }
686
687 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
688 {
689 arm9tdmi_init_target(cmd_ctx, target);
690
691 return ERROR_OK;
692 }
693
694 int arm920t_quit(void)
695 {
696 return ERROR_OK;
697 }
698
699 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
700 {
701 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
702 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
703
704 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
705 */
706 arm9tdmi_init_arch_info(target, arm9tdmi, tap);
707
708 arm9tdmi->arch_info = arm920t;
709 arm920t->common_magic = ARM920T_COMMON_MAGIC;
710
711 arm7_9->post_debug_entry = arm920t_post_debug_entry;
712 arm7_9->pre_restore_context = arm920t_pre_restore_context;
713
714 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
715 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
716 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
717 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
718 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
719 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
720 arm920t->armv4_5_mmu.has_tiny_pages = 1;
721 arm920t->armv4_5_mmu.mmu_enabled = 0;
722
723 /* disabling linefills leads to lockups, so keep them enabled for now
724 * this doesn't affect correctness, but might affect timing issues, if
725 * important data is evicted from the cache during the debug session
726 * */
727 arm920t->preserve_cache = 0;
728
729 /* override hw single-step capability from ARM9TDMI */
730 arm7_9->has_single_step = 1;
731
732 return ERROR_OK;
733 }
734
735 int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
736 {
737 arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
738
739 arm920t_init_arch_info(target, arm920t, target->tap);
740
741 return ERROR_OK;
742 }
743
744 int arm920t_register_commands(struct command_context_s *cmd_ctx)
745 {
746 int retval;
747 command_t *arm920t_cmd;
748
749
750 retval = arm9tdmi_register_commands(cmd_ctx);
751
752 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
753
754 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
755 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
756 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
757 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
758
759 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
760 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
761 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
762
763 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
764 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
765 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
766
767 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
768 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
769
770 return retval;
771 }
772
773 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
774 {
775 int retval = ERROR_OK;
776 target_t *target = get_current_target(cmd_ctx);
777 armv4_5_common_t *armv4_5;
778 arm7_9_common_t *arm7_9;
779 arm9tdmi_common_t *arm9tdmi;
780 arm920t_common_t *arm920t;
781 arm_jtag_t *jtag_info;
782 u32 cp15c15;
783 u32 cp15_ctrl, cp15_ctrl_saved;
784 u32 regs[16];
785 u32 *regs_p[16];
786 u32 C15_C_D_Ind, C15_C_I_Ind;
787 int i;
788 FILE *output;
789 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
790 int segment, index;
791
792 if (argc != 1)
793 {
794 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
795 return ERROR_OK;
796 }
797
798 if ((output = fopen(args[0], "w")) == NULL)
799 {
800 LOG_DEBUG("error opening cache content file");
801 return ERROR_OK;
802 }
803
804 for (i = 0; i < 16; i++)
805 regs_p[i] = &regs[i];
806
807 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
808 {
809 command_print(cmd_ctx, "current target isn't an ARM920t target");
810 return ERROR_OK;
811 }
812
813 jtag_info = &arm7_9->jtag_info;
814
815 /* disable MMU and Caches */
816 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
817 if((retval = jtag_execute_queue()) != ERROR_OK)
818 {
819 return retval;
820 }
821 cp15_ctrl_saved = cp15_ctrl;
822 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
823 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
824
825 /* read CP15 test state register */
826 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
827 jtag_execute_queue();
828
829 /* read DCache content */
830 fprintf(output, "DCache:\n");
831
832 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
833 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
834 {
835 fprintf(output, "\nsegment: %i\n----------", segment);
836
837 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
838 regs[0] = 0x0 | (segment << 5);
839 arm9tdmi_write_core_regs(target, 0x1, regs);
840
841 /* set interpret mode */
842 cp15c15 |= 0x1;
843 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
844
845 /* D CAM Read, loads current victim into C15.C.D.Ind */
846 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
847
848 /* read current victim */
849 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
850
851 /* clear interpret mode */
852 cp15c15 &= ~0x1;
853 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
854
855 for (index = 0; index < 64; index++)
856 {
857 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
858 regs[0] = 0x0 | (segment << 5) | (index << 26);
859 arm9tdmi_write_core_regs(target, 0x1, regs);
860
861 /* set interpret mode */
862 cp15c15 |= 0x1;
863 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
864
865 /* Write DCache victim */
866 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
867
868 /* Read D RAM */
869 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
870
871 /* Read D CAM */
872 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
873
874 /* clear interpret mode */
875 cp15c15 &= ~0x1;
876 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
877
878 /* read D RAM and CAM content */
879 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
880 if((retval = jtag_execute_queue()) != ERROR_OK)
881 {
882 return retval;
883 }
884
885 d_cache[segment][index].cam = regs[9];
886
887 /* mask LFSR[6] */
888 regs[9] &= 0xfffffffe;
889 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
890
891 for (i = 1; i < 9; i++)
892 {
893 d_cache[segment][index].data[i] = regs[i];
894 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
895 }
896
897 }
898
899 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
900 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
901 arm9tdmi_write_core_regs(target, 0x1, regs);
902
903 /* set interpret mode */
904 cp15c15 |= 0x1;
905 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
906
907 /* Write DCache victim */
908 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
909
910 /* clear interpret mode */
911 cp15c15 &= ~0x1;
912 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
913 }
914
915 /* read ICache content */
916 fprintf(output, "ICache:\n");
917
918 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
919 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
920 {
921 fprintf(output, "segment: %i\n----------", segment);
922
923 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
924 regs[0] = 0x0 | (segment << 5);
925 arm9tdmi_write_core_regs(target, 0x1, regs);
926
927 /* set interpret mode */
928 cp15c15 |= 0x1;
929 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
930
931 /* I CAM Read, loads current victim into C15.C.I.Ind */
932 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
933
934 /* read current victim */
935 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
936
937 /* clear interpret mode */
938 cp15c15 &= ~0x1;
939 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
940
941 for (index = 0; index < 64; index++)
942 {
943 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
944 regs[0] = 0x0 | (segment << 5) | (index << 26);
945 arm9tdmi_write_core_regs(target, 0x1, regs);
946
947 /* set interpret mode */
948 cp15c15 |= 0x1;
949 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
950
951 /* Write ICache victim */
952 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
953
954 /* Read I RAM */
955 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
956
957 /* Read I CAM */
958 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
959
960 /* clear interpret mode */
961 cp15c15 &= ~0x1;
962 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
963
964 /* read I RAM and CAM content */
965 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
966 if((retval = jtag_execute_queue()) != ERROR_OK)
967 {
968 return retval;
969 }
970
971 i_cache[segment][index].cam = regs[9];
972
973 /* mask LFSR[6] */
974 regs[9] &= 0xfffffffe;
975 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
976
977 for (i = 1; i < 9; i++)
978 {
979 i_cache[segment][index].data[i] = regs[i];
980 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
981 }
982 }
983
984 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
985 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
986 arm9tdmi_write_core_regs(target, 0x1, regs);
987
988 /* set interpret mode */
989 cp15c15 |= 0x1;
990 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
991
992 /* Write ICache victim */
993 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
994
995 /* clear interpret mode */
996 cp15c15 &= ~0x1;
997 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
998 }
999
1000 /* restore CP15 MMU and Cache settings */
1001 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1002
1003 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
1004
1005 fclose(output);
1006
1007 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1008 return ERROR_FAIL;
1009
1010 /* mark registers dirty. */
1011 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1012 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1013 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1014 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1015 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1016 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1017 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1018 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1019 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1020 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1021
1022 return ERROR_OK;
1023 }
1024
1025 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1026 {
1027 int retval = ERROR_OK;
1028 target_t *target = get_current_target(cmd_ctx);
1029 armv4_5_common_t *armv4_5;
1030 arm7_9_common_t *arm7_9;
1031 arm9tdmi_common_t *arm9tdmi;
1032 arm920t_common_t *arm920t;
1033 arm_jtag_t *jtag_info;
1034 u32 cp15c15;
1035 u32 cp15_ctrl, cp15_ctrl_saved;
1036 u32 regs[16];
1037 u32 *regs_p[16];
1038 int i;
1039 FILE *output;
1040 u32 Dlockdown, Ilockdown;
1041 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1042 int victim;
1043
1044 if (argc != 1)
1045 {
1046 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1047 return ERROR_OK;
1048 }
1049
1050 if ((output = fopen(args[0], "w")) == NULL)
1051 {
1052 LOG_DEBUG("error opening mmu content file");
1053 return ERROR_OK;
1054 }
1055
1056 for (i = 0; i < 16; i++)
1057 regs_p[i] = &regs[i];
1058
1059 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1060 {
1061 command_print(cmd_ctx, "current target isn't an ARM920t target");
1062 return ERROR_OK;
1063 }
1064
1065 jtag_info = &arm7_9->jtag_info;
1066
1067 /* disable MMU and Caches */
1068 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1069 if((retval = jtag_execute_queue()) != ERROR_OK)
1070 {
1071 return retval;
1072 }
1073 cp15_ctrl_saved = cp15_ctrl;
1074 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1075 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1076
1077 /* read CP15 test state register */
1078 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1079 if((retval = jtag_execute_queue()) != ERROR_OK)
1080 {
1081 return retval;
1082 }
1083
1084 /* prepare reading D TLB content
1085 * */
1086
1087 /* set interpret mode */
1088 cp15c15 |= 0x1;
1089 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1090
1091 /* Read D TLB lockdown */
1092 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1093
1094 /* clear interpret mode */
1095 cp15c15 &= ~0x1;
1096 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1097
1098 /* read D TLB lockdown stored to r1 */
1099 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1100 if((retval = jtag_execute_queue()) != ERROR_OK)
1101 {
1102 return retval;
1103 }
1104 Dlockdown = regs[1];
1105
1106 for (victim = 0; victim < 64; victim += 8)
1107 {
1108 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1109 * base remains unchanged, victim goes through entries 0 to 63 */
1110 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1111 arm9tdmi_write_core_regs(target, 0x2, regs);
1112
1113 /* set interpret mode */
1114 cp15c15 |= 0x1;
1115 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1116
1117 /* Write D TLB lockdown */
1118 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1119
1120 /* Read D TLB CAM */
1121 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1122
1123 /* clear interpret mode */
1124 cp15c15 &= ~0x1;
1125 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1126
1127 /* read D TLB CAM content stored to r2-r9 */
1128 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1129 if((retval = jtag_execute_queue()) != ERROR_OK)
1130 {
1131 return retval;
1132 }
1133
1134 for (i = 0; i < 8; i++)
1135 d_tlb[victim + i].cam = regs[i + 2];
1136 }
1137
1138 for (victim = 0; victim < 64; victim++)
1139 {
1140 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1141 * base remains unchanged, victim goes through entries 0 to 63 */
1142 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1143 arm9tdmi_write_core_regs(target, 0x2, regs);
1144
1145 /* set interpret mode */
1146 cp15c15 |= 0x1;
1147 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1148
1149 /* Write D TLB lockdown */
1150 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1151
1152 /* Read D TLB RAM1 */
1153 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1154
1155 /* Read D TLB RAM2 */
1156 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1157
1158 /* clear interpret mode */
1159 cp15c15 &= ~0x1;
1160 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1161
1162 /* read D TLB RAM content stored to r2 and r3 */
1163 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1164 if((retval = jtag_execute_queue()) != ERROR_OK)
1165 {
1166 return retval;
1167 }
1168
1169 d_tlb[victim].ram1 = regs[2];
1170 d_tlb[victim].ram2 = regs[3];
1171 }
1172
1173 /* restore D TLB lockdown */
1174 regs[1] = Dlockdown;
1175 arm9tdmi_write_core_regs(target, 0x2, regs);
1176
1177 /* Write D TLB lockdown */
1178 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1179
1180 /* prepare reading I TLB content
1181 * */
1182
1183 /* set interpret mode */
1184 cp15c15 |= 0x1;
1185 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1186
1187 /* Read I TLB lockdown */
1188 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1189
1190 /* clear interpret mode */
1191 cp15c15 &= ~0x1;
1192 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1193
1194 /* read I TLB lockdown stored to r1 */
1195 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1196 if((retval = jtag_execute_queue()) != ERROR_OK)
1197 {
1198 return retval;
1199 }
1200 Ilockdown = regs[1];
1201
1202 for (victim = 0; victim < 64; victim += 8)
1203 {
1204 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1205 * base remains unchanged, victim goes through entries 0 to 63 */
1206 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1207 arm9tdmi_write_core_regs(target, 0x2, regs);
1208
1209 /* set interpret mode */
1210 cp15c15 |= 0x1;
1211 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1212
1213 /* Write I TLB lockdown */
1214 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1215
1216 /* Read I TLB CAM */
1217 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1218
1219 /* clear interpret mode */
1220 cp15c15 &= ~0x1;
1221 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1222
1223 /* read I TLB CAM content stored to r2-r9 */
1224 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1225 if((retval = jtag_execute_queue()) != ERROR_OK)
1226 {
1227 return retval;
1228 }
1229
1230 for (i = 0; i < 8; i++)
1231 i_tlb[i + victim].cam = regs[i + 2];
1232 }
1233
1234 for (victim = 0; victim < 64; victim++)
1235 {
1236 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1237 * base remains unchanged, victim goes through entries 0 to 63 */
1238 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1239 arm9tdmi_write_core_regs(target, 0x2, regs);
1240
1241 /* set interpret mode */
1242 cp15c15 |= 0x1;
1243 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1244
1245 /* Write I TLB lockdown */
1246 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1247
1248 /* Read I TLB RAM1 */
1249 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1250
1251 /* Read I TLB RAM2 */
1252 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1253
1254 /* clear interpret mode */
1255 cp15c15 &= ~0x1;
1256 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1257
1258 /* read I TLB RAM content stored to r2 and r3 */
1259 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1260 if((retval = jtag_execute_queue()) != ERROR_OK)
1261 {
1262 return retval;
1263 }
1264
1265 i_tlb[victim].ram1 = regs[2];
1266 i_tlb[victim].ram2 = regs[3];
1267 }
1268
1269 /* restore I TLB lockdown */
1270 regs[1] = Ilockdown;
1271 arm9tdmi_write_core_regs(target, 0x2, regs);
1272
1273 /* Write I TLB lockdown */
1274 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1275
1276 /* restore CP15 MMU and Cache settings */
1277 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1278
1279 /* output data to file */
1280 fprintf(output, "D TLB content:\n");
1281 for (i = 0; i < 64; i++)
1282 {
1283 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1284 }
1285
1286 fprintf(output, "\n\nI TLB content:\n");
1287 for (i = 0; i < 64; i++)
1288 {
1289 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1290 }
1291
1292 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1293
1294 fclose(output);
1295
1296 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1297 return ERROR_FAIL;
1298
1299 /* mark registers dirty */
1300 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1301 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1302 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1303 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1304 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1305 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1306 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1307 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1308 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1309 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1310
1311 return ERROR_OK;
1312 }
1313 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1314 {
1315 int retval;
1316 target_t *target = get_current_target(cmd_ctx);
1317 armv4_5_common_t *armv4_5;
1318 arm7_9_common_t *arm7_9;
1319 arm9tdmi_common_t *arm9tdmi;
1320 arm920t_common_t *arm920t;
1321 arm_jtag_t *jtag_info;
1322
1323 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1324 {
1325 command_print(cmd_ctx, "current target isn't an ARM920t target");
1326 return ERROR_OK;
1327 }
1328
1329 jtag_info = &arm7_9->jtag_info;
1330
1331 if (target->state != TARGET_HALTED)
1332 {
1333 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1334 return ERROR_OK;
1335 }
1336
1337 /* one or more argument, access a single register (write if second argument is given */
1338 if (argc >= 1)
1339 {
1340 int address = strtoul(args[0], NULL, 0);
1341
1342 if (argc == 1)
1343 {
1344 u32 value;
1345 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1346 {
1347 command_print(cmd_ctx, "couldn't access reg %i", address);
1348 return ERROR_OK;
1349 }
1350 if((retval = jtag_execute_queue()) != ERROR_OK)
1351 {
1352 return retval;
1353 }
1354
1355 command_print(cmd_ctx, "%i: %8.8x", address, value);
1356 }
1357 else if (argc == 2)
1358 {
1359 u32 value = strtoul(args[1], NULL, 0);
1360 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1361 {
1362 command_print(cmd_ctx, "couldn't access reg %i", address);
1363 return ERROR_OK;
1364 }
1365 command_print(cmd_ctx, "%i: %8.8x", address, value);
1366 }
1367 }
1368
1369 return ERROR_OK;
1370 }
1371
1372 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1373 {
1374 int retval;
1375 target_t *target = get_current_target(cmd_ctx);
1376 armv4_5_common_t *armv4_5;
1377 arm7_9_common_t *arm7_9;
1378 arm9tdmi_common_t *arm9tdmi;
1379 arm920t_common_t *arm920t;
1380 arm_jtag_t *jtag_info;
1381
1382 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1383 {
1384 command_print(cmd_ctx, "current target isn't an ARM920t target");
1385 return ERROR_OK;
1386 }
1387
1388 jtag_info = &arm7_9->jtag_info;
1389
1390 if (target->state != TARGET_HALTED)
1391 {
1392 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1393 return ERROR_OK;
1394 }
1395
1396 /* one or more argument, access a single register (write if second argument is given */
1397 if (argc >= 1)
1398 {
1399 u32 opcode = strtoul(args[0], NULL, 0);
1400
1401 if (argc == 1)
1402 {
1403 u32 value;
1404 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1405 {
1406 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1407 return ERROR_OK;
1408 }
1409
1410 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1411 }
1412 else if (argc == 2)
1413 {
1414 u32 value = strtoul(args[1], NULL, 0);
1415 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1416 {
1417 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1418 return ERROR_OK;
1419 }
1420 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1421 }
1422 else if (argc == 3)
1423 {
1424 u32 value = strtoul(args[1], NULL, 0);
1425 u32 address = strtoul(args[2], NULL, 0);
1426 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1427 {
1428 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1429 return ERROR_OK;
1430 }
1431 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1432 }
1433 }
1434 else
1435 {
1436 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1437 }
1438
1439 return ERROR_OK;
1440 }
1441
1442 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1443 {
1444 target_t *target = get_current_target(cmd_ctx);
1445 armv4_5_common_t *armv4_5;
1446 arm7_9_common_t *arm7_9;
1447 arm9tdmi_common_t *arm9tdmi;
1448 arm920t_common_t *arm920t;
1449
1450 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1451 {
1452 command_print(cmd_ctx, "current target isn't an ARM920t target");
1453 return ERROR_OK;
1454 }
1455
1456 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1457 }
1458
1459 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1460 {
1461 target_t *target = get_current_target(cmd_ctx);
1462 armv4_5_common_t *armv4_5;
1463 arm7_9_common_t *arm7_9;
1464 arm9tdmi_common_t *arm9tdmi;
1465 arm920t_common_t *arm920t;
1466 arm_jtag_t *jtag_info;
1467
1468 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1469 {
1470 command_print(cmd_ctx, "current target isn't an ARM920t target");
1471 return ERROR_OK;
1472 }
1473
1474 jtag_info = &arm7_9->jtag_info;
1475
1476 if (target->state != TARGET_HALTED)
1477 {
1478 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1479 return ERROR_OK;
1480 }
1481
1482 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1483 }
1484
1485 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1486 {
1487 target_t *target = get_current_target(cmd_ctx);
1488 armv4_5_common_t *armv4_5;
1489 arm7_9_common_t *arm7_9;
1490 arm9tdmi_common_t *arm9tdmi;
1491 arm920t_common_t *arm920t;
1492 arm_jtag_t *jtag_info;
1493
1494 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1495 {
1496 command_print(cmd_ctx, "current target isn't an ARM920t target");
1497 return ERROR_OK;
1498 }
1499
1500 jtag_info = &arm7_9->jtag_info;
1501
1502 if (target->state != TARGET_HALTED)
1503 {
1504 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1505 return ERROR_OK;
1506 }
1507
1508 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1509 }
1510
1511 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1512 {
1513 target_t *target = get_current_target(cmd_ctx);
1514 armv4_5_common_t *armv4_5;
1515 arm7_9_common_t *arm7_9;
1516 arm9tdmi_common_t *arm9tdmi;
1517 arm920t_common_t *arm920t;
1518 arm_jtag_t *jtag_info;
1519
1520 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1521 {
1522 command_print(cmd_ctx, "current target isn't an ARM920t target");
1523 return ERROR_OK;
1524 }
1525
1526 jtag_info = &arm7_9->jtag_info;
1527
1528 if (target->state != TARGET_HALTED)
1529 {
1530 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1531 return ERROR_OK;
1532 }
1533
1534 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1535 }
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