1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include <helper/time_support.h>
26 #include "target_type.h"
28 #include "arm_opcodes.h"
32 * For information about the ARM920T, see ARM DDI 0151C especially
33 * Chapter 9 about debug support, which shows how to manipulate each
34 * of the different scan chains:
36 * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
37 * 1 ... debugging; watchpoint and breakpoint status, etc; also
38 * MMU and cache access in conjunction with scan chain 15
40 * 3 ... external boundary scan (SoC-specific, unused here)
41 * 4 ... access to cache tag RAM
43 * 15 ... access coprocessor 15, "physical" or "interpreted" modes
44 * "interpreted" works with a few actual MRC/MCR instructions
45 * "physical" provides register-like behaviors.
47 * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
51 #define _DEBUG_INSTRUCTION_EXECUTION_
54 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
56 static int arm920t_read_cp15_physical(struct target
*target
,
57 int reg_addr
, uint32_t *value
)
59 struct arm920t_common
*arm920t
= target_to_arm920(target
);
60 struct arm_jtag
*jtag_info
;
61 struct scan_field fields
[4];
62 uint8_t access_type_buf
= 1;
63 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
66 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
68 jtag_set_end_state(TAP_IDLE
);
69 arm_jtag_scann(jtag_info
, 0xf);
70 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
72 fields
[0].tap
= jtag_info
->tap
;
73 fields
[0].num_bits
= 1;
74 fields
[0].out_value
= &access_type_buf
;
75 fields
[0].in_value
= NULL
;
77 fields
[1].tap
= jtag_info
->tap
;
78 fields
[1].num_bits
= 32;
79 fields
[1].out_value
= NULL
;
80 fields
[1].in_value
= NULL
;
82 fields
[2].tap
= jtag_info
->tap
;
83 fields
[2].num_bits
= 6;
84 fields
[2].out_value
= ®_addr_buf
;
85 fields
[2].in_value
= NULL
;
87 fields
[3].tap
= jtag_info
->tap
;
88 fields
[3].num_bits
= 1;
89 fields
[3].out_value
= &nr_w_buf
;
90 fields
[3].in_value
= NULL
;
92 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
94 fields
[1].in_value
= (uint8_t *)value
;
96 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
98 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
100 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
101 jtag_execute_queue();
102 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
108 static int arm920t_write_cp15_physical(struct target
*target
,
109 int reg_addr
, uint32_t value
)
111 struct arm920t_common
*arm920t
= target_to_arm920(target
);
112 struct arm_jtag
*jtag_info
;
113 struct scan_field fields
[4];
114 uint8_t access_type_buf
= 1;
115 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
116 uint8_t nr_w_buf
= 1;
117 uint8_t value_buf
[4];
119 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
121 buf_set_u32(value_buf
, 0, 32, value
);
123 jtag_set_end_state(TAP_IDLE
);
124 arm_jtag_scann(jtag_info
, 0xf);
125 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
127 fields
[0].tap
= jtag_info
->tap
;
128 fields
[0].num_bits
= 1;
129 fields
[0].out_value
= &access_type_buf
;
130 fields
[0].in_value
= NULL
;
132 fields
[1].tap
= jtag_info
->tap
;
133 fields
[1].num_bits
= 32;
134 fields
[1].out_value
= value_buf
;
135 fields
[1].in_value
= NULL
;
137 fields
[2].tap
= jtag_info
->tap
;
138 fields
[2].num_bits
= 6;
139 fields
[2].out_value
= ®_addr_buf
;
140 fields
[2].in_value
= NULL
;
142 fields
[3].tap
= jtag_info
->tap
;
143 fields
[3].num_bits
= 1;
144 fields
[3].out_value
= &nr_w_buf
;
145 fields
[3].in_value
= NULL
;
147 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
149 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
150 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
156 static int arm920t_execute_cp15(struct target
*target
, uint32_t cp15_opcode
,
160 struct arm920t_common
*arm920t
= target_to_arm920(target
);
161 struct arm_jtag
*jtag_info
;
162 struct scan_field fields
[4];
163 uint8_t access_type_buf
= 0; /* interpreted access */
164 uint8_t reg_addr_buf
= 0x0;
165 uint8_t nr_w_buf
= 0;
166 uint8_t cp15_opcode_buf
[4];
168 jtag_info
= &arm920t
->arm7_9_common
.jtag_info
;
170 jtag_set_end_state(TAP_IDLE
);
171 arm_jtag_scann(jtag_info
, 0xf);
172 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
174 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
176 fields
[0].tap
= jtag_info
->tap
;
177 fields
[0].num_bits
= 1;
178 fields
[0].out_value
= &access_type_buf
;
179 fields
[0].in_value
= NULL
;
181 fields
[1].tap
= jtag_info
->tap
;
182 fields
[1].num_bits
= 32;
183 fields
[1].out_value
= cp15_opcode_buf
;
184 fields
[1].in_value
= NULL
;
186 fields
[2].tap
= jtag_info
->tap
;
187 fields
[2].num_bits
= 6;
188 fields
[2].out_value
= ®_addr_buf
;
189 fields
[2].in_value
= NULL
;
191 fields
[3].tap
= jtag_info
->tap
;
192 fields
[3].num_bits
= 1;
193 fields
[3].out_value
= &nr_w_buf
;
194 fields
[3].in_value
= NULL
;
196 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
198 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
199 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
200 retval
= arm7_9_execute_sys_speed(target
);
201 if (retval
!= ERROR_OK
)
204 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
206 LOG_ERROR("failed executing JTAG queue");
213 static int arm920t_read_cp15_interpreted(struct target
*target
,
214 uint32_t cp15_opcode
, uint32_t address
, uint32_t *value
)
216 struct arm
*armv4_5
= target_to_arm(target
);
219 uint32_t cp15c15
= 0x0;
220 struct reg
*r
= armv4_5
->core_cache
->reg_list
;
222 /* load address into R1 */
224 arm9tdmi_write_core_regs(target
, 0x2, regs
);
226 /* read-modify-write CP15 test state register
227 * to enable interpreted access mode */
228 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
229 jtag_execute_queue();
230 cp15c15
|= 1; /* set interpret mode */
231 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
233 /* execute CP15 instruction and ARM load (reading from coprocessor) */
234 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
236 /* disable interpreted access mode */
237 cp15c15
&= ~1U; /* clear interpret mode */
238 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
240 /* retrieve value from R0 */
242 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
243 jtag_execute_queue();
245 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
246 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
249 if (!is_arm_mode(armv4_5
->core_mode
))
259 int arm920t_write_cp15_interpreted(struct target
*target
,
260 uint32_t cp15_opcode
, uint32_t value
, uint32_t address
)
262 uint32_t cp15c15
= 0x0;
263 struct arm
*armv4_5
= target_to_arm(target
);
265 struct reg
*r
= armv4_5
->core_cache
->reg_list
;
267 /* load value, address into R0, R1 */
270 arm9tdmi_write_core_regs(target
, 0x3, regs
);
272 /* read-modify-write CP15 test state register
273 * to enable interpreted access mode */
274 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
275 jtag_execute_queue();
276 cp15c15
|= 1; /* set interpret mode */
277 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
279 /* execute CP15 instruction and ARM store (writing to coprocessor) */
280 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
282 /* disable interpreted access mode */
283 cp15c15
&= ~1U; /* set interpret mode */
284 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
287 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
290 if (!is_arm_mode(armv4_5
->core_mode
))
300 uint32_t arm920t_get_ttb(struct target
*target
)
305 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
312 void arm920t_disable_mmu_caches(struct target
*target
, int mmu
, int d_u_cache
, int i_cache
)
314 uint32_t cp15_control
;
316 /* read cp15 control register */
317 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
318 jtag_execute_queue();
321 cp15_control
&= ~0x1U
;
324 cp15_control
&= ~0x4U
;
327 cp15_control
&= ~0x1000U
;
329 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
333 void arm920t_enable_mmu_caches(struct target
*target
, int mmu
, int d_u_cache
, int i_cache
)
335 uint32_t cp15_control
;
337 /* read cp15 control register */
338 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
339 jtag_execute_queue();
342 cp15_control
|= 0x1U
;
345 cp15_control
|= 0x4U
;
348 cp15_control
|= 0x1000U
;
350 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
354 void arm920t_post_debug_entry(struct target
*target
)
357 struct arm920t_common
*arm920t
= target_to_arm920(target
);
359 /* examine cp15 control reg */
360 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
361 jtag_execute_queue();
362 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm920t
->cp15_control_reg
);
364 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
366 uint32_t cache_type_reg
;
367 /* identify caches */
368 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
369 jtag_execute_queue();
370 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
373 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
374 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
375 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
377 /* save i/d fault status and address register */
378 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
379 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
380 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
381 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
383 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
", I FAR: 0x%8.8" PRIx32
"",
384 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
386 if (arm920t
->preserve_cache
)
388 /* read-modify-write CP15 test state register
389 * to disable I/D-cache linefills */
390 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
391 jtag_execute_queue();
393 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
398 void arm920t_pre_restore_context(struct target
*target
)
401 struct arm920t_common
*arm920t
= target_to_arm920(target
);
403 /* restore i/d fault status and address register */
404 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
405 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
406 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
407 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
409 /* read-modify-write CP15 test state register
410 * to reenable I/D-cache linefills */
411 if (arm920t
->preserve_cache
)
413 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
414 jtag_execute_queue();
416 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
420 static const char arm920_not
[] = "target is not an ARM920";
422 static int arm920t_verify_pointer(struct command_context
*cmd_ctx
,
423 struct arm920t_common
*arm920t
)
425 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
) {
426 command_print(cmd_ctx
, arm920_not
);
427 return ERROR_TARGET_INVALID
;
433 /** Logs summary of ARM920 state for a halted target. */
434 int arm920t_arch_state(struct target
*target
)
436 static const char *state
[] =
438 "disabled", "enabled"
441 struct arm920t_common
*arm920t
= target_to_arm920(target
);
444 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
446 LOG_ERROR("BUG: %s", arm920_not
);
447 return ERROR_TARGET_INVALID
;
450 armv4_5
= &arm920t
->arm7_9_common
.armv4_5_common
;
452 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
453 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
454 "MMU: %s, D-Cache: %s, I-Cache: %s",
455 arm_state_strings
[armv4_5
->core_state
],
456 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
457 arm_mode_name(armv4_5
->core_mode
),
458 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32),
459 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
460 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
461 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
462 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
467 static int arm920_mmu(struct target
*target
, int *enabled
)
469 if (target
->state
!= TARGET_HALTED
) {
470 LOG_ERROR("%s: target not halted", __func__
);
471 return ERROR_TARGET_INVALID
;
474 *enabled
= target_to_arm920(target
)->armv4_5_mmu
.mmu_enabled
;
478 static int arm920_virt2phys(struct target
*target
,
479 uint32_t virt
, uint32_t *phys
)
481 /** @todo Implement this! */
482 LOG_ERROR("%s: not implemented", __func__
);
486 /** Reads a buffer, in the specified word size, with current MMU settings. */
487 int arm920t_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
491 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
497 static int arm920t_read_phys_memory(struct target
*target
,
498 uint32_t address
, uint32_t size
,
499 uint32_t count
, uint8_t *buffer
)
501 struct arm920t_common
*arm920t
= target_to_arm920(target
);
503 return armv4_5_mmu_read_physical(target
, &arm920t
->armv4_5_mmu
,
504 address
, size
, count
, buffer
);
507 static int arm920t_write_phys_memory(struct target
*target
,
508 uint32_t address
, uint32_t size
,
509 uint32_t count
, uint8_t *buffer
)
511 struct arm920t_common
*arm920t
= target_to_arm920(target
);
513 return armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
,
514 address
, size
, count
, buffer
);
518 /** Writes a buffer, in the specified word size, with current MMU settings. */
519 int arm920t_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
523 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
526 /* This fn is used to write breakpoints, so we need to make sure
527 * that the data cache is flushed and the instruction cache is
530 if (((size
== 4) || (size
== 2)) && (count
== 1))
532 struct arm920t_common
*arm920t
= target_to_arm920(target
);
534 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
536 LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
537 /* MCR p15,0,Rd,c7,c10,2 */
538 retval
= arm920t_write_cp15_interpreted(target
, 0xee070f5e, 0x0, address
);
539 if (retval
!= ERROR_OK
)
543 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
545 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
546 retval
= arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
547 if (retval
!= ERROR_OK
)
556 int arm920t_soft_reset_halt(struct target
*target
)
558 int retval
= ERROR_OK
;
559 struct arm920t_common
*arm920t
= target_to_arm920(target
);
560 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
561 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
562 struct reg
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
564 if ((retval
= target_halt(target
)) != ERROR_OK
)
569 long long then
= timeval_ms();
571 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
573 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
575 embeddedice_read_reg(dbg_stat
);
576 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
584 if (debug_level
>= 3)
586 /* do not eat all CPU, time out after 1 se*/
595 LOG_ERROR("Failed to halt CPU after 1 sec");
596 return ERROR_TARGET_TIMEOUT
;
599 target
->state
= TARGET_HALTED
;
601 /* SVC, ARM state, IRQ and FIQ disabled */
604 cpsr
= buf_get_u32(armv4_5
->cpsr
->value
, 0, 32);
607 arm_set_cpsr(armv4_5
, cpsr
);
608 armv4_5
->cpsr
->dirty
= 1;
610 /* start fetching from 0x0 */
611 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
612 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
613 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
615 arm920t_disable_mmu_caches(target
, 1, 1, 1);
616 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
617 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
618 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
620 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
628 /* FIXME remove forward decls */
629 static int arm920t_mrc(struct target
*target
, int cpnum
,
630 uint32_t op1
, uint32_t op2
,
631 uint32_t CRn
, uint32_t CRm
,
633 static int arm920t_mcr(struct target
*target
, int cpnum
,
634 uint32_t op1
, uint32_t op2
,
635 uint32_t CRn
, uint32_t CRm
,
638 int arm920t_init_arch_info(struct target
*target
, struct arm920t_common
*arm920t
, struct jtag_tap
*tap
)
640 struct arm7_9_common
*arm7_9
= &arm920t
->arm7_9_common
;
642 arm7_9
->armv4_5_common
.mrc
= arm920t_mrc
;
643 arm7_9
->armv4_5_common
.mcr
= arm920t_mcr
;
645 /* initialize arm7/arm9 specific info (including armv4_5) */
646 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
648 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
650 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
651 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
653 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
654 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
655 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
656 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
657 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
658 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
659 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
660 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
662 /* disabling linefills leads to lockups, so keep them enabled for now
663 * this doesn't affect correctness, but might affect timing issues, if
664 * important data is evicted from the cache during the debug session
666 arm920t
->preserve_cache
= 0;
668 /* override hw single-step capability from ARM9TDMI */
669 arm7_9
->has_single_step
= 1;
674 static int arm920t_target_create(struct target
*target
, Jim_Interp
*interp
)
676 struct arm920t_common
*arm920t
= calloc(1,sizeof(struct arm920t_common
));
678 return arm920t_init_arch_info(target
, arm920t
, target
->tap
);
681 COMMAND_HANDLER(arm920t_handle_read_cache_command
)
683 int retval
= ERROR_OK
;
684 struct target
*target
= get_current_target(CMD_CTX
);
685 struct arm920t_common
*arm920t
= target_to_arm920(target
);
686 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
687 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
689 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
691 uint32_t *regs_p
[16];
692 uint32_t C15_C_D_Ind
, C15_C_I_Ind
;
695 struct arm920t_cache_line d_cache
[8][64], i_cache
[8][64];
699 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
700 if (retval
!= ERROR_OK
)
705 command_print(CMD_CTX
, "usage: arm920t read_cache <filename>");
709 if ((output
= fopen(CMD_ARGV
[0], "w")) == NULL
)
711 LOG_DEBUG("error opening cache content file");
715 for (i
= 0; i
< 16; i
++)
716 regs_p
[i
] = ®s
[i
];
718 /* disable MMU and Caches */
719 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
720 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
724 cp15_ctrl_saved
= cp15_ctrl
;
725 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
726 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
728 /* read CP15 test state register */
729 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
730 jtag_execute_queue();
732 /* read DCache content */
733 fprintf(output
, "DCache:\n");
735 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
736 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
738 fprintf(output
, "\nsegment: %i\n----------", segment
);
740 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
741 regs
[0] = 0x0 | (segment
<< 5);
742 arm9tdmi_write_core_regs(target
, 0x1, regs
);
744 /* set interpret mode */
746 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
748 /* D CAM Read, loads current victim into C15.C.D.Ind */
749 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
751 /* read current victim */
752 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
754 /* clear interpret mode */
756 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
758 for (index
= 0; index
< 64; index
++)
760 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
761 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
762 arm9tdmi_write_core_regs(target
, 0x1, regs
);
764 /* set interpret mode */
766 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
768 /* Write DCache victim */
769 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
772 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
775 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
777 /* clear interpret mode */
779 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
781 /* read D RAM and CAM content */
782 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
783 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
788 d_cache
[segment
][index
].cam
= regs
[9];
791 regs
[9] &= 0xfffffffe;
792 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32
", content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
794 for (i
= 1; i
< 9; i
++)
796 d_cache
[segment
][index
].data
[i
] = regs
[i
];
797 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n", i
-1, regs
[i
]);
802 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
803 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
804 arm9tdmi_write_core_regs(target
, 0x1, regs
);
806 /* set interpret mode */
808 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
810 /* Write DCache victim */
811 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
813 /* clear interpret mode */
815 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
818 /* read ICache content */
819 fprintf(output
, "ICache:\n");
821 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
822 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
824 fprintf(output
, "segment: %i\n----------", segment
);
826 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
827 regs
[0] = 0x0 | (segment
<< 5);
828 arm9tdmi_write_core_regs(target
, 0x1, regs
);
830 /* set interpret mode */
832 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
834 /* I CAM Read, loads current victim into C15.C.I.Ind */
835 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
837 /* read current victim */
838 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
840 /* clear interpret mode */
842 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
844 for (index
= 0; index
< 64; index
++)
846 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
847 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
848 arm9tdmi_write_core_regs(target
, 0x1, regs
);
850 /* set interpret mode */
852 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
854 /* Write ICache victim */
855 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
858 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
861 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
863 /* clear interpret mode */
865 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
867 /* read I RAM and CAM content */
868 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
869 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
874 i_cache
[segment
][index
].cam
= regs
[9];
877 regs
[9] &= 0xfffffffe;
878 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32
", content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
880 for (i
= 1; i
< 9; i
++)
882 i_cache
[segment
][index
].data
[i
] = regs
[i
];
883 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n", i
-1, regs
[i
]);
887 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
888 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
889 arm9tdmi_write_core_regs(target
, 0x1, regs
);
891 /* set interpret mode */
893 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
895 /* Write ICache victim */
896 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
898 /* clear interpret mode */
900 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
903 /* restore CP15 MMU and Cache settings */
904 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
906 command_print(CMD_CTX
, "cache content successfully output to %s", CMD_ARGV
[0]);
910 if (!is_arm_mode(armv4_5
->core_mode
))
913 /* force writeback of the valid data */
914 r
= armv4_5
->core_cache
->reg_list
;
915 r
[0].dirty
= r
[0].valid
;
916 r
[1].dirty
= r
[1].valid
;
917 r
[2].dirty
= r
[2].valid
;
918 r
[3].dirty
= r
[3].valid
;
919 r
[4].dirty
= r
[4].valid
;
920 r
[5].dirty
= r
[5].valid
;
921 r
[6].dirty
= r
[6].valid
;
922 r
[7].dirty
= r
[7].valid
;
924 r
= arm_reg_current(armv4_5
, 8);
927 r
= arm_reg_current(armv4_5
, 9);
933 COMMAND_HANDLER(arm920t_handle_read_mmu_command
)
935 int retval
= ERROR_OK
;
936 struct target
*target
= get_current_target(CMD_CTX
);
937 struct arm920t_common
*arm920t
= target_to_arm920(target
);
938 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
939 struct arm
*armv4_5
= &arm7_9
->armv4_5_common
;
941 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
943 uint32_t *regs_p
[16];
946 uint32_t Dlockdown
, Ilockdown
;
947 struct arm920t_tlb_entry d_tlb
[64], i_tlb
[64];
951 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
952 if (retval
!= ERROR_OK
)
957 command_print(CMD_CTX
, "usage: arm920t read_mmu <filename>");
961 if ((output
= fopen(CMD_ARGV
[0], "w")) == NULL
)
963 LOG_DEBUG("error opening mmu content file");
967 for (i
= 0; i
< 16; i
++)
968 regs_p
[i
] = ®s
[i
];
970 /* disable MMU and Caches */
971 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
972 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
976 cp15_ctrl_saved
= cp15_ctrl
;
977 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
978 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
980 /* read CP15 test state register */
981 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
982 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
987 /* prepare reading D TLB content
990 /* set interpret mode */
992 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
994 /* Read D TLB lockdown */
995 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
997 /* clear interpret mode */
999 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1001 /* read D TLB lockdown stored to r1 */
1002 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1003 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1007 Dlockdown
= regs
[1];
1009 for (victim
= 0; victim
< 64; victim
+= 8)
1011 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1012 * base remains unchanged, victim goes through entries 0 to 63 */
1013 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1014 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1016 /* set interpret mode */
1018 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1020 /* Write D TLB lockdown */
1021 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1023 /* Read D TLB CAM */
1024 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1026 /* clear interpret mode */
1028 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1030 /* read D TLB CAM content stored to r2-r9 */
1031 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1032 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1037 for (i
= 0; i
< 8; i
++)
1038 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1041 for (victim
= 0; victim
< 64; victim
++)
1043 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1044 * base remains unchanged, victim goes through entries 0 to 63 */
1045 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1046 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1048 /* set interpret mode */
1050 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1052 /* Write D TLB lockdown */
1053 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1055 /* Read D TLB RAM1 */
1056 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1058 /* Read D TLB RAM2 */
1059 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1061 /* clear interpret mode */
1063 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1065 /* read D TLB RAM content stored to r2 and r3 */
1066 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1067 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1072 d_tlb
[victim
].ram1
= regs
[2];
1073 d_tlb
[victim
].ram2
= regs
[3];
1076 /* restore D TLB lockdown */
1077 regs
[1] = Dlockdown
;
1078 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1080 /* Write D TLB lockdown */
1081 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1083 /* prepare reading I TLB content
1086 /* set interpret mode */
1088 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1090 /* Read I TLB lockdown */
1091 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1093 /* clear interpret mode */
1095 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1097 /* read I TLB lockdown stored to r1 */
1098 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1099 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1103 Ilockdown
= regs
[1];
1105 for (victim
= 0; victim
< 64; victim
+= 8)
1107 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1108 * base remains unchanged, victim goes through entries 0 to 63 */
1109 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1110 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1112 /* set interpret mode */
1114 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1116 /* Write I TLB lockdown */
1117 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1119 /* Read I TLB CAM */
1120 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1122 /* clear interpret mode */
1124 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1126 /* read I TLB CAM content stored to r2-r9 */
1127 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1128 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1133 for (i
= 0; i
< 8; i
++)
1134 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1137 for (victim
= 0; victim
< 64; victim
++)
1139 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1140 * base remains unchanged, victim goes through entries 0 to 63 */
1141 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1142 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1144 /* set interpret mode */
1146 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1148 /* Write I TLB lockdown */
1149 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1151 /* Read I TLB RAM1 */
1152 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1154 /* Read I TLB RAM2 */
1155 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1157 /* clear interpret mode */
1159 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1161 /* read I TLB RAM content stored to r2 and r3 */
1162 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1163 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1168 i_tlb
[victim
].ram1
= regs
[2];
1169 i_tlb
[victim
].ram2
= regs
[3];
1172 /* restore I TLB lockdown */
1173 regs
[1] = Ilockdown
;
1174 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1176 /* Write I TLB lockdown */
1177 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1179 /* restore CP15 MMU and Cache settings */
1180 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1182 /* output data to file */
1183 fprintf(output
, "D TLB content:\n");
1184 for (i
= 0; i
< 64; i
++)
1186 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1189 fprintf(output
, "\n\nI TLB content:\n");
1190 for (i
= 0; i
< 64; i
++)
1192 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1195 command_print(CMD_CTX
, "mmu content successfully output to %s", CMD_ARGV
[0]);
1199 if (!is_arm_mode(armv4_5
->core_mode
))
1202 /* force writeback of the valid data */
1203 r
= armv4_5
->core_cache
->reg_list
;
1204 r
[0].dirty
= r
[0].valid
;
1205 r
[1].dirty
= r
[1].valid
;
1206 r
[2].dirty
= r
[2].valid
;
1207 r
[3].dirty
= r
[3].valid
;
1208 r
[4].dirty
= r
[4].valid
;
1209 r
[5].dirty
= r
[5].valid
;
1210 r
[6].dirty
= r
[6].valid
;
1211 r
[7].dirty
= r
[7].valid
;
1213 r
= arm_reg_current(armv4_5
, 8);
1214 r
->dirty
= r
->valid
;
1216 r
= arm_reg_current(armv4_5
, 9);
1217 r
->dirty
= r
->valid
;
1222 COMMAND_HANDLER(arm920t_handle_cp15_command
)
1225 struct target
*target
= get_current_target(CMD_CTX
);
1226 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1228 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1229 if (retval
!= ERROR_OK
)
1232 if (target
->state
!= TARGET_HALTED
)
1234 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1238 /* one or more argument, access a single register (write if second argument is given */
1242 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], address
);
1247 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1249 command_print(CMD_CTX
, "couldn't access reg %i", address
);
1252 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1257 command_print(CMD_CTX
, "%i: %8.8" PRIx32
"", address
, value
);
1259 else if (CMD_ARGC
== 2)
1262 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1263 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1265 command_print(CMD_CTX
, "couldn't access reg %i", address
);
1268 command_print(CMD_CTX
, "%i: %8.8" PRIx32
"", address
, value
);
1275 COMMAND_HANDLER(arm920t_handle_cp15i_command
)
1278 struct target
*target
= get_current_target(CMD_CTX
);
1279 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1281 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1282 if (retval
!= ERROR_OK
)
1286 if (target
->state
!= TARGET_HALTED
)
1288 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1292 /* one or more argument, access a single register (write if second argument is given */
1296 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], opcode
);
1301 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1303 command_print(CMD_CTX
, "couldn't execute %8.8" PRIx32
"", opcode
);
1307 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
"", opcode
, value
);
1309 else if (CMD_ARGC
== 2)
1312 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1313 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1315 command_print(CMD_CTX
, "couldn't execute %8.8" PRIx32
"", opcode
);
1318 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
"", opcode
, value
);
1320 else if (CMD_ARGC
== 3)
1323 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1325 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
1326 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1328 command_print(CMD_CTX
, "couldn't execute %8.8" PRIx32
"", opcode
);
1331 command_print(CMD_CTX
, "%8.8" PRIx32
": %8.8" PRIx32
" %8.8" PRIx32
"", opcode
, value
, address
);
1336 command_print(CMD_CTX
, "usage: arm920t cp15i <opcode> [value] [address]");
1342 COMMAND_HANDLER(arm920t_handle_cache_info_command
)
1345 struct target
*target
= get_current_target(CMD_CTX
);
1346 struct arm920t_common
*arm920t
= target_to_arm920(target
);
1348 retval
= arm920t_verify_pointer(CMD_CTX
, arm920t
);
1349 if (retval
!= ERROR_OK
)
1352 return armv4_5_handle_cache_info_command(CMD_CTX
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1356 static int arm920t_mrc(struct target
*target
, int cpnum
,
1357 uint32_t op1
, uint32_t op2
,
1358 uint32_t CRn
, uint32_t CRm
,
1363 LOG_ERROR("Only cp15 is supported");
1368 return arm920t_read_cp15_interpreted(target
,
1369 ARMV4_5_MRC(cpnum
, op1
, 0, CRn
, CRm
, op2
),
1373 static int arm920t_mcr(struct target
*target
, int cpnum
,
1374 uint32_t op1
, uint32_t op2
,
1375 uint32_t CRn
, uint32_t CRm
,
1380 LOG_ERROR("Only cp15 is supported");
1384 /* write "from" r0 */
1385 return arm920t_write_cp15_interpreted(target
,
1386 ARMV4_5_MCR(cpnum
, op1
, 0, CRn
, CRm
, op2
),
1390 static const struct command_registration arm920t_exec_command_handlers
[] = {
1393 .handler
= &arm920t_handle_cp15_command
,
1394 .mode
= COMMAND_EXEC
,
1395 .help
= "display/modify cp15 register",
1396 .usage
= "<num> [value]",
1400 .handler
= &arm920t_handle_cp15i_command
,
1401 .mode
= COMMAND_EXEC
,
1402 .help
= "display/modify cp15 (interpreted access)",
1403 .usage
= "<opcode> [value] [address]",
1406 .name
= "cache_info",
1407 .handler
= &arm920t_handle_cache_info_command
,
1408 .mode
= COMMAND_EXEC
,
1409 .help
= "display information about target caches",
1412 .name
= "read_cache",
1413 .handler
= &arm920t_handle_read_cache_command
,
1414 .mode
= COMMAND_EXEC
,
1415 .help
= "display I/D cache content",
1419 .handler
= &arm920t_handle_read_mmu_command
,
1420 .mode
= COMMAND_EXEC
,
1421 .help
= "display I/D mmu content",
1423 COMMAND_REGISTRATION_DONE
1425 const struct command_registration arm920t_command_handlers
[] = {
1427 .chain
= arm9tdmi_command_handlers
,
1431 .mode
= COMMAND_ANY
,
1432 .help
= "arm920t command group",
1433 .chain
= arm920t_exec_command_handlers
,
1435 COMMAND_REGISTRATION_DONE
1438 /** Holds methods for ARM920 targets. */
1439 struct target_type arm920t_target
=
1443 .poll
= arm7_9_poll
,
1444 .arch_state
= arm920t_arch_state
,
1446 .target_request_data
= arm7_9_target_request_data
,
1448 .halt
= arm7_9_halt
,
1449 .resume
= arm7_9_resume
,
1450 .step
= arm7_9_step
,
1452 .assert_reset
= arm7_9_assert_reset
,
1453 .deassert_reset
= arm7_9_deassert_reset
,
1454 .soft_reset_halt
= arm920t_soft_reset_halt
,
1456 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
1458 .read_memory
= arm920t_read_memory
,
1459 .write_memory
= arm920t_write_memory
,
1460 .read_phys_memory
= arm920t_read_phys_memory
,
1461 .write_phys_memory
= arm920t_write_phys_memory
,
1463 .virt2phys
= arm920_virt2phys
,
1465 .bulk_write_memory
= arm7_9_bulk_write_memory
,
1467 .checksum_memory
= arm_checksum_memory
,
1468 .blank_check_memory
= arm_blank_check_memory
,
1470 .run_algorithm
= armv4_5_run_algorithm
,
1472 .add_breakpoint
= arm7_9_add_breakpoint
,
1473 .remove_breakpoint
= arm7_9_remove_breakpoint
,
1474 .add_watchpoint
= arm7_9_add_watchpoint
,
1475 .remove_watchpoint
= arm7_9_remove_watchpoint
,
1477 .commands
= arm920t_command_handlers
,
1478 .target_create
= arm920t_target_create
,
1479 .init_target
= arm9tdmi_init_target
,
1480 .examine
= arm7_9_examine
,
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