1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 /* forward declarations */
50 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
);
51 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_quit(void);
53 int arm920t_arch_state(struct target_s
*target
);
54 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
56 int arm920t_soft_reset_halt(struct target_s
*target
);
58 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
60 target_type_t arm920t_target
=
65 .arch_state
= arm920t_arch_state
,
67 .target_request_data
= arm7_9_target_request_data
,
70 .resume
= arm7_9_resume
,
73 .assert_reset
= arm7_9_assert_reset
,
74 .deassert_reset
= arm7_9_deassert_reset
,
75 .soft_reset_halt
= arm920t_soft_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm920t_read_memory
,
80 .write_memory
= arm920t_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
83 .blank_check_memory
= arm7_9_blank_check_memory
,
85 .run_algorithm
= armv4_5_run_algorithm
,
87 .add_breakpoint
= arm7_9_add_breakpoint
,
88 .remove_breakpoint
= arm7_9_remove_breakpoint
,
89 .add_watchpoint
= arm7_9_add_watchpoint
,
90 .remove_watchpoint
= arm7_9_remove_watchpoint
,
92 .register_commands
= arm920t_register_commands
,
93 .target_create
= arm920t_target_create
,
94 .init_target
= arm920t_init_target
,
95 .examine
= arm9tdmi_examine
,
99 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
101 armv4_5_common_t
*armv4_5
= target
->arch_info
;
102 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
103 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
104 scan_field_t fields
[4];
105 u8 access_type_buf
= 1;
106 u8 reg_addr_buf
= reg_addr
& 0x3f;
109 jtag_add_end_state(TAP_IDLE
);
110 arm_jtag_scann(jtag_info
, 0xf);
111 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
113 fields
[0].tap
= jtag_info
->tap
;
114 fields
[0].num_bits
= 1;
115 fields
[0].out_value
= &access_type_buf
;
116 fields
[0].in_value
= NULL
;
117 fields
[0].in_handler
= NULL
;
119 fields
[1].tap
= jtag_info
->tap
;
120 fields
[1].num_bits
= 32;
121 fields
[1].out_value
= NULL
;
122 fields
[1].in_value
= NULL
;
123 fields
[1].in_handler
= NULL
;
125 fields
[2].tap
= jtag_info
->tap
;
126 fields
[2].num_bits
= 6;
127 fields
[2].out_value
= ®_addr_buf
;
128 fields
[2].in_value
= NULL
;
129 fields
[2].in_handler
= NULL
;
131 fields
[3].tap
= jtag_info
->tap
;
132 fields
[3].num_bits
= 1;
133 fields
[3].out_value
= &nr_w_buf
;
134 fields
[3].in_value
= NULL
;
135 fields
[3].in_handler
= NULL
;
137 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
140 fields
[1].in_value
= tmp
;
142 jtag_add_dr_scan_now(4, fields
, TAP_INVALID
);
144 *value
=le_to_h_u32(tmp
);
146 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
147 jtag_execute_queue();
148 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
154 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
156 armv4_5_common_t
*armv4_5
= target
->arch_info
;
157 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
158 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
159 scan_field_t fields
[4];
160 u8 access_type_buf
= 1;
161 u8 reg_addr_buf
= reg_addr
& 0x3f;
165 buf_set_u32(value_buf
, 0, 32, value
);
167 jtag_add_end_state(TAP_IDLE
);
168 arm_jtag_scann(jtag_info
, 0xf);
169 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
171 fields
[0].tap
= jtag_info
->tap
;
172 fields
[0].num_bits
= 1;
173 fields
[0].out_value
= &access_type_buf
;
175 fields
[0].in_value
= NULL
;
178 fields
[0].in_handler
= NULL
;
181 fields
[1].tap
= jtag_info
->tap
;
182 fields
[1].num_bits
= 32;
183 fields
[1].out_value
= value_buf
;
185 fields
[1].in_value
= NULL
;
188 fields
[1].in_handler
= NULL
;
191 fields
[2].tap
= jtag_info
->tap
;
192 fields
[2].num_bits
= 6;
193 fields
[2].out_value
= ®_addr_buf
;
195 fields
[2].in_value
= NULL
;
198 fields
[2].in_handler
= NULL
;
201 fields
[3].tap
= jtag_info
->tap
;
202 fields
[3].num_bits
= 1;
203 fields
[3].out_value
= &nr_w_buf
;
205 fields
[3].in_value
= NULL
;
208 fields
[3].in_handler
= NULL
;
211 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
213 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
214 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
220 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
223 armv4_5_common_t
*armv4_5
= target
->arch_info
;
224 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
225 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
226 scan_field_t fields
[4];
227 u8 access_type_buf
= 0; /* interpreted access */
228 u8 reg_addr_buf
= 0x0;
230 u8 cp15_opcode_buf
[4];
232 jtag_add_end_state(TAP_IDLE
);
233 arm_jtag_scann(jtag_info
, 0xf);
234 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
236 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
238 fields
[0].tap
= jtag_info
->tap
;
239 fields
[0].num_bits
= 1;
240 fields
[0].out_value
= &access_type_buf
;
242 fields
[0].in_value
= NULL
;
245 fields
[0].in_handler
= NULL
;
248 fields
[1].tap
= jtag_info
->tap
;
249 fields
[1].num_bits
= 32;
250 fields
[1].out_value
= cp15_opcode_buf
;
252 fields
[1].in_value
= NULL
;
255 fields
[1].in_handler
= NULL
;
258 fields
[2].tap
= jtag_info
->tap
;
259 fields
[2].num_bits
= 6;
260 fields
[2].out_value
= ®_addr_buf
;
262 fields
[2].in_value
= NULL
;
265 fields
[2].in_handler
= NULL
;
268 fields
[3].tap
= jtag_info
->tap
;
269 fields
[3].num_bits
= 1;
270 fields
[3].out_value
= &nr_w_buf
;
272 fields
[3].in_value
= NULL
;
275 fields
[3].in_handler
= NULL
;
278 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
280 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
281 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
282 retval
= arm7_9_execute_sys_speed(target
);
283 if (retval
!= ERROR_OK
)
286 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
288 LOG_ERROR("failed executing JTAG queue, exiting");
295 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
297 armv4_5_common_t
*armv4_5
= target
->arch_info
;
302 /* load address into R1 */
304 arm9tdmi_write_core_regs(target
, 0x2, regs
);
306 /* read-modify-write CP15 test state register
307 * to enable interpreted access mode */
308 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
309 jtag_execute_queue();
310 cp15c15
|= 1; /* set interpret mode */
311 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
313 /* execute CP15 instruction and ARM load (reading from coprocessor) */
314 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
316 /* disable interpreted access mode */
317 cp15c15
&= ~1U; /* clear interpret mode */
318 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
320 /* retrieve value from R0 */
322 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
323 jtag_execute_queue();
325 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
326 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
329 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
332 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
333 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
338 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
341 armv4_5_common_t
*armv4_5
= target
->arch_info
;
344 /* load value, address into R0, R1 */
347 arm9tdmi_write_core_regs(target
, 0x3, regs
);
349 /* read-modify-write CP15 test state register
350 * to enable interpreted access mode */
351 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
352 jtag_execute_queue();
353 cp15c15
|= 1; /* set interpret mode */
354 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
356 /* execute CP15 instruction and ARM store (writing to coprocessor) */
357 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
359 /* disable interpreted access mode */
360 cp15c15
&= ~1U; /* set interpret mode */
361 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
363 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
364 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
367 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
370 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
371 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
376 u32
arm920t_get_ttb(target_t
*target
)
381 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
387 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
391 /* read cp15 control register */
392 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
393 jtag_execute_queue();
396 cp15_control
&= ~0x1U
;
399 cp15_control
&= ~0x4U
;
402 cp15_control
&= ~0x1000U
;
404 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
407 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
411 /* read cp15 control register */
412 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
413 jtag_execute_queue();
416 cp15_control
|= 0x1U
;
419 cp15_control
|= 0x4U
;
422 cp15_control
|= 0x1000U
;
424 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
427 void arm920t_post_debug_entry(target_t
*target
)
430 armv4_5_common_t
*armv4_5
= target
->arch_info
;
431 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
432 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
433 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
435 /* examine cp15 control reg */
436 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
437 jtag_execute_queue();
438 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
440 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
443 /* identify caches */
444 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
445 jtag_execute_queue();
446 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
449 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
450 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
451 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
453 /* save i/d fault status and address register */
454 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
455 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
456 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
457 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
459 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
460 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
462 if (arm920t
->preserve_cache
)
464 /* read-modify-write CP15 test state register
465 * to disable I/D-cache linefills */
466 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
467 jtag_execute_queue();
469 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
473 void arm920t_pre_restore_context(target_t
*target
)
476 armv4_5_common_t
*armv4_5
= target
->arch_info
;
477 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
478 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
479 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
481 /* restore i/d fault status and address register */
482 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
483 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
484 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
485 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
487 /* read-modify-write CP15 test state register
488 * to reenable I/D-cache linefills */
489 if (arm920t
->preserve_cache
)
491 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
492 jtag_execute_queue();
494 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
498 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
500 armv4_5_common_t
*armv4_5
= target
->arch_info
;
501 arm7_9_common_t
*arm7_9
;
502 arm9tdmi_common_t
*arm9tdmi
;
503 arm920t_common_t
*arm920t
;
505 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
510 arm7_9
= armv4_5
->arch_info
;
511 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
516 arm9tdmi
= arm7_9
->arch_info
;
517 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
522 arm920t
= arm9tdmi
->arch_info
;
523 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
528 *armv4_5_p
= armv4_5
;
530 *arm9tdmi_p
= arm9tdmi
;
531 *arm920t_p
= arm920t
;
536 int arm920t_arch_state(struct target_s
*target
)
538 armv4_5_common_t
*armv4_5
= target
->arch_info
;
539 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
540 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
541 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
545 "disabled", "enabled"
548 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
550 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
554 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
555 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
556 "MMU: %s, D-Cache: %s, I-Cache: %s",
557 armv4_5_state_strings
[armv4_5
->core_state
],
558 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
559 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
560 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
561 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
562 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
563 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
564 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
569 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
573 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
578 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
581 armv4_5_common_t
*armv4_5
= target
->arch_info
;
582 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
583 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
584 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
586 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
589 if (((size
== 4) || (size
== 2)) && (count
== 1))
591 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
593 LOG_DEBUG("D-Cache enabled, writing through to main memory");
597 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
600 /* cacheable & bufferable means write-back region */
602 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
605 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
607 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
608 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
615 int arm920t_soft_reset_halt(struct target_s
*target
)
617 int retval
= ERROR_OK
;
618 armv4_5_common_t
*armv4_5
= target
->arch_info
;
619 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
620 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
621 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
622 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
624 if((retval
= target_halt(target
)) != ERROR_OK
)
629 long long then
=timeval_ms();
631 while (!(timeout
=((timeval_ms()-then
)>1000)))
633 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
635 embeddedice_read_reg(dbg_stat
);
636 if((retval
= jtag_execute_queue()) != ERROR_OK
)
646 /* do not eat all CPU, time out after 1 se*/
655 LOG_ERROR("Failed to halt CPU after 1 sec");
656 return ERROR_TARGET_TIMEOUT
;
659 target
->state
= TARGET_HALTED
;
661 /* SVC, ARM state, IRQ and FIQ disabled */
662 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
663 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
664 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
666 /* start fetching from 0x0 */
667 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
668 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
669 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
671 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
672 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
674 arm920t_disable_mmu_caches(target
, 1, 1, 1);
675 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
676 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
677 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
679 if((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
687 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
689 arm9tdmi_init_target(cmd_ctx
, target
);
694 int arm920t_quit(void)
699 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, jtag_tap_t
*tap
)
701 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
702 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
704 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
706 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
708 arm9tdmi
->arch_info
= arm920t
;
709 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
711 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
712 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
714 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
715 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
716 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
717 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
718 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
719 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
720 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
721 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
723 /* disabling linefills leads to lockups, so keep them enabled for now
724 * this doesn't affect correctness, but might affect timing issues, if
725 * important data is evicted from the cache during the debug session
727 arm920t
->preserve_cache
= 0;
729 /* override hw single-step capability from ARM9TDMI */
730 arm7_9
->has_single_step
= 1;
735 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
737 arm920t_common_t
*arm920t
= calloc(1,sizeof(arm920t_common_t
));
739 arm920t_init_arch_info(target
, arm920t
, target
->tap
);
744 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
747 command_t
*arm920t_cmd
;
750 retval
= arm9tdmi_register_commands(cmd_ctx
);
752 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
754 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
755 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
756 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
757 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
759 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
760 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
761 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
763 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
764 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
765 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
767 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
768 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
773 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
775 int retval
= ERROR_OK
;
776 target_t
*target
= get_current_target(cmd_ctx
);
777 armv4_5_common_t
*armv4_5
;
778 arm7_9_common_t
*arm7_9
;
779 arm9tdmi_common_t
*arm9tdmi
;
780 arm920t_common_t
*arm920t
;
781 arm_jtag_t
*jtag_info
;
783 u32 cp15_ctrl
, cp15_ctrl_saved
;
786 u32 C15_C_D_Ind
, C15_C_I_Ind
;
789 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
794 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
798 if ((output
= fopen(args
[0], "w")) == NULL
)
800 LOG_DEBUG("error opening cache content file");
804 for (i
= 0; i
< 16; i
++)
805 regs_p
[i
] = ®s
[i
];
807 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
809 command_print(cmd_ctx
, "current target isn't an ARM920t target");
813 jtag_info
= &arm7_9
->jtag_info
;
815 /* disable MMU and Caches */
816 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
817 if((retval
= jtag_execute_queue()) != ERROR_OK
)
821 cp15_ctrl_saved
= cp15_ctrl
;
822 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
823 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
825 /* read CP15 test state register */
826 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
827 jtag_execute_queue();
829 /* read DCache content */
830 fprintf(output
, "DCache:\n");
832 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
833 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
835 fprintf(output
, "\nsegment: %i\n----------", segment
);
837 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
838 regs
[0] = 0x0 | (segment
<< 5);
839 arm9tdmi_write_core_regs(target
, 0x1, regs
);
841 /* set interpret mode */
843 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
845 /* D CAM Read, loads current victim into C15.C.D.Ind */
846 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
848 /* read current victim */
849 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
851 /* clear interpret mode */
853 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
855 for (index
= 0; index
< 64; index
++)
857 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
858 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
859 arm9tdmi_write_core_regs(target
, 0x1, regs
);
861 /* set interpret mode */
863 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
865 /* Write DCache victim */
866 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
869 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
872 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
874 /* clear interpret mode */
876 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
878 /* read D RAM and CAM content */
879 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
880 if((retval
= jtag_execute_queue()) != ERROR_OK
)
885 d_cache
[segment
][index
].cam
= regs
[9];
888 regs
[9] &= 0xfffffffe;
889 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
891 for (i
= 1; i
< 9; i
++)
893 d_cache
[segment
][index
].data
[i
] = regs
[i
];
894 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
899 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
900 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
901 arm9tdmi_write_core_regs(target
, 0x1, regs
);
903 /* set interpret mode */
905 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
907 /* Write DCache victim */
908 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
910 /* clear interpret mode */
912 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
915 /* read ICache content */
916 fprintf(output
, "ICache:\n");
918 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
919 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
921 fprintf(output
, "segment: %i\n----------", segment
);
923 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
924 regs
[0] = 0x0 | (segment
<< 5);
925 arm9tdmi_write_core_regs(target
, 0x1, regs
);
927 /* set interpret mode */
929 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
931 /* I CAM Read, loads current victim into C15.C.I.Ind */
932 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
934 /* read current victim */
935 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
937 /* clear interpret mode */
939 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
941 for (index
= 0; index
< 64; index
++)
943 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
944 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
945 arm9tdmi_write_core_regs(target
, 0x1, regs
);
947 /* set interpret mode */
949 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
951 /* Write ICache victim */
952 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
955 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
958 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
960 /* clear interpret mode */
962 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
964 /* read I RAM and CAM content */
965 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
966 if((retval
= jtag_execute_queue()) != ERROR_OK
)
971 i_cache
[segment
][index
].cam
= regs
[9];
974 regs
[9] &= 0xfffffffe;
975 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
977 for (i
= 1; i
< 9; i
++)
979 i_cache
[segment
][index
].data
[i
] = regs
[i
];
980 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
984 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
985 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
986 arm9tdmi_write_core_regs(target
, 0x1, regs
);
988 /* set interpret mode */
990 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
992 /* Write ICache victim */
993 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
995 /* clear interpret mode */
997 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1000 /* restore CP15 MMU and Cache settings */
1001 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1003 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
1007 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1010 /* mark registers dirty. */
1011 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1012 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1013 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1014 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1015 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1016 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1017 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1018 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1019 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1020 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1025 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1027 int retval
= ERROR_OK
;
1028 target_t
*target
= get_current_target(cmd_ctx
);
1029 armv4_5_common_t
*armv4_5
;
1030 arm7_9_common_t
*arm7_9
;
1031 arm9tdmi_common_t
*arm9tdmi
;
1032 arm920t_common_t
*arm920t
;
1033 arm_jtag_t
*jtag_info
;
1035 u32 cp15_ctrl
, cp15_ctrl_saved
;
1040 u32 Dlockdown
, Ilockdown
;
1041 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1046 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1050 if ((output
= fopen(args
[0], "w")) == NULL
)
1052 LOG_DEBUG("error opening mmu content file");
1056 for (i
= 0; i
< 16; i
++)
1057 regs_p
[i
] = ®s
[i
];
1059 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1061 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1065 jtag_info
= &arm7_9
->jtag_info
;
1067 /* disable MMU and Caches */
1068 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1069 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1073 cp15_ctrl_saved
= cp15_ctrl
;
1074 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1075 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1077 /* read CP15 test state register */
1078 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1079 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1084 /* prepare reading D TLB content
1087 /* set interpret mode */
1089 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1091 /* Read D TLB lockdown */
1092 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1094 /* clear interpret mode */
1096 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1098 /* read D TLB lockdown stored to r1 */
1099 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1100 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1104 Dlockdown
= regs
[1];
1106 for (victim
= 0; victim
< 64; victim
+= 8)
1108 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1109 * base remains unchanged, victim goes through entries 0 to 63 */
1110 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1111 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1113 /* set interpret mode */
1115 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1117 /* Write D TLB lockdown */
1118 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1120 /* Read D TLB CAM */
1121 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1123 /* clear interpret mode */
1125 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1127 /* read D TLB CAM content stored to r2-r9 */
1128 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1129 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1134 for (i
= 0; i
< 8; i
++)
1135 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1138 for (victim
= 0; victim
< 64; victim
++)
1140 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1141 * base remains unchanged, victim goes through entries 0 to 63 */
1142 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1143 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1145 /* set interpret mode */
1147 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1149 /* Write D TLB lockdown */
1150 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1152 /* Read D TLB RAM1 */
1153 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1155 /* Read D TLB RAM2 */
1156 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1158 /* clear interpret mode */
1160 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1162 /* read D TLB RAM content stored to r2 and r3 */
1163 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1164 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1169 d_tlb
[victim
].ram1
= regs
[2];
1170 d_tlb
[victim
].ram2
= regs
[3];
1173 /* restore D TLB lockdown */
1174 regs
[1] = Dlockdown
;
1175 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1177 /* Write D TLB lockdown */
1178 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1180 /* prepare reading I TLB content
1183 /* set interpret mode */
1185 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1187 /* Read I TLB lockdown */
1188 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1190 /* clear interpret mode */
1192 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1194 /* read I TLB lockdown stored to r1 */
1195 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1196 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1200 Ilockdown
= regs
[1];
1202 for (victim
= 0; victim
< 64; victim
+= 8)
1204 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1205 * base remains unchanged, victim goes through entries 0 to 63 */
1206 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1207 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1209 /* set interpret mode */
1211 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1213 /* Write I TLB lockdown */
1214 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1216 /* Read I TLB CAM */
1217 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1219 /* clear interpret mode */
1221 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1223 /* read I TLB CAM content stored to r2-r9 */
1224 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1225 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1230 for (i
= 0; i
< 8; i
++)
1231 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1234 for (victim
= 0; victim
< 64; victim
++)
1236 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1237 * base remains unchanged, victim goes through entries 0 to 63 */
1238 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1239 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1241 /* set interpret mode */
1243 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1245 /* Write I TLB lockdown */
1246 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1248 /* Read I TLB RAM1 */
1249 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1251 /* Read I TLB RAM2 */
1252 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1254 /* clear interpret mode */
1256 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1258 /* read I TLB RAM content stored to r2 and r3 */
1259 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1260 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1265 i_tlb
[victim
].ram1
= regs
[2];
1266 i_tlb
[victim
].ram2
= regs
[3];
1269 /* restore I TLB lockdown */
1270 regs
[1] = Ilockdown
;
1271 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1273 /* Write I TLB lockdown */
1274 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1276 /* restore CP15 MMU and Cache settings */
1277 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1279 /* output data to file */
1280 fprintf(output
, "D TLB content:\n");
1281 for (i
= 0; i
< 64; i
++)
1283 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1286 fprintf(output
, "\n\nI TLB content:\n");
1287 for (i
= 0; i
< 64; i
++)
1289 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1292 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1296 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1299 /* mark registers dirty */
1300 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1301 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1302 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1303 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1304 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1305 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1306 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1307 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1308 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1309 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1313 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1316 target_t
*target
= get_current_target(cmd_ctx
);
1317 armv4_5_common_t
*armv4_5
;
1318 arm7_9_common_t
*arm7_9
;
1319 arm9tdmi_common_t
*arm9tdmi
;
1320 arm920t_common_t
*arm920t
;
1321 arm_jtag_t
*jtag_info
;
1323 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1325 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1329 jtag_info
= &arm7_9
->jtag_info
;
1331 if (target
->state
!= TARGET_HALTED
)
1333 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1337 /* one or more argument, access a single register (write if second argument is given */
1340 int address
= strtoul(args
[0], NULL
, 0);
1345 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1347 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1350 if((retval
= jtag_execute_queue()) != ERROR_OK
)
1355 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1359 u32 value
= strtoul(args
[1], NULL
, 0);
1360 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1362 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1365 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1372 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1375 target_t
*target
= get_current_target(cmd_ctx
);
1376 armv4_5_common_t
*armv4_5
;
1377 arm7_9_common_t
*arm7_9
;
1378 arm9tdmi_common_t
*arm9tdmi
;
1379 arm920t_common_t
*arm920t
;
1380 arm_jtag_t
*jtag_info
;
1382 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1384 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1388 jtag_info
= &arm7_9
->jtag_info
;
1390 if (target
->state
!= TARGET_HALTED
)
1392 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1396 /* one or more argument, access a single register (write if second argument is given */
1399 u32 opcode
= strtoul(args
[0], NULL
, 0);
1404 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1406 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1410 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1414 u32 value
= strtoul(args
[1], NULL
, 0);
1415 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1417 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1420 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1424 u32 value
= strtoul(args
[1], NULL
, 0);
1425 u32 address
= strtoul(args
[2], NULL
, 0);
1426 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1428 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1431 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1436 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1442 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1444 target_t
*target
= get_current_target(cmd_ctx
);
1445 armv4_5_common_t
*armv4_5
;
1446 arm7_9_common_t
*arm7_9
;
1447 arm9tdmi_common_t
*arm9tdmi
;
1448 arm920t_common_t
*arm920t
;
1450 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1452 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1456 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1459 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1461 target_t
*target
= get_current_target(cmd_ctx
);
1462 armv4_5_common_t
*armv4_5
;
1463 arm7_9_common_t
*arm7_9
;
1464 arm9tdmi_common_t
*arm9tdmi
;
1465 arm920t_common_t
*arm920t
;
1466 arm_jtag_t
*jtag_info
;
1468 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1470 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1474 jtag_info
= &arm7_9
->jtag_info
;
1476 if (target
->state
!= TARGET_HALTED
)
1478 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1482 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1485 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1487 target_t
*target
= get_current_target(cmd_ctx
);
1488 armv4_5_common_t
*armv4_5
;
1489 arm7_9_common_t
*arm7_9
;
1490 arm9tdmi_common_t
*arm9tdmi
;
1491 arm920t_common_t
*arm920t
;
1492 arm_jtag_t
*jtag_info
;
1494 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1496 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1500 jtag_info
= &arm7_9
->jtag_info
;
1502 if (target
->state
!= TARGET_HALTED
)
1504 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1508 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1511 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1513 target_t
*target
= get_current_target(cmd_ctx
);
1514 armv4_5_common_t
*armv4_5
;
1515 arm7_9_common_t
*arm7_9
;
1516 arm9tdmi_common_t
*arm9tdmi
;
1517 arm920t_common_t
*arm920t
;
1518 arm_jtag_t
*jtag_info
;
1520 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1522 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1526 jtag_info
= &arm7_9
->jtag_info
;
1528 if (target
->state
!= TARGET_HALTED
)
1530 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1534 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
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