src/target/arm926ejs.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 1
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm926ejs_quit();
  52 int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size);
  53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm926ejs_soft_reset_halt(struct target_s *target);
  56
  57 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
  58
  59 target_type_t arm926ejs_target =
  60 {
  61         .name = "arm926ejs",
  62
  63         .poll = arm7_9_poll,
  64         .arch_state = arm926ejs_arch_state,
  65
  66         .target_request_data = arm7_9_target_request_data,
  67
  68         .halt = arm7_9_halt,
  69         .resume = arm7_9_resume,
  70         .step = arm7_9_step,
  71
  72         .assert_reset = arm7_9_assert_reset,
  73         .deassert_reset = arm7_9_deassert_reset,
  74         .soft_reset_halt = arm926ejs_soft_reset_halt,
  75         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  76
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  78
  79         .read_memory = arm7_9_read_memory,
  80         .write_memory = arm926ejs_write_memory,
  81         .bulk_write_memory = arm7_9_bulk_write_memory,
  82         .checksum_memory = arm7_9_checksum_memory,
  83
  84         .run_algorithm = armv4_5_run_algorithm,
  85
  86         .add_breakpoint = arm7_9_add_breakpoint,
  87         .remove_breakpoint = arm7_9_remove_breakpoint,
  88         .add_watchpoint = arm7_9_add_watchpoint,
  89         .remove_watchpoint = arm7_9_remove_watchpoint,
  90
  91         .register_commands = arm926ejs_register_commands,
  92         .target_command = arm926ejs_target_command,
  93         .init_target = arm926ejs_init_target,
  94         .quit = arm926ejs_quit
  95 };
  96
  97
  98 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
  99 {
 100         u8 *in_value=field->in_check_value;
 101
 102         /* The ARM926EJ-S' instruction register is 4 bits wide */
 103         u8 t=*in_value & 0xf;
 104         if ((t == 0x0f) || (t == 0x00))
 105         {
 106                 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 107                 return ERROR_OK;
 108         }
 109         else
 110         {
 111                 return ERROR_JTAG_QUEUE_FAILED;
 112         }
 113 }
 114
 115 int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
 116 {
 117         armv4_5_common_t *armv4_5 = target->arch_info;
 118         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 119         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 120         scan_field_t fields[4];
 121         u8 address_buf[2];
 122         u8 nr_w_buf = 0;
 123         u8 access = 1;
 124
 125         buf_set_u32(address_buf, 0, 14, address);
 126
 127         jtag_add_end_state(TAP_RTI);
 128         arm_jtag_scann(jtag_info, 0xf);
 129         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 130
 131         fields[0].device = jtag_info->chain_pos;
 132         fields[0].num_bits = 32;
 133         fields[0].out_value = NULL;
 134         fields[0].out_mask = NULL;
 135         fields[0].in_value = NULL;
 136         fields[0].in_check_value = NULL;
 137         fields[0].in_check_mask = NULL;
 138         fields[0].in_handler = NULL;
 139         fields[0].in_handler_priv = NULL;
 140
 141         fields[1].device = jtag_info->chain_pos;
 142         fields[1].num_bits = 1;
 143         fields[1].out_value = &access;
 144         fields[1].out_mask = NULL;
 145         fields[1].in_value = &access;
 146         fields[1].in_check_value = NULL;
 147         fields[1].in_check_mask = NULL;
 148         fields[1].in_handler = NULL;
 149         fields[1].in_handler_priv = NULL;
 150
 151         fields[2].device = jtag_info->chain_pos;
 152         fields[2].num_bits = 14;
 153         fields[2].out_value = address_buf;
 154         fields[2].out_mask = NULL;
 155         fields[2].in_value = NULL;
 156         fields[2].in_check_value = NULL;
 157         fields[2].in_check_mask = NULL;
 158         fields[2].in_handler = NULL;
 159         fields[2].in_handler_priv = NULL;
 160
 161         fields[3].device = jtag_info->chain_pos;
 162         fields[3].num_bits = 1;
 163         fields[3].out_value = &nr_w_buf;
 164         fields[3].out_mask = NULL;
 165         fields[3].in_value = NULL;
 166         fields[3].in_check_value = NULL;
 167         fields[3].in_check_mask = NULL;
 168         fields[3].in_handler = NULL;
 169         fields[3].in_handler_priv = NULL;
 170
 171         jtag_add_dr_scan(4, fields, -1, NULL);
 172
 173         fields[0].in_handler_priv = value;
 174         fields[0].in_handler = arm_jtag_buf_to_u32;
 175
 176         do
 177         {
 178                 /* rescan with NOP, to wait for the access to complete */
 179                 access = 0;
 180                 nr_w_buf = 0;
 181                 jtag_add_dr_scan(4, fields, -1, NULL);
 182                 jtag_execute_queue();
 183         } while (buf_get_u32(&access, 0, 1) != 1);
 184
 185 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 186         DEBUG("addr: 0x%x value: %8.8x", address, *value);
 187 #endif
 188
 189         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 190
 191         return ERROR_OK;
 192 }
 193
 194 int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
 195 {
 196         armv4_5_common_t *armv4_5 = target->arch_info;
 197         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 198         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 199         scan_field_t fields[4];
 200         u8 value_buf[4];
 201         u8 address_buf[2];
 202         u8 nr_w_buf = 1;
 203         u8 access = 1;
 204
 205         buf_set_u32(address_buf, 0, 14, address);
 206         buf_set_u32(value_buf, 0, 32, value);
 207
 208         jtag_add_end_state(TAP_RTI);
 209         arm_jtag_scann(jtag_info, 0xf);
 210         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 211
 212         fields[0].device = jtag_info->chain_pos;
 213         fields[0].num_bits = 32;
 214         fields[0].out_value = value_buf;
 215         fields[0].out_mask = NULL;
 216         fields[0].in_value = NULL;
 217         fields[0].in_check_value = NULL;
 218         fields[0].in_check_mask = NULL;
 219         fields[0].in_handler = NULL;
 220         fields[0].in_handler_priv = NULL;
 221
 222         fields[1].device = jtag_info->chain_pos;
 223         fields[1].num_bits = 1;
 224         fields[1].out_value = &access;
 225         fields[1].out_mask = NULL;
 226         fields[1].in_value = &access;
 227         fields[1].in_check_value = NULL;
 228         fields[1].in_check_mask = NULL;
 229         fields[1].in_handler = NULL;
 230         fields[1].in_handler_priv = NULL;
 231
 232         fields[2].device = jtag_info->chain_pos;
 233         fields[2].num_bits = 14;
 234         fields[2].out_value = address_buf;
 235         fields[2].out_mask = NULL;
 236         fields[2].in_value = NULL;
 237         fields[2].in_check_value = NULL;
 238         fields[2].in_check_mask = NULL;
 239         fields[2].in_handler = NULL;
 240         fields[2].in_handler_priv = NULL;
 241
 242         fields[3].device = jtag_info->chain_pos;
 243         fields[3].num_bits = 1;
 244         fields[3].out_value = &nr_w_buf;
 245         fields[3].out_mask = NULL;
 246         fields[3].in_value = NULL;
 247         fields[3].in_check_value = NULL;
 248         fields[3].in_check_mask = NULL;
 249         fields[3].in_handler = NULL;
 250         fields[3].in_handler_priv = NULL;
 251
 252         jtag_add_dr_scan(4, fields, -1, NULL);
 253
 254         do
 255         {
 256                 /* rescan with NOP, to wait for the access to complete */
 257                 access = 0;
 258                 nr_w_buf = 0;
 259                 jtag_add_dr_scan(4, fields, -1, NULL);
 260                 jtag_execute_queue();
 261         } while (buf_get_u32(&access, 0, 1) != 1);
 262
 263 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 264         DEBUG("addr: 0x%x value: %8.8x", address, value);
 265 #endif
 266
 267         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 268
 269         return ERROR_OK;
 270 }
 271
 272 int arm926ejs_examine_debug_reason(target_t *target)
 273 {
 274         armv4_5_common_t *armv4_5 = target->arch_info;
 275         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 276         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 277         int debug_reason;
 278         int retval;
 279
 280         embeddedice_read_reg(dbg_stat);
 281         if ((retval = jtag_execute_queue()) != ERROR_OK)
 282                 return retval;
 283
 284         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 285
 286         switch (debug_reason)
 287         {
 288                 case 1:
 289                         DEBUG("breakpoint from EICE unit 0");
 290                         target->debug_reason = DBG_REASON_BREAKPOINT;
 291                         break;
 292                 case 2:
 293                         DEBUG("breakpoint from EICE unit 1");
 294                         target->debug_reason = DBG_REASON_BREAKPOINT;
 295                         break;
 296                 case 3:
 297                         DEBUG("soft breakpoint (BKPT instruction)");
 298                         target->debug_reason = DBG_REASON_BREAKPOINT;
 299                         break;
 300                 case 4:
 301                         DEBUG("vector catch breakpoint");
 302                         target->debug_reason = DBG_REASON_BREAKPOINT;
 303                         break;
 304                 case 5:
 305                         DEBUG("external breakpoint");
 306                         target->debug_reason = DBG_REASON_BREAKPOINT;
 307                         break;
 308                 case 6:
 309                         DEBUG("watchpoint from EICE unit 0");
 310                         target->debug_reason = DBG_REASON_WATCHPOINT;
 311                         break;
 312                 case 7:
 313                         DEBUG("watchpoint from EICE unit 1");
 314                         target->debug_reason = DBG_REASON_WATCHPOINT;
 315                         break;
 316                 case 8:
 317                         DEBUG("external watchpoint");
 318                         target->debug_reason = DBG_REASON_WATCHPOINT;
 319                         break;
 320                 case 9:
 321                         DEBUG("internal debug request");
 322                         target->debug_reason = DBG_REASON_DBGRQ;
 323                         break;
 324                 case 10:
 325                         DEBUG("external debug request");
 326                         target->debug_reason = DBG_REASON_DBGRQ;
 327                         break;
 328                 case 11:
 329                         ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 330                         break;
 331                 default:
 332                         ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 333                         target->debug_reason = DBG_REASON_DBGRQ;
 334         }
 335
 336         return ERROR_OK;
 337 }
 338
 339 u32 arm926ejs_get_ttb(target_t *target)
 340 {
 341         int retval;
 342         u32 ttb = 0x0;
 343
 344         if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb)) != ERROR_OK)
 345                 return retval;
 346
 347         return ttb;
 348 }
 349
 350 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 351 {
 352         u32 cp15_control;
 353
 354         /* read cp15 control register */
 355         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
 356         jtag_execute_queue();
 357
 358         if (mmu)
 359         {
 360                 /* invalidate TLB */
 361                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0);
 362
 363                 cp15_control &= ~0x1U;
 364         }
 365
 366         if (d_u_cache)
 367         {
 368                 u32 debug_override;
 369                 /* read-modify-write CP15 debug override register
 370                  * to enable "test and clean all" */
 371                 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override);
 372                 debug_override |= 0x80000;
 373                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
 374
 375                 /* clean and invalidate DCache */
 376                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
 377
 378                 /* write CP15 debug override register
 379                  * to disable "test and clean all" */
 380                 debug_override &= ~0x80000;
 381                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
 382
 383                 cp15_control &= ~0x4U;
 384         }
 385
 386         if (i_cache)
 387         {
 388                 /* invalidate ICache */
 389                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
 390
 391                 cp15_control &= ~0x1000U;
 392         }
 393
 394         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
 395 }
 396
 397 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 398 {
 399         u32 cp15_control;
 400
 401         /* read cp15 control register */
 402         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
 403         jtag_execute_queue();
 404
 405         if (mmu)
 406                 cp15_control |= 0x1U;
 407
 408         if (d_u_cache)
 409                 cp15_control |= 0x4U;
 410
 411         if (i_cache)
 412                 cp15_control |= 0x1000U;
 413
 414         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
 415 }
 416
 417 void arm926ejs_post_debug_entry(target_t *target)
 418 {
 419         armv4_5_common_t *armv4_5 = target->arch_info;
 420         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 421         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 422         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 423
 424         /* examine cp15 control reg */
 425         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg);
 426         jtag_execute_queue();
 427         DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 428
 429         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 430         {
 431                 u32 cache_type_reg;
 432                 /* identify caches */
 433                 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg);
 434                 jtag_execute_queue();
 435                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 436         }
 437
 438         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 439         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 440         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 441
 442         /* save i/d fault status and address register */
 443         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs->d_fsr);
 444         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs->i_fsr);
 445         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs->d_far);
 446
 447         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 448                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 449
 450
 451         u32 cache_dbg_ctrl;
 452
 453         /* read-modify-write CP15 cache debug control register
 454          * to disable I/D-cache linefills and force WT */
 455         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
 456         cache_dbg_ctrl |= 0x7;
 457         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 458 }
 459
 460 void arm926ejs_pre_restore_context(target_t *target)
 461 {
 462         armv4_5_common_t *armv4_5 = target->arch_info;
 463         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 464         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 465         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 466
 467         /* restore i/d fault status and address register */
 468         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr);
 469         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr);
 470         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs->d_far);
 471
 472         u32 cache_dbg_ctrl;
 473
 474         /* read-modify-write CP15 cache debug control register
 475          * to reenable I/D-cache linefills and disable WT */
 476         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
 477         cache_dbg_ctrl &= ~0x7;
 478         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 479 }
 480
 481 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 482 {
 483         armv4_5_common_t *armv4_5 = target->arch_info;
 484         arm7_9_common_t *arm7_9;
 485         arm9tdmi_common_t *arm9tdmi;
 486         arm926ejs_common_t *arm926ejs;
 487
 488         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 489         {
 490                 return -1;
 491         }
 492
 493         arm7_9 = armv4_5->arch_info;
 494         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 495         {
 496                 return -1;
 497         }
 498
 499         arm9tdmi = arm7_9->arch_info;
 500         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 501         {
 502                 return -1;
 503         }
 504
 505         arm926ejs = arm9tdmi->arch_info;
 506         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 507         {
 508                 return -1;
 509         }
 510
 511         *armv4_5_p = armv4_5;
 512         *arm7_9_p = arm7_9;
 513         *arm9tdmi_p = arm9tdmi;
 514         *arm926ejs_p = arm926ejs;
 515
 516         return ERROR_OK;
 517 }
 518
 519 int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
 520 {
 521         armv4_5_common_t *armv4_5 = target->arch_info;
 522         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 523         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 524         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 525
 526         char *state[] =
 527         {
 528                 "disabled", "enabled"
 529         };
 530
 531         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 532         {
 533                 ERROR("BUG: called for a non-ARMv4/5 target");
 534                 exit(-1);
 535         }
 536
 537         snprintf(buf, buf_size,
 538                         "target halted in %s state due to %s, current mode: %s\n"
 539                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 540                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 541                          armv4_5_state_strings[armv4_5->core_state],
 542                          target_debug_reason_strings[target->debug_reason],
 543                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 544                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 545                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 546                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 547                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 548                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 549
 550         return ERROR_OK;
 551 }
 552
 553 int arm926ejs_soft_reset_halt(struct target_s *target)
 554 {
 555         armv4_5_common_t *armv4_5 = target->arch_info;
 556         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 557         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 558         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 559         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 560
 561         if (target->state == TARGET_RUNNING)
 562         {
 563                 target->type->halt(target);
 564         }
 565
 566         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 567         {
 568                 embeddedice_read_reg(dbg_stat);
 569                 jtag_execute_queue();
 570         }
 571
 572         target->state = TARGET_HALTED;
 573
 574         /* SVC, ARM state, IRQ and FIQ disabled */
 575         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 576         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 577         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 578
 579         /* start fetching from 0x0 */
 580         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 581         armv4_5->core_cache->reg_list[15].dirty = 1;
 582         armv4_5->core_cache->reg_list[15].valid = 1;
 583
 584         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 585         armv4_5->core_state = ARMV4_5_STATE_ARM;
 586
 587         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 588         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 589         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 590         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 591
 592         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 593
 594         return ERROR_OK;
 595 }
 596
 597 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 598 {
 599         int retval;
 600         armv4_5_common_t *armv4_5 = target->arch_info;
 601         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 602         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 603         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 604
 605         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 606                 return retval;
 607
 608         /* If ICache is enabled, we have to invalidate affected ICache lines
 609          * the DCache is forced to write-through, so we don't have to clean it here
 610          */
 611         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 612         {
 613                 if (count <= 1)
 614                 {
 615                         /* invalidate ICache single entry with MVA */
 616                         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address);
 617                 }
 618                 else
 619                 {
 620                         /* invalidate ICache */
 621                         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address);
 622                 }
 623         }
 624
 625         return retval;
 626 }
 627
 628 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 629 {
 630         arm9tdmi_init_target(cmd_ctx, target);
 631
 632         return ERROR_OK;
 633
 634 }
 635
 636 int arm926ejs_quit()
 637 {
 638
 639         return ERROR_OK;
 640 }
 641
 642 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
 643 {
 644         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 645         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 646
 647         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 648          */
 649         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 650
 651         arm9tdmi->arch_info = arm926ejs;
 652         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 653
 654         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 655         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 656
 657         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 658         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 659         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 660         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 661         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 662         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 663         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 664         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 665
 666         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 667
 668         /* The ARM926EJ-S implements the ARMv5TE architecture which
 669          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 670          */
 671         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 672         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 673
 674         arm7_9->sw_bkpts_use_wp = 0;
 675         arm7_9->sw_bkpts_enabled = 1;
 676
 677         return ERROR_OK;
 678 }
 679
 680 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 681 {
 682         int chain_pos;
 683         char *variant = NULL;
 684         arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
 685
 686         if (argc < 4)
 687         {
 688                 ERROR("'target arm926ejs' requires at least one additional argument");
 689                 exit(-1);
 690         }
 691
 692         chain_pos = strtoul(args[3], NULL, 0);
 693
 694         if (argc >= 5)
 695                 variant = args[4];
 696
 697         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 698
 699         arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
 700
 701         return ERROR_OK;
 702 }
 703
 704 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 705 {
 706         int retval;
 707         command_t *arm926ejs_cmd;
 708
 709
 710         retval = arm9tdmi_register_commands(cmd_ctx);
 711
 712         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 713
 714         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 715
 716         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 717         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 718
 719         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 720         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 721         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 722
 723         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 724         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 725         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 726
 727         return ERROR_OK;
 728 }
 729
 730 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 731 {
 732         int retval;
 733         target_t *target = get_current_target(cmd_ctx);
 734         armv4_5_common_t *armv4_5;
 735         arm7_9_common_t *arm7_9;
 736         arm9tdmi_common_t *arm9tdmi;
 737         arm926ejs_common_t *arm926ejs;
 738         int opcode_1;
 739         int opcode_2;
 740         int CRn;
 741         int CRm;
 742
 743         if ((argc < 4) || (argc > 5))
 744         {
 745                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 746                 return ERROR_OK;
 747         }
 748
 749         opcode_1 = strtoul(args[0], NULL, 0);
 750         opcode_2 = strtoul(args[1], NULL, 0);
 751         CRn = strtoul(args[2], NULL, 0);
 752         CRm = strtoul(args[3], NULL, 0);
 753
 754         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 755         {
 756                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 757                 return ERROR_OK;
 758         }
 759
 760         if (target->state != TARGET_HALTED)
 761         {
 762                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 763                 return ERROR_OK;
 764         }
 765
 766         if (argc == 4)
 767         {
 768                 u32 value;
 769                 if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), &value)) != ERROR_OK)
 770                 {
 771                         command_print(cmd_ctx, "couldn't access register");
 772                         return ERROR_OK;
 773                 }
 774                 jtag_execute_queue();
 775
 776                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 777         }
 778         else
 779         {
 780                 u32 value = strtoul(args[4], NULL, 0);
 781                 if ((retval = arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), value)) != ERROR_OK)
 782                 {
 783                         command_print(cmd_ctx, "couldn't access register");
 784                         return ERROR_OK;
 785                 }
 786                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 787         }
 788
 789         return ERROR_OK;
 790 }
 791
 792 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 793 {
 794         target_t *target = get_current_target(cmd_ctx);
 795         armv4_5_common_t *armv4_5;
 796         arm7_9_common_t *arm7_9;
 797         arm9tdmi_common_t *arm9tdmi;
 798         arm926ejs_common_t *arm926ejs;
 799
 800         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 801         {
 802                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 803                 return ERROR_OK;
 804         }
 805
 806         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 807 }
 808
 809 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 810 {
 811         target_t *target = get_current_target(cmd_ctx);
 812         armv4_5_common_t *armv4_5;
 813         arm7_9_common_t *arm7_9;
 814         arm9tdmi_common_t *arm9tdmi;
 815         arm926ejs_common_t *arm926ejs;
 816         arm_jtag_t *jtag_info;
 817
 818         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 819         {
 820                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 821                 return ERROR_OK;
 822         }
 823
 824         jtag_info = &arm7_9->jtag_info;
 825
 826         if (target->state != TARGET_HALTED)
 827         {
 828                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 829                 return ERROR_OK;
 830         }
 831
 832         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 833 }
 834
 835 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 836 {
 837         target_t *target = get_current_target(cmd_ctx);
 838         armv4_5_common_t *armv4_5;
 839         arm7_9_common_t *arm7_9;
 840         arm9tdmi_common_t *arm9tdmi;
 841         arm926ejs_common_t *arm926ejs;
 842         arm_jtag_t *jtag_info;
 843
 844         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 845         {
 846                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 847                 return ERROR_OK;
 848         }
 849
 850         jtag_info = &arm7_9->jtag_info;
 851
 852         if (target->state != TARGET_HALTED)
 853         {
 854                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 855                 return ERROR_OK;
 856         }
 857
 858         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 859 }
 860
 861 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 862 {
 863         target_t *target = get_current_target(cmd_ctx);
 864         armv4_5_common_t *armv4_5;
 865         arm7_9_common_t *arm7_9;
 866         arm9tdmi_common_t *arm9tdmi;
 867         arm926ejs_common_t *arm926ejs;
 868         arm_jtag_t *jtag_info;
 869
 870         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 871         {
 872                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 873                 return ERROR_OK;
 874         }
 875
 876         jtag_info = &arm7_9->jtag_info;
 877
 878         if (target->state != TARGET_HALTED)
 879         {
 880                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 881                 return ERROR_OK;
 882         }
 883
 884         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 885 }