1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2010 by Drasko DRASKOVIC *
9 * drasko.draskovic@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include "target_type.h"
33 #include "arm_opcodes.h"
35 #include "breakpoints.h"
38 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #define NB_CACHE_WAYS 4
44 #define CP15_CTL_DCACHE (1<<2)
45 #define CP15_CTL_ICACHE (1<<12)
48 * flag to give info about cache manipulation during debug :
49 * "0" - cache lines are invalidated "on the fly", for affected addresses.
50 * This is prefered from performance point of view.
51 * "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
52 * It is kept off during debugging.
54 static uint8_t arm946e_preserve_cache
;
56 int arm946e_post_debug_entry(struct target
*target
);
57 void arm946e_pre_restore_context(struct target
*target
);
58 static int arm946e_read_cp15(struct target
*target
, int reg_addr
, uint32_t *value
);
60 int arm946e_init_arch_info(struct target
*target
,
61 struct arm946e_common
*arm946e
,
64 struct arm7_9_common
*arm7_9
= &arm946e
->arm7_9_common
;
66 /* initialize arm7/arm9 specific info (including armv4_5) */
67 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
69 arm946e
->common_magic
= ARM946E_COMMON_MAGIC
;
72 * The ARM946E-S implements the ARMv5TE architecture which
73 * has the BKPT instruction, so we don't have to use a watchpoint comparator
75 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
76 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
79 arm7_9
->post_debug_entry
= arm946e_post_debug_entry
;
80 arm7_9
->pre_restore_context
= arm946e_pre_restore_context
;
83 * disabling linefills leads to lockups, so keep them enabled for now
84 * this doesn't affect correctness, but might affect timing issues, if
85 * important data is evicted from the cache during the debug session
87 arm946e_preserve_cache
= 0;
89 /* override hw single-step capability from ARM9TDMI */
90 /* arm7_9->has_single_step = 1; */
95 static int arm946e_target_create(struct target
*target
, Jim_Interp
*interp
)
97 struct arm946e_common
*arm946e
= calloc(1, sizeof(struct arm946e_common
));
99 arm946e_init_arch_info(target
, arm946e
, target
->tap
);
104 static int arm946e_verify_pointer(struct command_context
*cmd_ctx
,
105 struct arm946e_common
*arm946e
)
107 if (arm946e
->common_magic
!= ARM946E_COMMON_MAGIC
) {
108 command_print(cmd_ctx
, "target is not an ARM946");
109 return ERROR_TARGET_INVALID
;
115 * REVISIT: The "read_cp15" and "write_cp15" commands could hook up
116 * to eventual mrc() and mcr() routines ... the reg_addr values being
117 * constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
118 * See section 7.3 of the ARM946E-S TRM.
120 static int arm946e_read_cp15(struct target
*target
, int reg_addr
, uint32_t *value
)
122 int retval
= ERROR_OK
;
123 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
124 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
125 struct scan_field fields
[3];
126 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
127 uint8_t nr_w_buf
= 0;
129 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
130 if (retval
!= ERROR_OK
)
132 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
133 if (retval
!= ERROR_OK
)
136 fields
[0].num_bits
= 32;
137 /* REVISIT: table 7-2 shows that bits 31-31 need to be
138 * specified for accessing BIST registers ...
140 fields
[0].out_value
= NULL
;
141 fields
[0].in_value
= NULL
;
143 fields
[1].num_bits
= 6;
144 fields
[1].out_value
= ®_addr_buf
;
145 fields
[1].in_value
= NULL
;
147 fields
[2].num_bits
= 1;
148 fields
[2].out_value
= &nr_w_buf
;
149 fields
[2].in_value
= NULL
;
151 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
153 fields
[0].in_value
= (uint8_t *)value
;
154 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
156 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
162 retval
= jtag_execute_queue();
163 if (retval
!= ERROR_OK
)
169 int arm946e_write_cp15(struct target
*target
, int reg_addr
, uint32_t value
)
171 int retval
= ERROR_OK
;
172 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
173 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
174 struct scan_field fields
[3];
175 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
176 uint8_t nr_w_buf
= 1;
177 uint8_t value_buf
[4];
179 buf_set_u32(value_buf
, 0, 32, value
);
181 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
182 if (retval
!= ERROR_OK
)
184 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
185 if (retval
!= ERROR_OK
)
188 fields
[0].num_bits
= 32;
189 fields
[0].out_value
= value_buf
;
190 fields
[0].in_value
= NULL
;
192 fields
[1].num_bits
= 6;
193 fields
[1].out_value
= ®_addr_buf
;
194 fields
[1].in_value
= NULL
;
196 fields
[2].num_bits
= 1;
197 fields
[2].out_value
= &nr_w_buf
;
198 fields
[2].in_value
= NULL
;
200 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
202 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
203 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
206 retval
= jtag_execute_queue();
207 if (retval
!= ERROR_OK
)
213 uint32_t arm946e_invalidate_whole_dcache(struct target
*target
)
218 uint32_t cp15_idx
, seg
, dtag
;
223 arm946e_read_cp15(target
, 0x01, (uint32_t *) &csize
);
225 csize
= (csize
>> 18) & 0x0F;
230 shift
= csize
- 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
232 /* Cache size, given in bytes */
233 csize
= 1 << (12 + shift
);
234 /* One line (index) is 32 bytes (8 words) long */
235 nb_idx
= (csize
/ 32); /* gives nb of lines (indexes) in the cache */
237 /* Loop for all segmentde (i.e. ways) */
238 for (seg
= 0; seg
< NB_CACHE_WAYS
; seg
++) {
239 /* Loop for all indexes */
240 for (idx
= 0; idx
< nb_idx
; idx
++) {
241 /* Form and write cp15 index (segment + line idx) */
242 cp15_idx
= seg
<< 30 | idx
<< 5;
243 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
244 if (retval
!= ERROR_OK
) {
245 LOG_DEBUG("ERROR writing index");
250 arm946e_read_cp15(target
, 0x16, (uint32_t *) &dtag
);
252 /* Check cache line VALID bit */
253 if (!(dtag
>> 4 & 0x1))
256 /* Clean data cache line */
257 retval
= arm946e_write_cp15(target
, 0x35, 0x1);
258 if (retval
!= ERROR_OK
) {
259 LOG_DEBUG("ERROR cleaning cache line");
263 /* Flush data cache line */
264 retval
= arm946e_write_cp15(target
, 0x1a, 0x1);
265 if (retval
!= ERROR_OK
) {
266 LOG_DEBUG("ERROR flushing cache line");
275 uint32_t arm946e_invalidate_whole_icache(struct target
*target
)
279 LOG_DEBUG("FLUSHING I$");
282 * Invalidate (flush) I$
283 * mcr 15, 0, r0, cr7, cr5, {0}
285 retval
= arm946e_write_cp15(target
, 0x0f, 0x1);
286 if (retval
!= ERROR_OK
) {
287 LOG_DEBUG("ERROR flushing I$");
294 int arm946e_post_debug_entry(struct target
*target
)
296 uint32_t ctr_reg
= 0x0;
297 uint32_t retval
= ERROR_OK
;
298 struct arm946e_common
*arm946e
= target_to_arm946(target
);
300 /* See if CACHES are enabled, and save that info
301 * in the context bits, so that arm946e_pre_restore_context() can use them */
302 arm946e_read_cp15(target
, CP15_CTL
, (uint32_t *) &ctr_reg
);
304 /* Save control reg in the context */
305 arm946e
->cp15_control_reg
= ctr_reg
;
307 if (arm946e_preserve_cache
) {
308 if (ctr_reg
& CP15_CTL_DCACHE
) {
309 /* Clean and flush D$ */
310 arm946e_invalidate_whole_dcache(target
);
313 ctr_reg
&= ~CP15_CTL_DCACHE
;
316 if (ctr_reg
& CP15_CTL_ICACHE
) {
318 arm946e_invalidate_whole_icache(target
);
321 ctr_reg
&= ~CP15_CTL_ICACHE
;
324 /* Write the new configuration */
325 retval
= arm946e_write_cp15(target
, CP15_CTL
, ctr_reg
);
326 if (retval
!= ERROR_OK
) {
327 LOG_DEBUG("ERROR disabling cache");
330 } /* if preserve_cache */
335 void arm946e_pre_restore_context(struct target
*target
)
337 uint32_t ctr_reg
= 0x0;
340 if (arm946e_preserve_cache
) {
341 struct arm946e_common
*arm946e
= target_to_arm946(target
);
342 /* Get the contents of the CTR reg */
343 arm946e_read_cp15(target
, CP15_CTL
, (uint32_t *) &ctr_reg
);
346 * Read-modify-write CP15 control
347 * to reenable I/D-cache operation
348 * NOTE: It is not possible to disable cache by CP15.
349 * if arm946e_preserve_cache debugging flag enabled.
351 ctr_reg
|= arm946e
->cp15_control_reg
& (CP15_CTL_DCACHE
|CP15_CTL_ICACHE
);
353 /* Write the new configuration */
354 retval
= arm946e_write_cp15(target
, CP15_CTL
, ctr_reg
);
355 if (retval
!= ERROR_OK
)
356 LOG_DEBUG("ERROR enabling cache");
357 } /* if preserve_cache */
360 uint32_t arm946e_invalidate_dcache(struct target
*target
, uint32_t address
,
361 uint32_t size
, uint32_t count
)
363 uint32_t csize
= 0x0;
365 uint32_t cur_addr
= 0x0;
366 uint32_t cp15_idx
, set
, way
, dtag
;
370 for (i
= 0; i
< count
*size
; i
++) {
371 cur_addr
= address
+ i
;
374 arm946e_read_cp15(target
, 0x01, (uint32_t *) &csize
);
376 /* Conclude cache size to find number of lines */
377 csize
= (csize
>> 18) & 0x0F;
382 shift
= csize
- 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
384 csize
= 1 << (12 + shift
);
386 set
= (cur_addr
>> 5) & 0xff; /* set field is 8 bits long */
388 for (way
= 0; way
< NB_CACHE_WAYS
; way
++) {
390 * Find if the affected address is kept in the cache.
391 * Because JTAG Scan Chain 15 offers limited approach,
392 * we have to loop through all cache ways (segments) and
393 * read cache tags, then compare them with with address.
396 /* Form and write cp15 index (segment + line idx) */
397 cp15_idx
= way
<< 30 | set
<< 5;
398 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
399 if (retval
!= ERROR_OK
) {
400 LOG_DEBUG("ERROR writing index");
405 arm946e_read_cp15(target
, 0x16, (uint32_t *) &dtag
);
407 /* Check cache line VALID bit */
408 if (!(dtag
>> 4 & 0x1))
411 /* If line is valid and corresponds to affected address - invalidate it */
412 if (dtag
>> 5 == cur_addr
>> 5) {
413 /* Clean data cache line */
414 retval
= arm946e_write_cp15(target
, 0x35, 0x1);
415 if (retval
!= ERROR_OK
) {
416 LOG_DEBUG("ERROR cleaning cache line");
420 /* Flush data cache line */
421 retval
= arm946e_write_cp15(target
, 0x1c, 0x1);
422 if (retval
!= ERROR_OK
) {
423 LOG_DEBUG("ERROR flushing cache line");
429 } /* loop through all 4 ways */
430 } /* loop through all addresses */
435 uint32_t arm946e_invalidate_icache(struct target
*target
, uint32_t address
,
436 uint32_t size
, uint32_t count
)
438 uint32_t cur_addr
= 0x0;
439 uint32_t cp15_idx
, set
, way
, itag
;
443 for (i
= 0; i
< count
*size
; i
++) {
444 cur_addr
= address
+ i
;
446 set
= (cur_addr
>> 5) & 0xff; /* set field is 8 bits long */
448 for (way
= 0; way
< NB_CACHE_WAYS
; way
++) {
449 /* Form and write cp15 index (segment + line idx) */
450 cp15_idx
= way
<< 30 | set
<< 5;
451 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
452 if (retval
!= ERROR_OK
) {
453 LOG_DEBUG("ERROR writing index");
458 arm946e_read_cp15(target
, 0x17, (uint32_t *) &itag
);
460 /* Check cache line VALID bit */
461 if (!(itag
>> 4 & 0x1))
464 /* If line is valid and corresponds to affected address - invalidate it */
465 if (itag
>> 5 == cur_addr
>> 5) {
467 retval
= arm946e_write_cp15(target
, 0x1d, 0x0);
468 if (retval
!= ERROR_OK
) {
469 LOG_DEBUG("ERROR flushing cache line");
481 /** Writes a buffer, in the specified word size, with current MMU settings. */
482 int arm946e_write_memory(struct target
*target
, uint32_t address
,
483 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
489 struct arm946e_common
*arm946e
= target_to_arm946(target
);
490 /* Invalidate D$ if it is ON */
491 if (!arm946e_preserve_cache
&& (arm946e
->cp15_control_reg
& CP15_CTL_DCACHE
))
492 arm946e_invalidate_dcache(target
, address
, size
, count
);
497 retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
);
498 if (retval
!= ERROR_OK
)
502 * Invalidate I$ if it is ON.
504 * D$ has been cleaned and flushed before mem write thus forcing it to behave like write-through,
505 * because arm7_9_write_memory() has seen non-valid bit in D$
506 * and wrote data into physical RAM (without touching or allocating the cache line).
507 * From ARM946ES Technical Reference Manual we can see that it uses "allocate on read-miss"
508 * policy for both I$ and D$ (Chapter 3.2 and 3.3)
511 * "ARM system developer's guide: designing and optimizing system software" by
512 * Andrew N. Sloss, Dominic Symes and Chris Wright,
513 * Chapter 12.3.3 Allocating Policy on a Cache Miss :
514 * A read allocate on cache miss policy allocates a cache line only during a read from main memory.
515 * If the victim cache line contains valid data, then it is written to main memory before the cache line
516 * is filled with new data.
517 * Under this strategy, a write of new data to memory does not update the contents of the cache memory
518 * unless a cache line was allocated on a previous read from main memory.
519 * If the cache line contains valid data, then the write updates the cache and may update the main memory if
520 * the cache write policy is write-through.
521 * If the data is not in the cache, the controller writes to main memory only.
523 if (!arm946e_preserve_cache
&& (arm946e
->cp15_control_reg
& CP15_CTL_ICACHE
))
524 arm946e_invalidate_icache(target
, address
, size
, count
);
530 int arm946e_read_memory(struct target
*target
, uint32_t address
,
531 uint32_t size
, uint32_t count
, uint8_t *buffer
)
537 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
538 if (retval
!= ERROR_OK
)
545 COMMAND_HANDLER(arm946e_handle_cp15_command
)
548 struct target
*target
= get_current_target(CMD_CTX
);
549 struct arm946e_common
*arm946e
= target_to_arm946(target
);
551 retval
= arm946e_verify_pointer(CMD_CTX
, arm946e
);
552 if (retval
!= ERROR_OK
)
555 if (target
->state
!= TARGET_HALTED
) {
556 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
560 /* one or more argument, access a single register (write if second argument is given */
563 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
567 retval
= arm946e_read_cp15(target
, address
, &value
);
568 if (retval
!= ERROR_OK
) {
569 command_print(CMD_CTX
, "couldn't access reg %" PRIi32
, address
);
572 retval
= jtag_execute_queue();
573 if (retval
!= ERROR_OK
)
576 command_print(CMD_CTX
, "%" PRIi32
": %8.8" PRIx32
, address
, value
);
577 } else if (CMD_ARGC
== 2) {
579 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
580 retval
= arm946e_write_cp15(target
, address
, value
);
581 if (retval
!= ERROR_OK
) {
582 command_print(CMD_CTX
, "couldn't access reg %" PRIi32
, address
);
585 command_print(CMD_CTX
, "%" PRIi32
": %8.8" PRIx32
, address
, value
);
592 static const struct command_registration arm946e_exec_command_handlers
[] = {
595 .handler
= arm946e_handle_cp15_command
,
596 .mode
= COMMAND_EXEC
,
597 .usage
= "regnum [value]",
598 .help
= "display/modify cp15 register",
600 COMMAND_REGISTRATION_DONE
603 const struct command_registration arm946e_command_handlers
[] = {
605 .chain
= arm9tdmi_command_handlers
,
610 .help
= "arm946e command group",
612 .chain
= arm946e_exec_command_handlers
,
614 COMMAND_REGISTRATION_DONE
617 /** Holds methods for ARM946 targets. */
618 struct target_type arm946e_target
= {
622 .arch_state
= arm_arch_state
,
624 .target_request_data
= arm7_9_target_request_data
,
627 .resume
= arm7_9_resume
,
630 .assert_reset
= arm7_9_assert_reset
,
631 .deassert_reset
= arm7_9_deassert_reset
,
632 .soft_reset_halt
= arm7_9_soft_reset_halt
,
634 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
636 /* .read_memory = arm7_9_read_memory, */
637 /* .write_memory = arm7_9_write_memory, */
638 .read_memory
= arm946e_read_memory
,
639 .write_memory
= arm946e_write_memory
,
641 .bulk_write_memory
= arm7_9_bulk_write_memory
,
643 .checksum_memory
= arm_checksum_memory
,
644 .blank_check_memory
= arm_blank_check_memory
,
646 .run_algorithm
= armv4_5_run_algorithm
,
648 .add_breakpoint
= arm7_9_add_breakpoint
,
649 .remove_breakpoint
= arm7_9_remove_breakpoint
,
650 /* .add_breakpoint = arm946e_add_breakpoint, */
651 /* .remove_breakpoint = arm946e_remove_breakpoint, */
653 .add_watchpoint
= arm7_9_add_watchpoint
,
654 .remove_watchpoint
= arm7_9_remove_watchpoint
,
656 .commands
= arm946e_command_handlers
,
657 .target_create
= arm946e_target_create
,
658 .init_target
= arm9tdmi_init_target
,
659 .examine
= arm7_9_examine
,
660 .check_reset
= arm7_9_check_reset
,
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