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- add support for cortex_m3 target_request debugmsgs
[openocd.git] / src / target / arm9tdmi.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm9tdmi.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "etm.h"
32 #include "etb.h"
33 #include "log.h"
34 #include "jtag.h"
35 #include "arm_jtag.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 #if 0
41 #define _DEBUG_INSTRUCTION_EXECUTION_
42 #endif
43
44 /* cli handling */
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm9tdmi_quit();
52
53 target_type_t arm9tdmi_target =
54 {
55 .name = "arm9tdmi",
56
57 .poll = arm7_9_poll,
58 .arch_state = armv4_5_arch_state,
59
60 .target_request_data = arm7_9_target_request_data,
61
62 .halt = arm7_9_halt,
63 .resume = arm7_9_resume,
64 .step = arm7_9_step,
65
66 .assert_reset = arm7_9_assert_reset,
67 .deassert_reset = arm7_9_deassert_reset,
68 .soft_reset_halt = arm7_9_soft_reset_halt,
69 .prepare_reset_halt = arm7_9_prepare_reset_halt,
70
71 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
72
73 .read_memory = arm7_9_read_memory,
74 .write_memory = arm7_9_write_memory,
75 .bulk_write_memory = arm7_9_bulk_write_memory,
76 .checksum_memory = arm7_9_checksum_memory,
77
78 .run_algorithm = armv4_5_run_algorithm,
79
80 .add_breakpoint = arm7_9_add_breakpoint,
81 .remove_breakpoint = arm7_9_remove_breakpoint,
82 .add_watchpoint = arm7_9_add_watchpoint,
83 .remove_watchpoint = arm7_9_remove_watchpoint,
84
85 .register_commands = arm9tdmi_register_commands,
86 .target_command = arm9tdmi_target_command,
87 .init_target = arm9tdmi_init_target,
88 .quit = arm9tdmi_quit
89 };
90
91 arm9tdmi_vector_t arm9tdmi_vectors[] =
92 {
93 {"reset", ARM9TDMI_RESET_VECTOR},
94 {"undef", ARM9TDMI_UNDEF_VECTOR},
95 {"swi", ARM9TDMI_SWI_VECTOR},
96 {"pabt", ARM9TDMI_PABT_VECTOR},
97 {"dabt", ARM9TDMI_DABT_VECTOR},
98 {"reserved", ARM9TDMI_RESERVED_VECTOR},
99 {"irq", ARM9TDMI_IRQ_VECTOR},
100 {"fiq", ARM9TDMI_FIQ_VECTOR},
101 {0, 0},
102 };
103
104 int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
105 {
106 char *caller = priv;
107
108 DEBUG("caller: %s", caller);
109
110 return ERROR_JTAG_QUEUE_FAILED;
111 }
112
113 int arm9tdmi_examine_debug_reason(target_t *target)
114 {
115 /* get pointers to arch-specific information */
116 armv4_5_common_t *armv4_5 = target->arch_info;
117 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
118
119 /* only check the debug reason if we don't know it already */
120 if ((target->debug_reason != DBG_REASON_DBGRQ)
121 && (target->debug_reason != DBG_REASON_SINGLESTEP))
122 {
123 scan_field_t fields[3];
124 u8 databus[4];
125 u8 instructionbus[4];
126 u8 debug_reason;
127
128 jtag_add_end_state(TAP_PD);
129
130 fields[0].device = arm7_9->jtag_info.chain_pos;
131 fields[0].num_bits = 32;
132 fields[0].out_value = NULL;
133 fields[0].out_mask = NULL;
134 fields[0].in_value = databus;
135 fields[0].in_check_value = NULL;
136 fields[0].in_check_mask = NULL;
137 fields[0].in_handler = NULL;
138 fields[0].in_handler_priv = NULL;
139
140 fields[1].device = arm7_9->jtag_info.chain_pos;
141 fields[1].num_bits = 3;
142 fields[1].out_value = NULL;
143 fields[1].out_mask = NULL;
144 fields[1].in_value = &debug_reason;
145 fields[1].in_check_value = NULL;
146 fields[1].in_check_mask = NULL;
147 fields[1].in_handler = NULL;
148 fields[1].in_handler_priv = NULL;
149
150 fields[2].device = arm7_9->jtag_info.chain_pos;
151 fields[2].num_bits = 32;
152 fields[2].out_value = NULL;
153 fields[2].out_mask = NULL;
154 fields[2].in_value = instructionbus;
155 fields[2].in_check_value = NULL;
156 fields[2].in_check_mask = NULL;
157 fields[2].in_handler = NULL;
158 fields[2].in_handler_priv = NULL;
159
160 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
161 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
162
163 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
164 jtag_execute_queue();
165
166 fields[0].in_value = NULL;
167 fields[0].out_value = databus;
168 fields[1].in_value = NULL;
169 fields[1].out_value = &debug_reason;
170 fields[2].in_value = NULL;
171 fields[2].out_value = instructionbus;
172
173 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
174
175 if (debug_reason & 0x4)
176 if (debug_reason & 0x2)
177 target->debug_reason = DBG_REASON_WPTANDBKPT;
178 else
179 target->debug_reason = DBG_REASON_WATCHPOINT;
180 else
181 target->debug_reason = DBG_REASON_BREAKPOINT;
182 }
183
184 return ERROR_OK;
185 }
186
187 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
188 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
189 {
190 scan_field_t fields[3];
191 u8 out_buf[4];
192 u8 instr_buf[4];
193 u8 sysspeed_buf = 0x0;
194
195 /* prepare buffer */
196 buf_set_u32(out_buf, 0, 32, out);
197
198 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
199
200 if (sysspeed)
201 buf_set_u32(&sysspeed_buf, 2, 1, 1);
202
203 jtag_add_end_state(TAP_PD);
204 arm_jtag_scann(jtag_info, 0x1);
205
206 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
207
208 fields[0].device = jtag_info->chain_pos;
209 fields[0].num_bits = 32;
210 fields[0].out_value = out_buf;
211 fields[0].out_mask = NULL;
212 fields[0].in_value = NULL;
213 if (in)
214 {
215 fields[0].in_handler = arm_jtag_buf_to_u32;
216 fields[0].in_handler_priv = in;
217 }
218 else
219 {
220 fields[0].in_handler = NULL;
221 fields[0].in_handler_priv = NULL;
222 }
223 fields[0].in_check_value = NULL;
224 fields[0].in_check_mask = NULL;
225
226 fields[1].device = jtag_info->chain_pos;
227 fields[1].num_bits = 3;
228 fields[1].out_value = &sysspeed_buf;
229 fields[1].out_mask = NULL;
230 fields[1].in_value = NULL;
231 fields[1].in_check_value = NULL;
232 fields[1].in_check_mask = NULL;
233 fields[1].in_handler = NULL;
234 fields[1].in_handler_priv = NULL;
235
236 fields[2].device = jtag_info->chain_pos;
237 fields[2].num_bits = 32;
238 fields[2].out_value = instr_buf;
239 fields[2].out_mask = NULL;
240 fields[2].in_value = NULL;
241 fields[2].in_check_value = NULL;
242 fields[2].in_check_mask = NULL;
243 fields[2].in_handler = NULL;
244 fields[2].in_handler_priv = NULL;
245
246 jtag_add_dr_scan(3, fields, -1, NULL);
247
248 jtag_add_runtest(0, -1);
249
250 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
251 {
252 jtag_execute_queue();
253
254 if (in)
255 {
256 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
257 }
258 else
259 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
260 }
261 #endif
262
263 return ERROR_OK;
264 }
265
266 /* just read data (instruction and data-out = don't care) */
267 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
268 {
269 scan_field_t fields[3];
270
271 jtag_add_end_state(TAP_PD);
272 arm_jtag_scann(jtag_info, 0x1);
273
274 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
275
276 fields[0].device = jtag_info->chain_pos;
277 fields[0].num_bits = 32;
278 fields[0].out_value = NULL;
279 fields[0].out_mask = NULL;
280 fields[0].in_value = NULL;
281 fields[0].in_handler = arm_jtag_buf_to_u32;
282 fields[0].in_handler_priv = in;
283 fields[0].in_check_value = NULL;
284 fields[0].in_check_mask = NULL;
285
286 fields[1].device = jtag_info->chain_pos;
287 fields[1].num_bits = 3;
288 fields[1].out_value = NULL;
289 fields[1].out_mask = NULL;
290 fields[1].in_value = NULL;
291 fields[1].in_handler = NULL;
292 fields[1].in_handler_priv = NULL;
293 fields[1].in_check_value = NULL;
294 fields[1].in_check_mask = NULL;
295
296 fields[2].device = jtag_info->chain_pos;
297 fields[2].num_bits = 32;
298 fields[2].out_value = NULL;
299 fields[2].out_mask = NULL;
300 fields[2].in_value = NULL;
301 fields[2].in_check_value = NULL;
302 fields[2].in_check_mask = NULL;
303 fields[2].in_handler = NULL;
304 fields[2].in_handler_priv = NULL;
305
306 jtag_add_dr_scan(3, fields, -1, NULL);
307
308 jtag_add_runtest(0, -1);
309
310 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
311 {
312 jtag_execute_queue();
313
314 if (in)
315 {
316 DEBUG("in: 0x%8.8x", *in);
317 }
318 else
319 {
320 ERROR("BUG: called with in == NULL");
321 }
322 }
323 #endif
324
325 return ERROR_OK;
326 }
327
328 /* clock the target, and read the databus
329 * the *in pointer points to a buffer where elements of 'size' bytes
330 * are stored in big (be==1) or little (be==0) endianness
331 */
332 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
333 {
334 scan_field_t fields[3];
335
336 jtag_add_end_state(TAP_PD);
337 arm_jtag_scann(jtag_info, 0x1);
338
339 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
340
341 fields[0].device = jtag_info->chain_pos;
342 fields[0].num_bits = 32;
343 fields[0].out_value = NULL;
344 fields[0].out_mask = NULL;
345 fields[0].in_value = NULL;
346 switch (size)
347 {
348 case 4:
349 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
350 break;
351 case 2:
352 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
353 break;
354 case 1:
355 fields[0].in_handler = arm_jtag_buf_to_8;
356 break;
357 }
358 fields[0].in_handler_priv = in;
359 fields[0].in_check_value = NULL;
360 fields[0].in_check_mask = NULL;
361
362 fields[1].device = jtag_info->chain_pos;
363 fields[1].num_bits = 3;
364 fields[1].out_value = NULL;
365 fields[1].out_mask = NULL;
366 fields[1].in_value = NULL;
367 fields[1].in_handler = NULL;
368 fields[1].in_handler_priv = NULL;
369 fields[1].in_check_value = NULL;
370 fields[1].in_check_mask = NULL;
371
372 fields[2].device = jtag_info->chain_pos;
373 fields[2].num_bits = 32;
374 fields[2].out_value = NULL;
375 fields[2].out_mask = NULL;
376 fields[2].in_value = NULL;
377 fields[2].in_check_value = NULL;
378 fields[2].in_check_mask = NULL;
379 fields[2].in_handler = NULL;
380 fields[2].in_handler_priv = NULL;
381
382 jtag_add_dr_scan(3, fields, -1, NULL);
383
384 jtag_add_runtest(0, -1);
385
386 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
387 {
388 jtag_execute_queue();
389
390 if (in)
391 {
392 DEBUG("in: 0x%8.8x", *in);
393 }
394 else
395 {
396 ERROR("BUG: called with in == NULL");
397 }
398 }
399 #endif
400
401 return ERROR_OK;
402 }
403
404 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
405 {
406 /* get pointers to arch-specific information */
407 armv4_5_common_t *armv4_5 = target->arch_info;
408 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
409 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
410
411 /* save r0 before using it and put system in ARM state
412 * to allow common handling of ARM and THUMB debugging */
413
414 /* fetch STR r0, [r0] */
415 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
417 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
418 /* STR r0, [r0] in Memory */
419 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
420
421 /* MOV r0, r15 fetched, STR in Decode */
422 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
423 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
424 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
425 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
426 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
427 /* nothing fetched, STR r0, [r0] in Memory */
428 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
429
430 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
431 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
432 /* LDR in Decode */
433 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
434 /* LDR in Execute */
435 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
436 /* LDR in Memory (to account for interlock) */
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
438
439 /* fetch BX */
440 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
441 /* NOP fetched, BX in Decode, MOV in Execute */
442 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
443 /* NOP fetched, BX in Execute (1) */
444 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
445
446 jtag_execute_queue();
447
448 /* fix program counter:
449 * MOV r0, r15 was the 5th instruction (+8)
450 * reading PC in Thumb state gives address of instruction + 4
451 */
452 *pc -= 0xc;
453 }
454
455 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
456 {
457 int i;
458 /* get pointers to arch-specific information */
459 armv4_5_common_t *armv4_5 = target->arch_info;
460 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
461 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
462
463 /* STMIA r0-15, [r0] at debug speed
464 * register values will start to appear on 4th DCLK
465 */
466 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
467
468 /* fetch NOP, STM in DECODE stage */
469 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
470 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
471 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
472
473 for (i = 0; i <= 15; i++)
474 {
475 if (mask & (1 << i))
476 /* nothing fetched, STM in MEMORY (i'th cycle) */
477 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
478 }
479
480 }
481
482 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
483 {
484 int i;
485 /* get pointers to arch-specific information */
486 armv4_5_common_t *armv4_5 = target->arch_info;
487 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
488 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
489 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
490 u32 *buf_u32 = buffer;
491 u16 *buf_u16 = buffer;
492 u8 *buf_u8 = buffer;
493
494 /* STMIA r0-15, [r0] at debug speed
495 * register values will start to appear on 4th DCLK
496 */
497 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
498
499 /* fetch NOP, STM in DECODE stage */
500 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
501 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
503
504 for (i = 0; i <= 15; i++)
505 {
506 if (mask & (1 << i))
507 /* nothing fetched, STM in MEMORY (i'th cycle) */
508 switch (size)
509 {
510 case 4:
511 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
512 break;
513 case 2:
514 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
515 break;
516 case 1:
517 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
518 break;
519 }
520 }
521
522 }
523
524 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
525 {
526 /* get pointers to arch-specific information */
527 armv4_5_common_t *armv4_5 = target->arch_info;
528 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
529 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
530
531 /* MRS r0, cpsr */
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
537
538 /* STR r0, [r15] */
539 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
540 /* fetch NOP, STR in DECODE stage */
541 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
542 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
543 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
544 /* nothing fetched, STR in MEMORY */
545 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
546
547 }
548
549 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
550 {
551 /* get pointers to arch-specific information */
552 armv4_5_common_t *armv4_5 = target->arch_info;
553 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
554 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
555
556 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
557
558 /* MSR1 fetched */
559 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
560 /* MSR2 fetched, MSR1 in DECODE */
561 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
562 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
563 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
564 /* nothing fetched, MSR1 in EXECUTE (2) */
565 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
566 /* nothing fetched, MSR1 in EXECUTE (3) */
567 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
568 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
569 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
570 /* nothing fetched, MSR2 in EXECUTE (2) */
571 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
572 /* nothing fetched, MSR2 in EXECUTE (3) */
573 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
574 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
575 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
576 /* nothing fetched, MSR3 in EXECUTE (2) */
577 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
578 /* nothing fetched, MSR3 in EXECUTE (3) */
579 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
580 /* NOP fetched, MSR4 in EXECUTE (1) */
581 /* last MSR writes flags, which takes only one cycle */
582 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
583 }
584
585 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
586 {
587 /* get pointers to arch-specific information */
588 armv4_5_common_t *armv4_5 = target->arch_info;
589 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
590 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
591
592 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
593
594 /* MSR fetched */
595 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
596 /* NOP fetched, MSR in DECODE */
597 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
598 /* NOP fetched, MSR in EXECUTE (1) */
599 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
600
601 /* rot == 4 writes flags, which takes only one cycle */
602 if (rot != 4)
603 {
604 /* nothing fetched, MSR in EXECUTE (2) */
605 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
606 /* nothing fetched, MSR in EXECUTE (3) */
607 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
608 }
609 }
610
611 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
612 {
613 int i;
614 /* get pointers to arch-specific information */
615 armv4_5_common_t *armv4_5 = target->arch_info;
616 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
617 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
618
619 /* LDMIA r0-15, [r0] at debug speed
620 * register values will start to appear on 4th DCLK
621 */
622 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
623
624 /* fetch NOP, LDM in DECODE stage */
625 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
626 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
627 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
628
629 for (i = 0; i <= 15; i++)
630 {
631 if (mask & (1 << i))
632 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
633 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
634 }
635 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
636
637 }
638
639 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
640 {
641 /* get pointers to arch-specific information */
642 armv4_5_common_t *armv4_5 = target->arch_info;
643 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
644 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
645
646 /* put system-speed load-multiple into the pipeline */
647 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
648 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
649
650 }
651
652 void arm9tdmi_load_hword_reg(target_t *target, int num)
653 {
654 /* get pointers to arch-specific information */
655 armv4_5_common_t *armv4_5 = target->arch_info;
656 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
657 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
658
659 /* put system-speed load half-word into the pipeline */
660 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
661 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
662 }
663
664 void arm9tdmi_load_byte_reg(target_t *target, int num)
665 {
666 /* get pointers to arch-specific information */
667 armv4_5_common_t *armv4_5 = target->arch_info;
668 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
669 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
670
671 /* put system-speed load byte into the pipeline */
672 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
673 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
674
675 }
676
677 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
678 {
679 /* get pointers to arch-specific information */
680 armv4_5_common_t *armv4_5 = target->arch_info;
681 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
682 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
683
684 /* put system-speed store-multiple into the pipeline */
685 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
686 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
687
688 }
689
690 void arm9tdmi_store_hword_reg(target_t *target, int num)
691 {
692 /* get pointers to arch-specific information */
693 armv4_5_common_t *armv4_5 = target->arch_info;
694 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
695 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
696
697 /* put system-speed store half-word into the pipeline */
698 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
699 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
700
701 }
702
703 void arm9tdmi_store_byte_reg(target_t *target, int num)
704 {
705 /* get pointers to arch-specific information */
706 armv4_5_common_t *armv4_5 = target->arch_info;
707 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
708 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
709
710 /* put system-speed store byte into the pipeline */
711 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
712 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
713
714 }
715
716 void arm9tdmi_write_pc(target_t *target, u32 pc)
717 {
718 /* get pointers to arch-specific information */
719 armv4_5_common_t *armv4_5 = target->arch_info;
720 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
721 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
722
723 /* LDMIA r0-15, [r0] at debug speed
724 * register values will start to appear on 4th DCLK
725 */
726 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
727
728 /* fetch NOP, LDM in DECODE stage */
729 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
730 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
731 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
732 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
733 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
734 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
735 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
736 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
737 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
738 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
739 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
740
741 }
742
743 void arm9tdmi_branch_resume(target_t *target)
744 {
745 /* get pointers to arch-specific information */
746 armv4_5_common_t *armv4_5 = target->arch_info;
747 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
748 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
749
750 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
751 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
752
753 }
754
755 void arm9tdmi_branch_resume_thumb(target_t *target)
756 {
757 DEBUG("-");
758
759 /* get pointers to arch-specific information */
760 armv4_5_common_t *armv4_5 = target->arch_info;
761 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
762 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
763 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
764
765 /* LDMIA r0-15, [r0] at debug speed
766 * register values will start to appear on 4th DCLK
767 */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
769
770 /* fetch NOP, LDM in DECODE stage */
771 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
772 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
773 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
774 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
775 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
776 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
777 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
778
779 /* Branch and eXchange */
780 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
781
782 embeddedice_read_reg(dbg_stat);
783
784 /* fetch NOP, BX in DECODE stage */
785 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
786
787 embeddedice_read_reg(dbg_stat);
788
789 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
790 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
791
792 /* target is now in Thumb state */
793 embeddedice_read_reg(dbg_stat);
794
795 /* load r0 value, MOV_IM in Decode*/
796 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
797 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
798 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
799 /* fetch NOP, LDR in Execute */
800 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
801 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
802 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
803 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
804 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
805
806 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
807 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
808
809 embeddedice_read_reg(dbg_stat);
810
811 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
812 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
813
814 }
815
816 void arm9tdmi_enable_single_step(target_t *target)
817 {
818 /* get pointers to arch-specific information */
819 armv4_5_common_t *armv4_5 = target->arch_info;
820 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
821
822 if (arm7_9->has_single_step)
823 {
824 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
825 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
826 }
827 else
828 {
829 arm7_9_enable_eice_step(target);
830 }
831 }
832
833 void arm9tdmi_disable_single_step(target_t *target)
834 {
835 /* get pointers to arch-specific information */
836 armv4_5_common_t *armv4_5 = target->arch_info;
837 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
838
839 if (arm7_9->has_single_step)
840 {
841 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
842 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
843 }
844 else
845 {
846 arm7_9_disable_eice_step(target);
847 }
848 }
849
850 void arm9tdmi_build_reg_cache(target_t *target)
851 {
852 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
853 /* get pointers to arch-specific information */
854 armv4_5_common_t *armv4_5 = target->arch_info;
855 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
856 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
857
858 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
859 armv4_5->core_cache = (*cache_p);
860
861 /* one extra register (vector catch) */
862 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
863 arm7_9->eice_cache = (*cache_p)->next;
864
865 if (arm7_9->etm_ctx)
866 {
867 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
868 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
869 }
870 }
871
872 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
873 {
874
875 arm9tdmi_build_reg_cache(target);
876
877 return ERROR_OK;
878
879 }
880
881 int arm9tdmi_quit()
882 {
883
884 return ERROR_OK;
885 }
886
887 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
888 {
889 armv4_5_common_t *armv4_5;
890 arm7_9_common_t *arm7_9;
891
892 arm7_9 = &arm9tdmi->arm7_9_common;
893 armv4_5 = &arm7_9->armv4_5_common;
894
895 /* prepare JTAG information for the new target */
896 arm7_9->jtag_info.chain_pos = chain_pos;
897 arm7_9->jtag_info.scann_size = 5;
898
899 /* register arch-specific functions */
900 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
901 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
902 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
903 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
904 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
905
906 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
907 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
908 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
909
910 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
911 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
912 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
913
914 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
915 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
916 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
917
918 arm7_9->write_pc = arm9tdmi_write_pc;
919 arm7_9->branch_resume = arm9tdmi_branch_resume;
920 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
921
922 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
923 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
924
925 arm7_9->pre_debug_entry = NULL;
926 arm7_9->post_debug_entry = NULL;
927
928 arm7_9->pre_restore_context = NULL;
929 arm7_9->post_restore_context = NULL;
930
931 /* initialize arch-specific breakpoint handling */
932 arm7_9->arm_bkpt = 0xdeeedeee;
933 arm7_9->thumb_bkpt = 0xdeee;
934
935 arm7_9->sw_bkpts_use_wp = 1;
936 arm7_9->sw_bkpts_enabled = 0;
937 arm7_9->dbgreq_adjust_pc = 3;
938 arm7_9->arch_info = arm9tdmi;
939
940 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
941 arm9tdmi->arch_info = NULL;
942
943 if (variant)
944 {
945 arm9tdmi->variant = strdup(variant);
946 }
947 else
948 {
949 arm9tdmi->variant = strdup("");
950 }
951
952 arm7_9_init_arch_info(target, arm7_9);
953
954 /* override use of DBGRQ, this is safe on ARM9TDMI */
955 arm7_9->use_dbgrq = 1;
956
957 /* all ARM9s have the vector catch register */
958 arm7_9->has_vector_catch = 1;
959
960 return ERROR_OK;
961 }
962
963 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
964 {
965 armv4_5_common_t *armv4_5 = target->arch_info;
966 arm7_9_common_t *arm7_9;
967 arm9tdmi_common_t *arm9tdmi;
968
969 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
970 {
971 return -1;
972 }
973
974 arm7_9 = armv4_5->arch_info;
975 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
976 {
977 return -1;
978 }
979
980 arm9tdmi = arm7_9->arch_info;
981 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
982 {
983 return -1;
984 }
985
986 *armv4_5_p = armv4_5;
987 *arm7_9_p = arm7_9;
988 *arm9tdmi_p = arm9tdmi;
989
990 return ERROR_OK;
991 }
992
993
994 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
995 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
996 {
997 int chain_pos;
998 char *variant = NULL;
999 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
1000
1001 if (argc < 4)
1002 {
1003 ERROR("'target arm9tdmi' requires at least one additional argument");
1004 exit(-1);
1005 }
1006
1007 chain_pos = strtoul(args[3], NULL, 0);
1008
1009 if (argc >= 5)
1010 variant = args[4];
1011
1012 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1013
1014 return ERROR_OK;
1015 }
1016
1017 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1018 {
1019 int retval;
1020
1021 command_t *arm9tdmi_cmd;
1022
1023
1024 retval = arm7_9_register_commands(cmd_ctx);
1025
1026 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1027
1028 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1029
1030
1031 return ERROR_OK;
1032
1033 }
1034
1035 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1036 {
1037 target_t *target = get_current_target(cmd_ctx);
1038 armv4_5_common_t *armv4_5;
1039 arm7_9_common_t *arm7_9;
1040 arm9tdmi_common_t *arm9tdmi;
1041 reg_t *vector_catch;
1042 u32 vector_catch_value;
1043 int i, j;
1044
1045 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1046 {
1047 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1048 return ERROR_OK;
1049 }
1050
1051 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1052
1053 /* read the vector catch register if necessary */
1054 if (!vector_catch->valid)
1055 embeddedice_read_reg(vector_catch);
1056
1057 /* get the current setting */
1058 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1059
1060 if (argc > 0)
1061 {
1062 vector_catch_value = 0x0;
1063 if (strcmp(args[0], "all") == 0)
1064 {
1065 vector_catch_value = 0xdf;
1066 }
1067 else if (strcmp(args[0], "none") == 0)
1068 {
1069 /* do nothing */
1070 }
1071 else
1072 {
1073 for (i = 0; i < argc; i++)
1074 {
1075 /* go through list of vectors */
1076 for(j = 0; arm9tdmi_vectors[j].name; j++)
1077 {
1078 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1079 {
1080 vector_catch_value |= arm9tdmi_vectors[j].value;
1081 break;
1082 }
1083 }
1084
1085 /* complain if vector wasn't found */
1086 if (!arm9tdmi_vectors[j].name)
1087 {
1088 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1089
1090 /* reread current setting */
1091 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1092
1093 break;
1094 }
1095 }
1096 }
1097
1098 /* store new settings */
1099 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1100 embeddedice_store_reg(vector_catch);
1101 }
1102
1103 /* output current settings (skip RESERVED vector) */
1104 for (i = 0; i < 8; i++)
1105 {
1106 if (i != 5)
1107 {
1108 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1109 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1110 }
1111 }
1112
1113 return ERROR_OK;
1114 }
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