1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
41 #define _DEBUG_INSTRUCTION_EXECUTION_
45 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
53 target_type_t arm9tdmi_target
=
58 .arch_state
= armv4_5_arch_state
,
61 .resume
= arm7_9_resume
,
64 .assert_reset
= arm7_9_assert_reset
,
65 .deassert_reset
= arm7_9_deassert_reset
,
66 .soft_reset_halt
= arm7_9_soft_reset_halt
,
67 .prepare_reset_halt
= arm7_9_prepare_reset_halt
,
69 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
71 .read_memory
= arm7_9_read_memory
,
72 .write_memory
= arm7_9_write_memory
,
73 .bulk_write_memory
= arm7_9_bulk_write_memory
,
75 .run_algorithm
= armv4_5_run_algorithm
,
77 .add_breakpoint
= arm7_9_add_breakpoint
,
78 .remove_breakpoint
= arm7_9_remove_breakpoint
,
79 .add_watchpoint
= arm7_9_add_watchpoint
,
80 .remove_watchpoint
= arm7_9_remove_watchpoint
,
82 .register_commands
= arm9tdmi_register_commands
,
83 .target_command
= arm9tdmi_target_command
,
84 .init_target
= arm9tdmi_init_target
,
88 arm9tdmi_vector_t arm9tdmi_vectors
[] =
90 {"reset", ARM9TDMI_RESET_VECTOR
},
91 {"undef", ARM9TDMI_UNDEF_VECTOR
},
92 {"swi", ARM9TDMI_SWI_VECTOR
},
93 {"pabt", ARM9TDMI_PABT_VECTOR
},
94 {"dabt", ARM9TDMI_DABT_VECTOR
},
95 {"reserved", ARM9TDMI_RESERVED_VECTOR
},
96 {"irq", ARM9TDMI_IRQ_VECTOR
},
97 {"fiq", ARM9TDMI_FIQ_VECTOR
},
101 int arm9tdmi_jtag_error_handler(u8
*in_value
, void *priv
)
105 DEBUG("caller: %s", caller
);
110 int arm9tdmi_examine_debug_reason(target_t
*target
)
112 /* get pointers to arch-specific information */
113 armv4_5_common_t
*armv4_5
= target
->arch_info
;
114 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
116 /* only check the debug reason if we don't know it already */
117 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
118 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
120 error_handler_t error_handler
;
121 scan_field_t fields
[3];
123 u8 instructionbus
[4];
126 jtag_add_end_state(TAP_PD
);
128 fields
[0].device
= arm7_9
->jtag_info
.chain_pos
;
129 fields
[0].num_bits
= 32;
130 fields
[0].out_value
= NULL
;
131 fields
[0].out_mask
= NULL
;
132 fields
[0].in_value
= databus
;
133 fields
[0].in_check_value
= NULL
;
134 fields
[0].in_check_mask
= NULL
;
135 fields
[0].in_handler
= NULL
;
136 fields
[0].in_handler_priv
= NULL
;
138 fields
[1].device
= arm7_9
->jtag_info
.chain_pos
;
139 fields
[1].num_bits
= 3;
140 fields
[1].out_value
= NULL
;
141 fields
[1].out_mask
= NULL
;
142 fields
[1].in_value
= &debug_reason
;
143 fields
[1].in_check_value
= NULL
;
144 fields
[1].in_check_mask
= NULL
;
145 fields
[1].in_handler
= NULL
;
146 fields
[1].in_handler_priv
= NULL
;
148 fields
[2].device
= arm7_9
->jtag_info
.chain_pos
;
149 fields
[2].num_bits
= 32;
150 fields
[2].out_value
= NULL
;
151 fields
[2].out_mask
= NULL
;
152 fields
[2].in_value
= instructionbus
;
153 fields
[2].in_check_value
= NULL
;
154 fields
[2].in_check_mask
= NULL
;
155 fields
[2].in_handler
= NULL
;
156 fields
[2].in_handler_priv
= NULL
;
158 arm_jtag_scann(&arm7_9
->jtag_info
, 0x1);
159 error_handler
.error_handler
= arm9tdmi_jtag_error_handler
;
160 error_handler
.error_handler_priv
= "arm9tdmi_examine_debug_reason";
161 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, &error_handler
);
163 jtag_add_dr_scan(3, fields
, TAP_PD
, NULL
);
164 jtag_execute_queue();
166 fields
[0].in_value
= NULL
;
167 fields
[0].out_value
= databus
;
168 fields
[1].in_value
= NULL
;
169 fields
[1].out_value
= &debug_reason
;
170 fields
[2].in_value
= NULL
;
171 fields
[2].out_value
= instructionbus
;
173 jtag_add_dr_scan(3, fields
, TAP_PD
, NULL
);
175 if (debug_reason
& 0x4)
176 if (debug_reason
& 0x2)
177 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
179 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
181 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
187 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
188 int arm9tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 instr
, u32 out
, u32
*in
, int sysspeed
)
190 error_handler_t error_handler
;
191 scan_field_t fields
[3];
194 u8 sysspeed_buf
= 0x0;
197 buf_set_u32(out_buf
, 0, 32, out
);
199 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
202 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
204 jtag_add_end_state(TAP_PD
);
205 arm_jtag_scann(jtag_info
, 0x1);
207 error_handler
.error_handler
= arm9tdmi_jtag_error_handler
;
208 error_handler
.error_handler_priv
= "arm9tdmi_clock_out";
210 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, &error_handler
);
212 fields
[0].device
= jtag_info
->chain_pos
;
213 fields
[0].num_bits
= 32;
214 fields
[0].out_value
= out_buf
;
215 fields
[0].out_mask
= NULL
;
216 fields
[0].in_value
= NULL
;
219 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
220 fields
[0].in_handler_priv
= in
;
224 fields
[0].in_handler
= NULL
;
225 fields
[0].in_handler_priv
= NULL
;
227 fields
[0].in_check_value
= NULL
;
228 fields
[0].in_check_mask
= NULL
;
230 fields
[1].device
= jtag_info
->chain_pos
;
231 fields
[1].num_bits
= 3;
232 fields
[1].out_value
= &sysspeed_buf
;
233 fields
[1].out_mask
= NULL
;
234 fields
[1].in_value
= NULL
;
235 fields
[1].in_check_value
= NULL
;
236 fields
[1].in_check_mask
= NULL
;
237 fields
[1].in_handler
= NULL
;
238 fields
[1].in_handler_priv
= NULL
;
240 fields
[2].device
= jtag_info
->chain_pos
;
241 fields
[2].num_bits
= 32;
242 fields
[2].out_value
= instr_buf
;
243 fields
[2].out_mask
= NULL
;
244 fields
[2].in_value
= NULL
;
245 fields
[2].in_check_value
= NULL
;
246 fields
[2].in_check_mask
= NULL
;
247 fields
[2].in_handler
= NULL
;
248 fields
[2].in_handler_priv
= NULL
;
250 jtag_add_dr_scan(3, fields
, -1, NULL
);
252 jtag_add_runtest(0, -1);
254 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
256 jtag_execute_queue();
260 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
263 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
270 /* just read data (instruction and data-out = don't care) */
271 int arm9tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
273 scan_field_t fields
[3];
274 error_handler_t error_handler
;
276 jtag_add_end_state(TAP_PD
);
277 arm_jtag_scann(jtag_info
, 0x1);
279 error_handler
.error_handler
= arm9tdmi_jtag_error_handler
;
280 error_handler
.error_handler_priv
= "arm9tdmi_clock_data_in_endianness";
282 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, &error_handler
);
284 fields
[0].device
= jtag_info
->chain_pos
;
285 fields
[0].num_bits
= 32;
286 fields
[0].out_value
= NULL
;
287 fields
[0].out_mask
= NULL
;
288 fields
[0].in_value
= NULL
;
289 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
290 fields
[0].in_handler_priv
= in
;
291 fields
[0].in_check_value
= NULL
;
292 fields
[0].in_check_mask
= NULL
;
294 fields
[1].device
= jtag_info
->chain_pos
;
295 fields
[1].num_bits
= 3;
296 fields
[1].out_value
= NULL
;
297 fields
[1].out_mask
= NULL
;
298 fields
[1].in_value
= NULL
;
299 fields
[1].in_handler
= NULL
;
300 fields
[1].in_handler_priv
= NULL
;
301 fields
[1].in_check_value
= NULL
;
302 fields
[1].in_check_mask
= NULL
;
304 fields
[2].device
= jtag_info
->chain_pos
;
305 fields
[2].num_bits
= 32;
306 fields
[2].out_value
= NULL
;
307 fields
[2].out_mask
= NULL
;
308 fields
[2].in_value
= NULL
;
309 fields
[2].in_check_value
= NULL
;
310 fields
[2].in_check_mask
= NULL
;
311 fields
[2].in_handler
= NULL
;
312 fields
[2].in_handler_priv
= NULL
;
314 jtag_add_dr_scan(3, fields
, -1, NULL
);
316 jtag_add_runtest(0, -1);
318 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
320 jtag_execute_queue();
324 DEBUG("in: 0x%8.8x", *in
);
328 ERROR("BUG: called with in == NULL");
336 /* clock the target, and read the databus
337 * the *in pointer points to a buffer where elements of 'size' bytes
338 * are stored in big (be==1) or little (be==0) endianness
340 int arm9tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
342 scan_field_t fields
[3];
343 error_handler_t error_handler
;
345 jtag_add_end_state(TAP_PD
);
346 arm_jtag_scann(jtag_info
, 0x1);
348 error_handler
.error_handler
= arm9tdmi_jtag_error_handler
;
349 error_handler
.error_handler_priv
= "arm9tdmi_clock_data_in_endianness";
351 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, &error_handler
);
353 fields
[0].device
= jtag_info
->chain_pos
;
354 fields
[0].num_bits
= 32;
355 fields
[0].out_value
= NULL
;
356 fields
[0].out_mask
= NULL
;
357 fields
[0].in_value
= NULL
;
361 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be32
: arm_jtag_buf_to_le32
;
364 fields
[0].in_handler
= (be
) ? arm_jtag_buf_to_be16
: arm_jtag_buf_to_le16
;
367 fields
[0].in_handler
= arm_jtag_buf_to_8
;
370 fields
[0].in_handler_priv
= in
;
371 fields
[0].in_check_value
= NULL
;
372 fields
[0].in_check_mask
= NULL
;
374 fields
[1].device
= jtag_info
->chain_pos
;
375 fields
[1].num_bits
= 3;
376 fields
[1].out_value
= NULL
;
377 fields
[1].out_mask
= NULL
;
378 fields
[1].in_value
= NULL
;
379 fields
[1].in_handler
= NULL
;
380 fields
[1].in_handler_priv
= NULL
;
381 fields
[1].in_check_value
= NULL
;
382 fields
[1].in_check_mask
= NULL
;
384 fields
[2].device
= jtag_info
->chain_pos
;
385 fields
[2].num_bits
= 32;
386 fields
[2].out_value
= NULL
;
387 fields
[2].out_mask
= NULL
;
388 fields
[2].in_value
= NULL
;
389 fields
[2].in_check_value
= NULL
;
390 fields
[2].in_check_mask
= NULL
;
391 fields
[2].in_handler
= NULL
;
392 fields
[2].in_handler_priv
= NULL
;
394 jtag_add_dr_scan(3, fields
, -1, NULL
);
396 jtag_add_runtest(0, -1);
398 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
400 jtag_execute_queue();
404 DEBUG("in: 0x%8.8x", *in
);
408 ERROR("BUG: called with in == NULL");
416 void arm9tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
418 /* get pointers to arch-specific information */
419 armv4_5_common_t
*armv4_5
= target
->arch_info
;
420 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
421 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
423 /* save r0 before using it and put system in ARM state
424 * to allow common handling of ARM and THUMB debugging */
426 /* fetch STR r0, [r0] */
427 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
428 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
429 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
430 /* STR r0, [r0] in Memory */
431 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
433 /* MOV r0, r15 fetched, STR in Decode */
434 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
435 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
436 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
437 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
438 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
439 /* nothing fetched, STR r0, [r0] in Memory */
440 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
442 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
443 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
445 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
447 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
448 /* LDR in Memory (to account for interlock) */
449 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
452 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
453 /* NOP fetched, BX in Decode, MOV in Execute */
454 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
455 /* NOP fetched, BX in Execute (1) */
456 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
458 jtag_execute_queue();
460 /* fix program counter:
461 * MOV r0, r15 was the 5th instruction (+8)
462 * reading PC in Thumb state gives address of instruction + 4
467 void arm9tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
470 /* get pointers to arch-specific information */
471 armv4_5_common_t
*armv4_5
= target
->arch_info
;
472 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
473 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
475 /* STMIA r0-15, [r0] at debug speed
476 * register values will start to appear on 4th DCLK
478 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
480 /* fetch NOP, STM in DECODE stage */
481 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
482 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
483 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
485 for (i
= 0; i
<= 15; i
++)
488 /* nothing fetched, STM in MEMORY (i'th cycle) */
489 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
494 void arm9tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
497 /* get pointers to arch-specific information */
498 armv4_5_common_t
*armv4_5
= target
->arch_info
;
499 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
500 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
501 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
502 u32
*buf_u32
= buffer
;
503 u16
*buf_u16
= buffer
;
506 /* STMIA r0-15, [r0] at debug speed
507 * register values will start to appear on 4th DCLK
509 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
511 /* fetch NOP, STM in DECODE stage */
512 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
513 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
514 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
516 for (i
= 0; i
<= 15; i
++)
519 /* nothing fetched, STM in MEMORY (i'th cycle) */
523 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
526 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
529 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
536 void arm9tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
538 /* get pointers to arch-specific information */
539 armv4_5_common_t
*armv4_5
= target
->arch_info
;
540 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
541 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
544 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
545 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
546 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
547 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
548 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
551 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
552 /* fetch NOP, STR in DECODE stage */
553 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
554 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
555 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
556 /* nothing fetched, STR in MEMORY */
557 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
561 void arm9tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
563 /* get pointers to arch-specific information */
564 armv4_5_common_t
*armv4_5
= target
->arch_info
;
565 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
566 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
568 DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
571 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
572 /* MSR2 fetched, MSR1 in DECODE */
573 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
574 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
575 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
576 /* nothing fetched, MSR1 in EXECUTE (2) */
577 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
578 /* nothing fetched, MSR1 in EXECUTE (3) */
579 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
580 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
581 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
582 /* nothing fetched, MSR2 in EXECUTE (2) */
583 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
584 /* nothing fetched, MSR2 in EXECUTE (3) */
585 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
586 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
587 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
588 /* nothing fetched, MSR3 in EXECUTE (2) */
589 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
590 /* nothing fetched, MSR3 in EXECUTE (3) */
591 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
592 /* NOP fetched, MSR4 in EXECUTE (1) */
593 /* last MSR writes flags, which takes only one cycle */
594 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
597 void arm9tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
599 /* get pointers to arch-specific information */
600 armv4_5_common_t
*armv4_5
= target
->arch_info
;
601 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
602 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
604 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
607 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
608 /* NOP fetched, MSR in DECODE */
609 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
610 /* NOP fetched, MSR in EXECUTE (1) */
611 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
613 /* rot == 4 writes flags, which takes only one cycle */
616 /* nothing fetched, MSR in EXECUTE (2) */
617 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
618 /* nothing fetched, MSR in EXECUTE (3) */
619 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
623 void arm9tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
626 /* get pointers to arch-specific information */
627 armv4_5_common_t
*armv4_5
= target
->arch_info
;
628 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
629 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
631 /* LDMIA r0-15, [r0] at debug speed
632 * register values will start to appear on 4th DCLK
634 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
636 /* fetch NOP, LDM in DECODE stage */
637 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
638 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
639 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
641 for (i
= 0; i
<= 15; i
++)
644 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
645 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
647 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
651 void arm9tdmi_load_word_regs(target_t
*target
, u32 mask
)
653 /* get pointers to arch-specific information */
654 armv4_5_common_t
*armv4_5
= target
->arch_info
;
655 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
656 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
658 /* put system-speed load-multiple into the pipeline */
659 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
660 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
664 void arm9tdmi_load_hword_reg(target_t
*target
, int num
)
666 /* get pointers to arch-specific information */
667 armv4_5_common_t
*armv4_5
= target
->arch_info
;
668 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
669 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
671 /* put system-speed load half-word into the pipeline */
672 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
673 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
676 void arm9tdmi_load_byte_reg(target_t
*target
, int num
)
678 /* get pointers to arch-specific information */
679 armv4_5_common_t
*armv4_5
= target
->arch_info
;
680 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
681 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
683 /* put system-speed load byte into the pipeline */
684 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
685 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
689 void arm9tdmi_store_word_regs(target_t
*target
, u32 mask
)
691 /* get pointers to arch-specific information */
692 armv4_5_common_t
*armv4_5
= target
->arch_info
;
693 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
694 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
696 /* put system-speed store-multiple into the pipeline */
697 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
698 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
702 void arm9tdmi_store_hword_reg(target_t
*target
, int num
)
704 /* get pointers to arch-specific information */
705 armv4_5_common_t
*armv4_5
= target
->arch_info
;
706 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
707 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
709 /* put system-speed store half-word into the pipeline */
710 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
711 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
715 void arm9tdmi_store_byte_reg(target_t
*target
, int num
)
717 /* get pointers to arch-specific information */
718 armv4_5_common_t
*armv4_5
= target
->arch_info
;
719 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
720 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
722 /* put system-speed store byte into the pipeline */
723 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
724 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
728 void arm9tdmi_write_pc(target_t
*target
, u32 pc
)
730 /* get pointers to arch-specific information */
731 armv4_5_common_t
*armv4_5
= target
->arch_info
;
732 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
733 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
735 /* LDMIA r0-15, [r0] at debug speed
736 * register values will start to appear on 4th DCLK
738 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
740 /* fetch NOP, LDM in DECODE stage */
741 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
742 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
743 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
744 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
745 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
746 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
747 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
748 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
749 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
750 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
751 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
755 void arm9tdmi_branch_resume(target_t
*target
)
757 /* get pointers to arch-specific information */
758 armv4_5_common_t
*armv4_5
= target
->arch_info
;
759 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
760 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
762 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
763 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
767 void arm9tdmi_branch_resume_thumb(target_t
*target
)
771 /* get pointers to arch-specific information */
772 armv4_5_common_t
*armv4_5
= target
->arch_info
;
773 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
774 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
775 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
777 /* LDMIA r0-15, [r0] at debug speed
778 * register values will start to appear on 4th DCLK
780 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
782 /* fetch NOP, LDM in DECODE stage */
783 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
784 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
785 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
786 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
787 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
788 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
789 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
791 /* Branch and eXchange */
792 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
794 embeddedice_read_reg(dbg_stat
);
796 /* fetch NOP, BX in DECODE stage */
797 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
799 embeddedice_read_reg(dbg_stat
);
801 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
802 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
804 /* target is now in Thumb state */
805 embeddedice_read_reg(dbg_stat
);
807 /* load r0 value, MOV_IM in Decode*/
808 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
809 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
810 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
811 /* fetch NOP, LDR in Execute */
812 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
813 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
814 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
815 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
816 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
818 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
819 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
821 embeddedice_read_reg(dbg_stat
);
823 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
824 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
828 void arm9tdmi_enable_single_step(target_t
*target
)
830 /* get pointers to arch-specific information */
831 armv4_5_common_t
*armv4_5
= target
->arch_info
;
832 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
834 if (arm7_9
->has_single_step
)
836 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
837 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
841 arm7_9_enable_eice_step(target
);
845 void arm9tdmi_disable_single_step(target_t
*target
)
847 /* get pointers to arch-specific information */
848 armv4_5_common_t
*armv4_5
= target
->arch_info
;
849 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
851 if (arm7_9
->has_single_step
)
853 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
854 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
858 arm7_9_disable_eice_step(target
);
862 void arm9tdmi_build_reg_cache(target_t
*target
)
864 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
865 /* get pointers to arch-specific information */
866 armv4_5_common_t
*armv4_5
= target
->arch_info
;
867 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
868 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
870 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
871 armv4_5
->core_cache
= (*cache_p
);
873 /* one extra register (vector catch) */
874 (*cache_p
)->next
= embeddedice_build_reg_cache(target
, arm7_9
);
875 arm7_9
->eice_cache
= (*cache_p
)->next
;
879 (*cache_p
)->next
->next
= etm_build_reg_cache(target
, jtag_info
, 0);
880 arm7_9
->etm_cache
= (*cache_p
)->next
->next
;
885 (*cache_p
)->next
->next
->next
= etb_build_reg_cache(arm7_9
->etb
);
886 arm7_9
->etb
->reg_cache
= (*cache_p
)->next
->next
->next
;
890 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
893 arm9tdmi_build_reg_cache(target
);
905 int arm9tdmi_init_arch_info(target_t
*target
, arm9tdmi_common_t
*arm9tdmi
, int chain_pos
, char *variant
)
907 armv4_5_common_t
*armv4_5
;
908 arm7_9_common_t
*arm7_9
;
910 arm7_9
= &arm9tdmi
->arm7_9_common
;
911 armv4_5
= &arm7_9
->armv4_5_common
;
913 /* prepare JTAG information for the new target */
914 arm7_9
->jtag_info
.chain_pos
= chain_pos
;
915 arm7_9
->jtag_info
.scann_size
= 5;
917 /* register arch-specific functions */
918 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
919 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
920 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
921 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
922 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
924 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
925 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
926 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
928 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
929 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
930 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
932 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
933 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
934 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
936 arm7_9
->write_pc
= arm9tdmi_write_pc
;
937 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
938 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
940 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
941 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
943 arm7_9
->pre_debug_entry
= NULL
;
944 arm7_9
->post_debug_entry
= NULL
;
946 arm7_9
->pre_restore_context
= NULL
;
947 arm7_9
->post_restore_context
= NULL
;
949 /* initialize arch-specific breakpoint handling */
950 arm7_9
->arm_bkpt
= 0xdeeedeee;
951 arm7_9
->thumb_bkpt
= 0xdeee;
953 arm7_9
->sw_bkpts_use_wp
= 1;
954 arm7_9
->sw_bkpts_enabled
= 0;
955 arm7_9
->dbgreq_adjust_pc
= 3;
956 arm7_9
->arch_info
= arm9tdmi
;
958 arm9tdmi
->common_magic
= ARM9TDMI_COMMON_MAGIC
;
959 arm9tdmi
->arch_info
= NULL
;
963 arm9tdmi
->variant
= strdup(variant
);
967 arm9tdmi
->variant
= strdup("");
970 arm7_9_init_arch_info(target
, arm7_9
);
972 /* override use of DBGRQ, this is safe on ARM9TDMI */
973 arm7_9
->use_dbgrq
= 1;
975 /* all ARM9s have the vector catch register */
976 arm7_9
->has_vector_catch
= 1;
981 int arm9tdmi_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
)
983 armv4_5_common_t
*armv4_5
= target
->arch_info
;
984 arm7_9_common_t
*arm7_9
;
985 arm9tdmi_common_t
*arm9tdmi
;
987 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
992 arm7_9
= armv4_5
->arch_info
;
993 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
998 arm9tdmi
= arm7_9
->arch_info
;
999 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
1004 *armv4_5_p
= armv4_5
;
1006 *arm9tdmi_p
= arm9tdmi
;
1012 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
1013 int arm9tdmi_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
1016 char *variant
= NULL
;
1017 arm9tdmi_common_t
*arm9tdmi
= malloc(sizeof(arm9tdmi_common_t
));
1021 ERROR("'target arm9tdmi' requires at least one additional argument");
1025 chain_pos
= strtoul(args
[3], NULL
, 0);
1030 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
1035 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
)
1039 command_t
*arm9tdmi_cmd
;
1042 retval
= arm7_9_register_commands(cmd_ctx
);
1044 arm9tdmi_cmd
= register_command(cmd_ctx
, NULL
, "arm9tdmi", NULL
, COMMAND_ANY
, "arm9tdmi specific commands");
1046 register_command(cmd_ctx
, arm9tdmi_cmd
, "vector_catch", handle_arm9tdmi_catch_vectors_command
, COMMAND_EXEC
, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1053 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1055 target_t
*target
= get_current_target(cmd_ctx
);
1056 armv4_5_common_t
*armv4_5
;
1057 arm7_9_common_t
*arm7_9
;
1058 arm9tdmi_common_t
*arm9tdmi
;
1059 reg_t
*vector_catch
;
1060 u32 vector_catch_value
;
1063 if (arm9tdmi_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
) != ERROR_OK
)
1065 command_print(cmd_ctx
, "current target isn't an ARM9TDMI based target");
1069 vector_catch
= &arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
];
1071 /* read the vector catch register if necessary */
1072 if (!vector_catch
->valid
)
1073 embeddedice_read_reg(vector_catch
);
1075 /* get the current setting */
1076 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1080 vector_catch_value
= 0x0;
1081 if (strcmp(args
[0], "all") == 0)
1083 vector_catch_value
= 0xdf;
1085 else if (strcmp(args
[0], "none") == 0)
1091 for (i
= 0; i
< argc
; i
++)
1093 /* go through list of vectors */
1094 for(j
= 0; arm9tdmi_vectors
[j
].name
; j
++)
1096 if (strcmp(args
[i
], arm9tdmi_vectors
[j
].name
) == 0)
1098 vector_catch_value
|= arm9tdmi_vectors
[j
].value
;
1103 /* complain if vector wasn't found */
1104 if (!arm9tdmi_vectors
[j
].name
)
1106 command_print(cmd_ctx
, "vector '%s' not found, leaving current setting unchanged", args
[i
]);
1108 /* reread current setting */
1109 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1116 /* store new settings */
1117 buf_set_u32(vector_catch
->value
, 0, 32, vector_catch_value
);
1118 embeddedice_store_reg(vector_catch
);
1121 /* output current settings (skip RESERVED vector) */
1122 for (i
= 0; i
< 8; i
++)
1126 command_print(cmd_ctx
, "%s: %s", arm9tdmi_vectors
[i
].name
,
1127 (vector_catch_value
& (1 << i
)) ? "catch" : "don't catch");
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